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authorJaswinder Singh Rajput <jaswinder@infradead.org>2008-12-27 08:02:28 -0500
committerIngo Molnar <mingo@elte.hu>2008-12-29 12:17:36 -0500
commit824877111cd7f2b4fd2fe6947c5c5cbbb3ac5bd8 (patch)
tree4dabc2c724815a12a756947b45491b2af33737b2 /arch/x86/pci/pci.h
parentc854c91979e0717c619bc55e124d41d60d5eb3d6 (diff)
x86, pci: move arch/x86/pci/pci.h to arch/x86/include/asm/pci_x86.h
Impact: cleanup Now that arch/x86/pci/pci.h is used in a number of other places as well, move the lowlevel x86 pci definitions into the architecture include files. (not to be confused with the existing arch/x86/include/asm/pci.h file, which provides public details about x86 PCI) Tested on: X86_32_UP, X86_32_SMP and X86_64_SMP Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/pci/pci.h')
-rw-r--r--arch/x86/pci/pci.h162
1 files changed, 0 insertions, 162 deletions
diff --git a/arch/x86/pci/pci.h b/arch/x86/pci/pci.h
deleted file mode 100644
index 1959018aac02..000000000000
--- a/arch/x86/pci/pci.h
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * Low-Level PCI Access for i386 machines.
3 *
4 * (c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7#undef DEBUG
8
9#ifdef DEBUG
10#define DBG(x...) printk(x)
11#else
12#define DBG(x...)
13#endif
14
15#define PCI_PROBE_BIOS 0x0001
16#define PCI_PROBE_CONF1 0x0002
17#define PCI_PROBE_CONF2 0x0004
18#define PCI_PROBE_MMCONF 0x0008
19#define PCI_PROBE_MASK 0x000f
20#define PCI_PROBE_NOEARLY 0x0010
21
22#define PCI_NO_CHECKS 0x0400
23#define PCI_USE_PIRQ_MASK 0x0800
24#define PCI_ASSIGN_ROMS 0x1000
25#define PCI_BIOS_IRQ_SCAN 0x2000
26#define PCI_ASSIGN_ALL_BUSSES 0x4000
27#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
28#define PCI_USE__CRS 0x10000
29#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
30#define PCI_HAS_IO_ECS 0x40000
31#define PCI_NOASSIGN_ROMS 0x80000
32
33extern unsigned int pci_probe;
34extern unsigned long pirq_table_addr;
35
36enum pci_bf_sort_state {
37 pci_bf_sort_default,
38 pci_force_nobf,
39 pci_force_bf,
40 pci_dmi_bf,
41};
42
43/* pci-i386.c */
44
45extern unsigned int pcibios_max_latency;
46
47void pcibios_resource_survey(void);
48
49/* pci-pc.c */
50
51extern int pcibios_last_bus;
52extern struct pci_bus *pci_root_bus;
53extern struct pci_ops pci_root_ops;
54
55/* pci-irq.c */
56
57struct irq_info {
58 u8 bus, devfn; /* Bus, device and function */
59 struct {
60 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
61 u16 bitmap; /* Available IRQs */
62 } __attribute__((packed)) irq[4];
63 u8 slot; /* Slot number, 0=onboard */
64 u8 rfu;
65} __attribute__((packed));
66
67struct irq_routing_table {
68 u32 signature; /* PIRQ_SIGNATURE should be here */
69 u16 version; /* PIRQ_VERSION */
70 u16 size; /* Table size in bytes */
71 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
72 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
73 u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
74 u32 miniport_data; /* Crap */
75 u8 rfu[11];
76 u8 checksum; /* Modulo 256 checksum must give zero */
77 struct irq_info slots[0];
78} __attribute__((packed));
79
80extern unsigned int pcibios_irq_mask;
81
82extern int pcibios_scanned;
83extern spinlock_t pci_config_lock;
84
85extern int (*pcibios_enable_irq)(struct pci_dev *dev);
86extern void (*pcibios_disable_irq)(struct pci_dev *dev);
87
88struct pci_raw_ops {
89 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
90 int reg, int len, u32 *val);
91 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
92 int reg, int len, u32 val);
93};
94
95extern struct pci_raw_ops *raw_pci_ops;
96extern struct pci_raw_ops *raw_pci_ext_ops;
97
98extern struct pci_raw_ops pci_direct_conf1;
99extern bool port_cf9_safe;
100
101/* arch_initcall level */
102extern int pci_direct_probe(void);
103extern void pci_direct_init(int type);
104extern void pci_pcbios_init(void);
105extern int pci_olpc_init(void);
106extern void __init dmi_check_pciprobe(void);
107extern void __init dmi_check_skip_isa_align(void);
108
109/* some common used subsys_initcalls */
110extern int __init pci_acpi_init(void);
111extern int __init pcibios_irq_init(void);
112extern int __init pci_visws_init(void);
113extern int __init pci_numaq_init(void);
114extern int __init pcibios_init(void);
115
116/* pci-mmconfig.c */
117
118extern int __init pci_mmcfg_arch_init(void);
119extern void __init pci_mmcfg_arch_free(void);
120
121/*
122 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
123 * on their northbrige except through the * %eax register. As such, you MUST
124 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
125 * accessor functions.
126 * In fact just use pci_config_*, nothing else please.
127 */
128static inline unsigned char mmio_config_readb(void __iomem *pos)
129{
130 u8 val;
131 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
132 return val;
133}
134
135static inline unsigned short mmio_config_readw(void __iomem *pos)
136{
137 u16 val;
138 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
139 return val;
140}
141
142static inline unsigned int mmio_config_readl(void __iomem *pos)
143{
144 u32 val;
145 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
146 return val;
147}
148
149static inline void mmio_config_writeb(void __iomem *pos, u8 val)
150{
151 asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
152}
153
154static inline void mmio_config_writew(void __iomem *pos, u16 val)
155{
156 asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
157}
158
159static inline void mmio_config_writel(void __iomem *pos, u32 val)
160{
161 asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
162}
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