Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-bigbox-pci

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-bigbox-pci:
  x86: add pci=check_enable_amd_mmconf and dmi check
  x86: work around io allocation overlap of HT links
  acpi: get boot_cpu_id as early for k8_scan_nodes
  x86_64: don't need set default res if only have one root bus
  x86: double check the multi root bus with fam10h mmconf
  x86: multi pci root bus with different io resource range, on 64-bit
  x86: use bus conf in NB conf fun1 to get bus range on, on 64-bit
  x86: get mp_bus_to_node early
  x86 pci: remove checking type for mmconfig probe
  x86: remove unneeded check in mmconf reject
  driver core: try parent numa_node at first before using default
  x86: seperate mmconf for fam10h out from setup_64.c
  x86: if acpi=off, force setting the mmconf for fam10h
  x86_64: check MSR to get MMCONFIG for AMD Family 10h
  x86_64: check and enable MMCONFIG for AMD Family 10h
  x86_64: set cfg_size for AMD Family 10h in case MMCONFIG
  x86: mmconf enable mcfg early
  x86: clear pci_mmcfg_virt when mmcfg get rejected
  x86: validate against acpi motherboard resources

Fixed up fairly trivial conflicts in arch/x86/pci/{init.c,pci.h} due to
OLPC support manually.

1 files changed, 212 insertions, 35 deletions

diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 8d54df4dfaad..0cfebecf2a8f 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -28,7 +28,7 @@ static int __initdata pci_mmcfg_resources_inserted;
 static const char __init *pci_mmcfg_e7520(void)
 {
         u32 win;
-        pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);
+        raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
 
         win = win & 0xf000;
         if(win == 0x0000 || win == 0xf000)
@@ -53,7 +53,7 @@ static const char __init *pci_mmcfg_intel_945(void)
 
         pci_mmcfg_config_num = 1;
 
-        pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
+        raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
 
         /* Enable bit */
         if (!(pciexbar & 1))
@@ -100,33 +100,102 @@ static const char __init *pci_mmcfg_intel_945(void)
         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 }
 
+static const char __init *pci_mmcfg_amd_fam10h(void)
+{
+        u32 low, high, address;
+        u64 base, msr;
+        int i;
+        unsigned segnbits = 0, busnbits;
+
+        if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
+                return NULL;
+
+        address = MSR_FAM10H_MMIO_CONF_BASE;
+        if (rdmsr_safe(address, &low, &high))
+                return NULL;
+
+        msr = high;
+        msr <<= 32;
+        msr |= low;
+
+        /* mmconfig is not enable */
+        if (!(msr & FAM10H_MMIO_CONF_ENABLE))
+                return NULL;
+
+        base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
+
+        busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
+                         FAM10H_MMIO_CONF_BUSRANGE_MASK;
+
+        /*
+         * only handle bus 0 ?
+         * need to skip it
+         */
+        if (!busnbits)
+                return NULL;
+
+        if (busnbits > 8) {
+                segnbits = busnbits - 8;
+                busnbits = 8;
+        }
+
+        pci_mmcfg_config_num = (1 << segnbits);
+        pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
+                                   pci_mmcfg_config_num, GFP_KERNEL);
+        if (!pci_mmcfg_config)
+                return NULL;
+
+        for (i = 0; i < (1 << segnbits); i++) {
+                pci_mmcfg_config[i].address = base + (1<<28) * i;
+                pci_mmcfg_config[i].pci_segment = i;
+                pci_mmcfg_config[i].start_bus_number = 0;
+                pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
+        }
+
+        return "AMD Family 10h NB";
+}
+
 struct pci_mmcfg_hostbridge_probe {
+        u32 bus;
+        u32 devfn;
         u32 vendor;
         u32 device;
         const char *(*probe)(void);
 };
 
 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
-        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
-        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
+        { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
+          PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
+        { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
+          PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
+        { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
+          0x1200, pci_mmcfg_amd_fam10h },
+        { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
+          0x1200, pci_mmcfg_amd_fam10h },
 };
 
 static int __init pci_mmcfg_check_hostbridge(void)
 {
         u32 l;
+        u32 bus, devfn;
         u16 vendor, device;
         int i;
         const char *name;
 
-        pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0, 4, &l);
-        vendor = l & 0xffff;
-        device = (l >> 16) & 0xffff;
+        if (!raw_pci_ops)
+                return 0;
 
         pci_mmcfg_config_num = 0;
         pci_mmcfg_config = NULL;
         name = NULL;
 
         for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
+                bus =  pci_mmcfg_probes[i].bus;
+                devfn = pci_mmcfg_probes[i].devfn;
+                raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
+                vendor = l & 0xffff;
+                device = (l >> 16) & 0xffff;
+
                 if (pci_mmcfg_probes[i].vendor == vendor &&
                     pci_mmcfg_probes[i].device == device)
                         name = pci_mmcfg_probes[i].probe();
@@ -173,9 +242,78 @@ static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
         pci_mmcfg_resources_inserted = 1;
 }
 
-static void __init pci_mmcfg_reject_broken(int type)
+static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
+                                              void *data)
+{
+        struct resource *mcfg_res = data;
+        struct acpi_resource_address64 address;
+        acpi_status status;
+
+        if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
+                struct acpi_resource_fixed_memory32 *fixmem32 =
+                        &res->data.fixed_memory32;
+                if (!fixmem32)
+                        return AE_OK;
+                if ((mcfg_res->start >= fixmem32->address) &&
+                    (mcfg_res->end < (fixmem32->address +
+                                      fixmem32->address_length))) {
+                        mcfg_res->flags = 1;
+                        return AE_CTRL_TERMINATE;
+                }
+        }
+        if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
+            (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
+                return AE_OK;
+
+        status = acpi_resource_to_address64(res, &address);
+        if (ACPI_FAILURE(status) ||
+           (address.address_length <= 0) ||
+           (address.resource_type != ACPI_MEMORY_RANGE))
+                return AE_OK;
+
+        if ((mcfg_res->start >= address.minimum) &&
+            (mcfg_res->end < (address.minimum + address.address_length))) {
+                mcfg_res->flags = 1;
+                return AE_CTRL_TERMINATE;
+        }
+        return AE_OK;
+}
+
+static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
+                void *context, void **rv)
+{
+        struct resource *mcfg_res = context;
+
+        acpi_walk_resources(handle, METHOD_NAME__CRS,
+                            check_mcfg_resource, context);
+
+        if (mcfg_res->flags)
+                return AE_CTRL_TERMINATE;
+
+        return AE_OK;
+}
+
+static int __init is_acpi_reserved(unsigned long start, unsigned long end)
+{
+        struct resource mcfg_res;
+
+        mcfg_res.start = start;
+        mcfg_res.end = end;
+        mcfg_res.flags = 0;
+
+        acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
+
+        if (!mcfg_res.flags)
+                acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
+                                 NULL);
+
+        return mcfg_res.flags;
+}
+
+static void __init pci_mmcfg_reject_broken(int early)
 {
         typeof(pci_mmcfg_config[0]) *cfg;
+        int i;
 
         if ((pci_mmcfg_config_num == 0) ||
             (pci_mmcfg_config == NULL) ||
@@ -184,51 +322,80 @@ static void __init pci_mmcfg_reject_broken(int type)
 
         cfg = &pci_mmcfg_config[0];
 
-        /*
-         * Handle more broken MCFG tables on Asus etc.
-         * They only contain a single entry for bus 0-0.
-         */
-        if (pci_mmcfg_config_num == 1 &&
-            cfg->pci_segment == 0 &&
-            (cfg->start_bus_number | cfg->end_bus_number) == 0) {
-                printk(KERN_ERR "PCI: start and end of bus number is 0. "
-                       "Rejected as broken MCFG.\n");
-                goto reject;
+        for (i = 0; i < pci_mmcfg_config_num; i++) {
+                int valid = 0;
+                u32 size = (cfg->end_bus_number + 1) << 20;
+                cfg = &pci_mmcfg_config[i];
+                printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
+                       "segment %hu buses %u - %u\n",
+                       i, (unsigned long)cfg->address, cfg->pci_segment,
+                       (unsigned int)cfg->start_bus_number,
+                       (unsigned int)cfg->end_bus_number);
+
+                if (!early &&
+                    is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
+                        printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
+                               "in ACPI motherboard resources\n",
+                               cfg->address);
+                        valid = 1;
+                }
+
+                if (valid)
+                        continue;
+
+                if (!early)
+                        printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
+                               " reserved in ACPI motherboard resources\n",
+                               cfg->address);
+                /* Don't try to do this check unless configuration
+                   type 1 is available. how about type 2 ?*/
+                if (raw_pci_ops && e820_all_mapped(cfg->address,
+                                                  cfg->address + size - 1,
+                                                  E820_RESERVED)) {
+                        printk(KERN_NOTICE
+                               "PCI: MCFG area at %Lx reserved in E820\n",
+                               cfg->address);
+                        valid = 1;
+                }
+
+                if (!valid)
+                        goto reject;
         }
 
-        /*
-         * Only do this check when type 1 works. If it doesn't work
-         * assume we run on a Mac and always use MCFG
-         */
-        if (type == 1 && !e820_all_mapped(cfg->address,
-                                          cfg->address + MMCONFIG_APER_MIN,
-                                          E820_RESERVED)) {
-                printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
-                       " E820-reserved\n", cfg->address);
-                goto reject;
-        }
         return;
 
 reject:
         printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
+        pci_mmcfg_arch_free();
         kfree(pci_mmcfg_config);
         pci_mmcfg_config = NULL;
         pci_mmcfg_config_num = 0;
 }
 
-void __init pci_mmcfg_init(int type)
-{
-        int known_bridge = 0;
+static int __initdata known_bridge;
 
+void __init __pci_mmcfg_init(int early)
+{
+        /* MMCONFIG disabled */
         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
                 return;
 
-        if (type == 1 && pci_mmcfg_check_hostbridge())
-                known_bridge = 1;
+        /* MMCONFIG already enabled */
+        if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
+                return;
+
+        /* for late to exit */
+        if (known_bridge)
+                return;
+
+        if (early) {
+                if (pci_mmcfg_check_hostbridge())
+                        known_bridge = 1;
+        }
 
         if (!known_bridge) {
                 acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
-                pci_mmcfg_reject_broken(type);
+                pci_mmcfg_reject_broken(early);
         }
 
         if ((pci_mmcfg_config_num == 0) ||
@@ -249,6 +416,16 @@ void __init pci_mmcfg_init(int type)
         }
 }
 
+void __init pci_mmcfg_early_init(void)
+{
+        __pci_mmcfg_init(1);
+}
+
+void __init pci_mmcfg_late_init(void)
+{
+        __pci_mmcfg_init(0);
+}
+
 static int __init pci_mmcfg_late_insert_resources(void)
 {
         /*