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authorJiang Liu <jiang.liu@linux.intel.com>2014-06-09 04:20:01 -0400
committerThomas Gleixner <tglx@linutronix.de>2014-06-21 17:05:43 -0400
commitecc527d560cd87c74cc0bc7aff36eb72f7e18615 (patch)
treecb09c8ae51fbc58c41efd235813a372093329d25 /arch/x86/pci/intel_mid_pci.c
parent9506063992cc0785246fd314a4a40b6314685aa8 (diff)
x86, irq, SFI: Use common irqdomain map interface to program IOAPIC pins
Refine SFI to use common irqdomain map interface to program IOAPIC pins, so we can unify the callsite to progam IOAPIC pins. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: H. Peter Anvin <hpa@linux.intel.com> Cc: sfi-devel@simplefirmware.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Len Brown <lenb@kernel.org> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Link: http://lkml.kernel.org/r/1402302011-23642-33-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/pci/intel_mid_pci.c')
-rw-r--r--arch/x86/pci/intel_mid_pci.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index fcbdc5fac2c6..337d165c64f1 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -208,27 +208,22 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
208 208
209static int intel_mid_pci_irq_enable(struct pci_dev *dev) 209static int intel_mid_pci_irq_enable(struct pci_dev *dev)
210{ 210{
211 u8 pin; 211 int polarity;
212 struct io_apic_irq_attr irq_attr;
213 212
214 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 213 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
214 polarity = 0; /* active high */
215 else
216 polarity = 1; /* active low */
215 217
216 /* 218 /*
217 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to 219 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
218 * IOAPIC RTE entries, so we just enable RTE for the device. 220 * IOAPIC RTE entries, so we just enable RTE for the device.
219 */ 221 */
222 if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
223 return -EBUSY;
220 if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0) 224 if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
221 return -EBUSY; 225 return -EBUSY;
222 226
223 irq_attr.ioapic = mp_find_ioapic(dev->irq);
224 irq_attr.ioapic_pin = dev->irq;
225 irq_attr.trigger = 1; /* level */
226 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
227 irq_attr.polarity = 0; /* active high */
228 else
229 irq_attr.polarity = 1; /* active low */
230 io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
231
232 return 0; 227 return 0;
233} 228}
234 229