diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2007-10-11 05:16:36 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2007-10-11 05:16:36 -0400 |
commit | fb9aa6f1d4a1e11e66a680460b2c2b2b10b62f79 (patch) | |
tree | e0ad51f39b48a342244cef62099bd1a8a93927db /arch/x86/pci/fixup.c | |
parent | 4b60eb8380a0b588a03b6052d7ac93e1964c75b8 (diff) |
i386: move pci
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/pci/fixup.c')
-rw-r--r-- | arch/x86/pci/fixup.c | 446 |
1 files changed, 446 insertions, 0 deletions
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c new file mode 100644 index 000000000000..c82cbf4c7226 --- /dev/null +++ b/arch/x86/pci/fixup.c | |||
@@ -0,0 +1,446 @@ | |||
1 | /* | ||
2 | * Exceptions for specific devices. Usually work-arounds for fatal design flaws. | ||
3 | */ | ||
4 | |||
5 | #include <linux/delay.h> | ||
6 | #include <linux/dmi.h> | ||
7 | #include <linux/pci.h> | ||
8 | #include <linux/init.h> | ||
9 | #include "pci.h" | ||
10 | |||
11 | |||
12 | static void __devinit pci_fixup_i450nx(struct pci_dev *d) | ||
13 | { | ||
14 | /* | ||
15 | * i450NX -- Find and scan all secondary buses on all PXB's. | ||
16 | */ | ||
17 | int pxb, reg; | ||
18 | u8 busno, suba, subb; | ||
19 | |||
20 | printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d)); | ||
21 | reg = 0xd0; | ||
22 | for(pxb=0; pxb<2; pxb++) { | ||
23 | pci_read_config_byte(d, reg++, &busno); | ||
24 | pci_read_config_byte(d, reg++, &suba); | ||
25 | pci_read_config_byte(d, reg++, &subb); | ||
26 | DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb); | ||
27 | if (busno) | ||
28 | pci_scan_bus_with_sysdata(busno); /* Bus A */ | ||
29 | if (suba < subb) | ||
30 | pci_scan_bus_with_sysdata(suba+1); /* Bus B */ | ||
31 | } | ||
32 | pcibios_last_bus = -1; | ||
33 | } | ||
34 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx); | ||
35 | |||
36 | static void __devinit pci_fixup_i450gx(struct pci_dev *d) | ||
37 | { | ||
38 | /* | ||
39 | * i450GX and i450KX -- Find and scan all secondary buses. | ||
40 | * (called separately for each PCI bridge found) | ||
41 | */ | ||
42 | u8 busno; | ||
43 | pci_read_config_byte(d, 0x4a, &busno); | ||
44 | printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno); | ||
45 | pci_scan_bus_with_sysdata(busno); | ||
46 | pcibios_last_bus = -1; | ||
47 | } | ||
48 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx); | ||
49 | |||
50 | static void __devinit pci_fixup_umc_ide(struct pci_dev *d) | ||
51 | { | ||
52 | /* | ||
53 | * UM8886BF IDE controller sets region type bits incorrectly, | ||
54 | * therefore they look like memory despite of them being I/O. | ||
55 | */ | ||
56 | int i; | ||
57 | |||
58 | printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d)); | ||
59 | for(i=0; i<4; i++) | ||
60 | d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; | ||
61 | } | ||
62 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); | ||
63 | |||
64 | static void __devinit pci_fixup_ncr53c810(struct pci_dev *d) | ||
65 | { | ||
66 | /* | ||
67 | * NCR 53C810 returns class code 0 (at least on some systems). | ||
68 | * Fix class to be PCI_CLASS_STORAGE_SCSI | ||
69 | */ | ||
70 | if (!d->class) { | ||
71 | printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d)); | ||
72 | d->class = PCI_CLASS_STORAGE_SCSI << 8; | ||
73 | } | ||
74 | } | ||
75 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810); | ||
76 | |||
77 | static void __devinit pci_fixup_latency(struct pci_dev *d) | ||
78 | { | ||
79 | /* | ||
80 | * SiS 5597 and 5598 chipsets require latency timer set to | ||
81 | * at most 32 to avoid lockups. | ||
82 | */ | ||
83 | DBG("PCI: Setting max latency to 32\n"); | ||
84 | pcibios_max_latency = 32; | ||
85 | } | ||
86 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); | ||
87 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); | ||
88 | |||
89 | static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d) | ||
90 | { | ||
91 | /* | ||
92 | * PIIX4 ACPI device: hardwired IRQ9 | ||
93 | */ | ||
94 | d->irq = 9; | ||
95 | } | ||
96 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi); | ||
97 | |||
98 | /* | ||
99 | * Addresses issues with problems in the memory write queue timer in | ||
100 | * certain VIA Northbridges. This bugfix is per VIA's specifications, | ||
101 | * except for the KL133/KM133: clearing bit 5 on those Northbridges seems | ||
102 | * to trigger a bug in its integrated ProSavage video card, which | ||
103 | * causes screen corruption. We only clear bits 6 and 7 for that chipset, | ||
104 | * until VIA can provide us with definitive information on why screen | ||
105 | * corruption occurs, and what exactly those bits do. | ||
106 | * | ||
107 | * VIA 8363,8622,8361 Northbridges: | ||
108 | * - bits 5, 6, 7 at offset 0x55 need to be turned off | ||
109 | * VIA 8367 (KT266x) Northbridges: | ||
110 | * - bits 5, 6, 7 at offset 0x95 need to be turned off | ||
111 | * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: | ||
112 | * - bits 6, 7 at offset 0x55 need to be turned off | ||
113 | */ | ||
114 | |||
115 | #define VIA_8363_KL133_REVISION_ID 0x81 | ||
116 | #define VIA_8363_KM133_REVISION_ID 0x84 | ||
117 | |||
118 | static void pci_fixup_via_northbridge_bug(struct pci_dev *d) | ||
119 | { | ||
120 | u8 v; | ||
121 | int where = 0x55; | ||
122 | int mask = 0x1f; /* clear bits 5, 6, 7 by default */ | ||
123 | |||
124 | if (d->device == PCI_DEVICE_ID_VIA_8367_0) { | ||
125 | /* fix pci bus latency issues resulted by NB bios error | ||
126 | it appears on bug free^Wreduced kt266x's bios forces | ||
127 | NB latency to zero */ | ||
128 | pci_write_config_byte(d, PCI_LATENCY_TIMER, 0); | ||
129 | |||
130 | where = 0x95; /* the memory write queue timer register is | ||
131 | different for the KT266x's: 0x95 not 0x55 */ | ||
132 | } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 && | ||
133 | (d->revision == VIA_8363_KL133_REVISION_ID || | ||
134 | d->revision == VIA_8363_KM133_REVISION_ID)) { | ||
135 | mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 | ||
136 | causes screen corruption on the KL133/KM133 */ | ||
137 | } | ||
138 | |||
139 | pci_read_config_byte(d, where, &v); | ||
140 | if (v & ~mask) { | ||
141 | printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ | ||
142 | d->device, d->revision, where, v, mask, v & mask); | ||
143 | v &= mask; | ||
144 | pci_write_config_byte(d, where, v); | ||
145 | } | ||
146 | } | ||
147 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); | ||
148 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); | ||
149 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); | ||
150 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); | ||
151 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); | ||
152 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); | ||
153 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); | ||
154 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); | ||
155 | |||
156 | /* | ||
157 | * For some reasons Intel decided that certain parts of their | ||
158 | * 815, 845 and some other chipsets must look like PCI-to-PCI bridges | ||
159 | * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, | ||
160 | * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according | ||
161 | * to Intel terminology. These devices do forward all addresses from | ||
162 | * system to PCI bus no matter what are their window settings, so they are | ||
163 | * "transparent" (or subtractive decoding) from programmers point of view. | ||
164 | */ | ||
165 | static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev) | ||
166 | { | ||
167 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && | ||
168 | (dev->device & 0xff00) == 0x2400) | ||
169 | dev->transparent = 1; | ||
170 | } | ||
171 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge); | ||
172 | |||
173 | /* | ||
174 | * Fixup for C1 Halt Disconnect problem on nForce2 systems. | ||
175 | * | ||
176 | * From information provided by "Allen Martin" <AMartin@nvidia.com>: | ||
177 | * | ||
178 | * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle | ||
179 | * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns. | ||
180 | * This allows the state-machine and timer to return to a proper state within | ||
181 | * 80 ns of the CONNECT and probe appearing together. Since the CPU will not | ||
182 | * issue another HALT within 80 ns of the initial HALT, the failure condition | ||
183 | * is avoided. | ||
184 | */ | ||
185 | static void pci_fixup_nforce2(struct pci_dev *dev) | ||
186 | { | ||
187 | u32 val; | ||
188 | |||
189 | /* | ||
190 | * Chip Old value New value | ||
191 | * C17 0x1F0FFF01 0x1F01FF01 | ||
192 | * C18D 0x9F0FFF01 0x9F01FF01 | ||
193 | * | ||
194 | * Northbridge chip version may be determined by | ||
195 | * reading the PCI revision ID (0xC1 or greater is C18D). | ||
196 | */ | ||
197 | pci_read_config_dword(dev, 0x6c, &val); | ||
198 | |||
199 | /* | ||
200 | * Apply fixup if needed, but don't touch disconnect state | ||
201 | */ | ||
202 | if ((val & 0x00FF0000) != 0x00010000) { | ||
203 | printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n"); | ||
204 | pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); | ||
205 | } | ||
206 | } | ||
207 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); | ||
208 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); | ||
209 | |||
210 | /* Max PCI Express root ports */ | ||
211 | #define MAX_PCIEROOT 6 | ||
212 | static int quirk_aspm_offset[MAX_PCIEROOT << 3]; | ||
213 | |||
214 | #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7)) | ||
215 | |||
216 | static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) | ||
217 | { | ||
218 | return raw_pci_ops->read(0, bus->number, devfn, where, size, value); | ||
219 | } | ||
220 | |||
221 | /* | ||
222 | * Replace the original pci bus ops for write with a new one that will filter | ||
223 | * the request to insure ASPM cannot be enabled. | ||
224 | */ | ||
225 | static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) | ||
226 | { | ||
227 | u8 offset; | ||
228 | |||
229 | offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)]; | ||
230 | |||
231 | if ((offset) && (where == offset)) | ||
232 | value = value & 0xfffffffc; | ||
233 | |||
234 | return raw_pci_ops->write(0, bus->number, devfn, where, size, value); | ||
235 | } | ||
236 | |||
237 | static struct pci_ops quirk_pcie_aspm_ops = { | ||
238 | .read = quirk_pcie_aspm_read, | ||
239 | .write = quirk_pcie_aspm_write, | ||
240 | }; | ||
241 | |||
242 | /* | ||
243 | * Prevents PCI Express ASPM (Active State Power Management) being enabled. | ||
244 | * | ||
245 | * Save the register offset, where the ASPM control bits are located, | ||
246 | * for each PCI Express device that is in the device list of | ||
247 | * the root port in an array for fast indexing. Replace the bus ops | ||
248 | * with the modified one. | ||
249 | */ | ||
250 | static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) | ||
251 | { | ||
252 | int cap_base, i; | ||
253 | struct pci_bus *pbus; | ||
254 | struct pci_dev *dev; | ||
255 | |||
256 | if ((pbus = pdev->subordinate) == NULL) | ||
257 | return; | ||
258 | |||
259 | /* | ||
260 | * Check if the DID of pdev matches one of the six root ports. This | ||
261 | * check is needed in the case this function is called directly by the | ||
262 | * hot-plug driver. | ||
263 | */ | ||
264 | if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) || | ||
265 | (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1)) | ||
266 | return; | ||
267 | |||
268 | if (list_empty(&pbus->devices)) { | ||
269 | /* | ||
270 | * If no device is attached to the root port at power-up or | ||
271 | * after hot-remove, the pbus->devices is empty and this code | ||
272 | * will set the offsets to zero and the bus ops to parent's bus | ||
273 | * ops, which is unmodified. | ||
274 | */ | ||
275 | for (i= GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) | ||
276 | quirk_aspm_offset[i] = 0; | ||
277 | |||
278 | pbus->ops = pbus->parent->ops; | ||
279 | } else { | ||
280 | /* | ||
281 | * If devices are attached to the root port at power-up or | ||
282 | * after hot-add, the code loops through the device list of | ||
283 | * each root port to save the register offsets and replace the | ||
284 | * bus ops. | ||
285 | */ | ||
286 | list_for_each_entry(dev, &pbus->devices, bus_list) { | ||
287 | /* There are 0 to 8 devices attached to this bus */ | ||
288 | cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP); | ||
289 | quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)]= cap_base + 0x10; | ||
290 | } | ||
291 | pbus->ops = &quirk_pcie_aspm_ops; | ||
292 | } | ||
293 | } | ||
294 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk ); | ||
295 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk ); | ||
296 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk ); | ||
297 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk ); | ||
298 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk ); | ||
299 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk ); | ||
300 | |||
301 | /* | ||
302 | * Fixup to mark boot BIOS video selected by BIOS before it changes | ||
303 | * | ||
304 | * From information provided by "Jon Smirl" <jonsmirl@gmail.com> | ||
305 | * | ||
306 | * The standard boot ROM sequence for an x86 machine uses the BIOS | ||
307 | * to select an initial video card for boot display. This boot video | ||
308 | * card will have it's BIOS copied to C0000 in system RAM. | ||
309 | * IORESOURCE_ROM_SHADOW is used to associate the boot video | ||
310 | * card with this copy. On laptops this copy has to be used since | ||
311 | * the main ROM may be compressed or combined with another image. | ||
312 | * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW | ||
313 | * is marked here since the boot video device will be the only enabled | ||
314 | * video device at this point. | ||
315 | */ | ||
316 | |||
317 | static void __devinit pci_fixup_video(struct pci_dev *pdev) | ||
318 | { | ||
319 | struct pci_dev *bridge; | ||
320 | struct pci_bus *bus; | ||
321 | u16 config; | ||
322 | |||
323 | if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA) | ||
324 | return; | ||
325 | |||
326 | /* Is VGA routed to us? */ | ||
327 | bus = pdev->bus; | ||
328 | while (bus) { | ||
329 | bridge = bus->self; | ||
330 | |||
331 | /* | ||
332 | * From information provided by | ||
333 | * "David Miller" <davem@davemloft.net> | ||
334 | * The bridge control register is valid for PCI header | ||
335 | * type BRIDGE, or CARDBUS. Host to PCI controllers use | ||
336 | * PCI header type NORMAL. | ||
337 | */ | ||
338 | if (bridge | ||
339 | &&((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE) | ||
340 | ||(bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) { | ||
341 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | ||
342 | &config); | ||
343 | if (!(config & PCI_BRIDGE_CTL_VGA)) | ||
344 | return; | ||
345 | } | ||
346 | bus = bus->parent; | ||
347 | } | ||
348 | pci_read_config_word(pdev, PCI_COMMAND, &config); | ||
349 | if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { | ||
350 | pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW; | ||
351 | printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev)); | ||
352 | } | ||
353 | } | ||
354 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); | ||
355 | |||
356 | /* | ||
357 | * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A. | ||
358 | * | ||
359 | * We pretend to bring them out of full D3 state, and restore the proper | ||
360 | * IRQ, PCI cache line size, and BARs, otherwise the device won't function | ||
361 | * properly. In some cases, the device will generate an interrupt on | ||
362 | * the wrong IRQ line, causing any devices sharing the line it's | ||
363 | * *supposed* to use to be disabled by the kernel's IRQ debug code. | ||
364 | */ | ||
365 | static u16 toshiba_line_size; | ||
366 | |||
367 | static struct dmi_system_id __devinitdata toshiba_ohci1394_dmi_table[] = { | ||
368 | { | ||
369 | .ident = "Toshiba PS5 based laptop", | ||
370 | .matches = { | ||
371 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
372 | DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"), | ||
373 | }, | ||
374 | }, | ||
375 | { | ||
376 | .ident = "Toshiba PSM4 based laptop", | ||
377 | .matches = { | ||
378 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
379 | DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"), | ||
380 | }, | ||
381 | }, | ||
382 | { | ||
383 | .ident = "Toshiba A40 based laptop", | ||
384 | .matches = { | ||
385 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
386 | DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"), | ||
387 | }, | ||
388 | }, | ||
389 | { } | ||
390 | }; | ||
391 | |||
392 | static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev) | ||
393 | { | ||
394 | if (!dmi_check_system(toshiba_ohci1394_dmi_table)) | ||
395 | return; /* only applies to certain Toshibas (so far) */ | ||
396 | |||
397 | dev->current_state = PCI_D3cold; | ||
398 | pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size); | ||
399 | } | ||
400 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032, | ||
401 | pci_pre_fixup_toshiba_ohci1394); | ||
402 | |||
403 | static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev) | ||
404 | { | ||
405 | if (!dmi_check_system(toshiba_ohci1394_dmi_table)) | ||
406 | return; /* only applies to certain Toshibas (so far) */ | ||
407 | |||
408 | /* Restore config space on Toshiba laptops */ | ||
409 | pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size); | ||
410 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq); | ||
411 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, | ||
412 | pci_resource_start(dev, 0)); | ||
413 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, | ||
414 | pci_resource_start(dev, 1)); | ||
415 | } | ||
416 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032, | ||
417 | pci_post_fixup_toshiba_ohci1394); | ||
418 | |||
419 | |||
420 | /* | ||
421 | * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device | ||
422 | * configuration space. | ||
423 | */ | ||
424 | static void pci_early_fixup_cyrix_5530(struct pci_dev *dev) | ||
425 | { | ||
426 | u8 r; | ||
427 | /* clear 'F4 Video Configuration Trap' bit */ | ||
428 | pci_read_config_byte(dev, 0x42, &r); | ||
429 | r &= 0xfd; | ||
430 | pci_write_config_byte(dev, 0x42, r); | ||
431 | } | ||
432 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, | ||
433 | pci_early_fixup_cyrix_5530); | ||
434 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, | ||
435 | pci_early_fixup_cyrix_5530); | ||
436 | |||
437 | /* | ||
438 | * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller: | ||
439 | * prevent update of the BAR0, which doesn't look like a normal BAR. | ||
440 | */ | ||
441 | static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev) | ||
442 | { | ||
443 | dev->resource[0].flags |= IORESOURCE_PCI_FIXED; | ||
444 | } | ||
445 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, | ||
446 | pci_siemens_interrupt_controller); | ||