Merge branch 'oprofile-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'oprofile-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (24 commits)
  oprofile/x86: make AMD IBS hotplug capable
  oprofile/x86: notify cpus only when daemon is running
  oprofile/x86: reordering some functions
  oprofile/x86: stop disabled counters in nmi handler
  oprofile/x86: protect cpu hotplug sections
  oprofile/x86: remove CONFIG_SMP macros
  oprofile/x86: fix uninitialized counter usage during cpu hotplug
  oprofile/x86: remove duplicate IBS capability check
  oprofile/x86: move IBS code
  oprofile/x86: return -EBUSY if counters are already reserved
  oprofile/x86: moving shutdown functions
  oprofile/x86: reserve counter msrs pairwise
  oprofile/x86: rework error handler in nmi_setup()
  oprofile: update file list in MAINTAINERS file
  oprofile: protect from not being in an IRQ context
  oprofile: remove double ring buffering
  ring-buffer: Add lost event count to end of sub buffer
  tracing: Show the lost events in the trace_pipe output
  ring-buffer: Add place holder recording of dropped events
  tracing: Fix compile error in module tracepoints when MODULE_UNLOAD not set
  ...

5 files changed, 321 insertions, 291 deletions

diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 2c505ee71014..b28d2f1253bb 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -31,8 +31,9 @@ static struct op_x86_model_spec *model;
 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
 
-/* 0 == registered but off, 1 == registered and on */
-static int nmi_enabled = 0;
+/* must be protected with get_online_cpus()/put_online_cpus(): */
+static int nmi_enabled;
+static int ctr_running;
 
 struct op_counter_config counter_config[OP_MAX_COUNTER];
 
@@ -61,12 +62,16 @@ static int profile_exceptions_notify(struct notifier_block *self,
 {
         struct die_args *args = (struct die_args *)data;
         int ret = NOTIFY_DONE;
-        int cpu = smp_processor_id();
 
         switch (val) {
         case DIE_NMI:
         case DIE_NMI_IPI:
-                model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
+                if (ctr_running)
+                        model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs));
+                else if (!nmi_enabled)
+                        break;
+                else
+                        model->stop(&__get_cpu_var(cpu_msrs));
                 ret = NOTIFY_STOP;
                 break;
         default:
@@ -95,24 +100,36 @@ static void nmi_cpu_save_registers(struct op_msrs *msrs)
 static void nmi_cpu_start(void *dummy)
 {
         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
-        model->start(msrs);
+        if (!msrs->controls)
+                WARN_ON_ONCE(1);
+        else
+                model->start(msrs);
 }
 
 static int nmi_start(void)
 {
+        get_online_cpus();
         on_each_cpu(nmi_cpu_start, NULL, 1);
+        ctr_running = 1;
+        put_online_cpus();
         return 0;
 }
 
 static void nmi_cpu_stop(void *dummy)
 {
         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
-        model->stop(msrs);
+        if (!msrs->controls)
+                WARN_ON_ONCE(1);
+        else
+                model->stop(msrs);
 }
 
 static void nmi_stop(void)
 {
+        get_online_cpus();
         on_each_cpu(nmi_cpu_stop, NULL, 1);
+        ctr_running = 0;
+        put_online_cpus();
 }
 
 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
@@ -252,7 +269,10 @@ static int nmi_switch_event(void)
         if (nmi_multiplex_on() < 0)
                 return -EINVAL;         /* not necessary */
 
-        on_each_cpu(nmi_cpu_switch, NULL, 1);
+        get_online_cpus();
+        if (ctr_running)
+                on_each_cpu(nmi_cpu_switch, NULL, 1);
+        put_online_cpus();
 
         return 0;
 }
@@ -295,6 +315,7 @@ static void free_msrs(void)
                 kfree(per_cpu(cpu_msrs, i).controls);
                 per_cpu(cpu_msrs, i).controls = NULL;
         }
+        nmi_shutdown_mux();
 }
 
 static int allocate_msrs(void)
@@ -307,14 +328,21 @@ static int allocate_msrs(void)
                 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
                                                         GFP_KERNEL);
                 if (!per_cpu(cpu_msrs, i).counters)
-                        return 0;
+                        goto fail;
                 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
                                                         GFP_KERNEL);
                 if (!per_cpu(cpu_msrs, i).controls)
-                        return 0;
+                        goto fail;
         }
 
+        if (!nmi_setup_mux())
+                goto fail;
+
         return 1;
+
+fail:
+        free_msrs();
+        return 0;
 }
 
 static void nmi_cpu_setup(void *dummy)
@@ -336,49 +364,6 @@ static struct notifier_block profile_exceptions_nb = {
         .priority = 2
 };
 
-static int nmi_setup(void)
-{
-        int err = 0;
-        int cpu;
-
-        if (!allocate_msrs())
-                err = -ENOMEM;
-        else if (!nmi_setup_mux())
-                err = -ENOMEM;
-        else
-                err = register_die_notifier(&profile_exceptions_nb);
-
-        if (err) {
-                free_msrs();
-                nmi_shutdown_mux();
-                return err;
-        }
-
-        /* We need to serialize save and setup for HT because the subset
-         * of msrs are distinct for save and setup operations
-         */
-
-        /* Assume saved/restored counters are the same on all CPUs */
-        model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
-        for_each_possible_cpu(cpu) {
-                if (!cpu)
-                        continue;
-
-                memcpy(per_cpu(cpu_msrs, cpu).counters,
-                       per_cpu(cpu_msrs, 0).counters,
-                       sizeof(struct op_msr) * model->num_counters);
-
-                memcpy(per_cpu(cpu_msrs, cpu).controls,
-                       per_cpu(cpu_msrs, 0).controls,
-                       sizeof(struct op_msr) * model->num_controls);
-
-                mux_clone(cpu);
-        }
-        on_each_cpu(nmi_cpu_setup, NULL, 1);
-        nmi_enabled = 1;
-        return 0;
-}
-
 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 {
         struct op_msr *counters = msrs->counters;
@@ -412,20 +397,24 @@ static void nmi_cpu_shutdown(void *dummy)
         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
         apic_write(APIC_LVTERR, v);
         nmi_cpu_restore_registers(msrs);
+        if (model->cpu_down)
+                model->cpu_down();
 }
 
-static void nmi_shutdown(void)
+static void nmi_cpu_up(void *dummy)
 {
-        struct op_msrs *msrs;
+        if (nmi_enabled)
+                nmi_cpu_setup(dummy);
+        if (ctr_running)
+                nmi_cpu_start(dummy);
+}
 
-        nmi_enabled = 0;
-        on_each_cpu(nmi_cpu_shutdown, NULL, 1);
-        unregister_die_notifier(&profile_exceptions_nb);
-        nmi_shutdown_mux();
-        msrs = &get_cpu_var(cpu_msrs);
-        model->shutdown(msrs);
-        free_msrs();
-        put_cpu_var(cpu_msrs);
+static void nmi_cpu_down(void *dummy)
+{
+        if (ctr_running)
+                nmi_cpu_stop(dummy);
+        if (nmi_enabled)
+                nmi_cpu_shutdown(dummy);
 }
 
 static int nmi_create_files(struct super_block *sb, struct dentry *root)
@@ -457,7 +446,6 @@ static int nmi_create_files(struct super_block *sb, struct dentry *root)
         return 0;
 }
 
-#ifdef CONFIG_SMP
 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
                                  void *data)
 {
@@ -465,10 +453,10 @@ static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
         switch (action) {
         case CPU_DOWN_FAILED:
         case CPU_ONLINE:
-                smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
+                smp_call_function_single(cpu, nmi_cpu_up, NULL, 0);
                 break;
         case CPU_DOWN_PREPARE:
-                smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
+                smp_call_function_single(cpu, nmi_cpu_down, NULL, 1);
                 break;
         }
         return NOTIFY_DONE;
@@ -477,7 +465,75 @@ static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 static struct notifier_block oprofile_cpu_nb = {
         .notifier_call = oprofile_cpu_notifier
 };
-#endif
+
+static int nmi_setup(void)
+{
+        int err = 0;
+        int cpu;
+
+        if (!allocate_msrs())
+                return -ENOMEM;
+
+        /* We need to serialize save and setup for HT because the subset
+         * of msrs are distinct for save and setup operations
+         */
+
+        /* Assume saved/restored counters are the same on all CPUs */
+        err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
+        if (err)
+                goto fail;
+
+        for_each_possible_cpu(cpu) {
+                if (!cpu)
+                        continue;
+
+                memcpy(per_cpu(cpu_msrs, cpu).counters,
+                       per_cpu(cpu_msrs, 0).counters,
+                       sizeof(struct op_msr) * model->num_counters);
+
+                memcpy(per_cpu(cpu_msrs, cpu).controls,
+                       per_cpu(cpu_msrs, 0).controls,
+                       sizeof(struct op_msr) * model->num_controls);
+
+                mux_clone(cpu);
+        }
+
+        nmi_enabled = 0;
+        ctr_running = 0;
+        barrier();
+        err = register_die_notifier(&profile_exceptions_nb);
+        if (err)
+                goto fail;
+
+        get_online_cpus();
+        register_cpu_notifier(&oprofile_cpu_nb);
+        on_each_cpu(nmi_cpu_setup, NULL, 1);
+        nmi_enabled = 1;
+        put_online_cpus();
+
+        return 0;
+fail:
+        free_msrs();
+        return err;
+}
+
+static void nmi_shutdown(void)
+{
+        struct op_msrs *msrs;
+
+        get_online_cpus();
+        unregister_cpu_notifier(&oprofile_cpu_nb);
+        on_each_cpu(nmi_cpu_shutdown, NULL, 1);
+        nmi_enabled = 0;
+        ctr_running = 0;
+        put_online_cpus();
+        barrier();
+        unregister_die_notifier(&profile_exceptions_nb);
+        msrs = &get_cpu_var(cpu_msrs);
+        model->shutdown(msrs);
+        free_msrs();
+        put_cpu_var(cpu_msrs);
+}
 
 #ifdef CONFIG_PM
 
@@ -687,9 +743,6 @@ int __init op_nmi_init(struct oprofile_operations *ops)
                 return -ENODEV;
         }
 
-#ifdef CONFIG_SMP
-        register_cpu_notifier(&oprofile_cpu_nb);
-#endif
         /* default values, can be overwritten by model */
         ops->create_files       = nmi_create_files;
         ops->setup              = nmi_setup;
@@ -716,12 +769,6 @@ int __init op_nmi_init(struct oprofile_operations *ops)
 
 void op_nmi_exit(void)
 {
-        if (using_nmi) {
+        if (using_nmi)
                 exit_sysfs();
-#ifdef CONFIG_SMP
-                unregister_cpu_notifier(&oprofile_cpu_nb);
-#endif
-        }
-        if (model->exit)
-                model->exit();
 }
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 090cbbec7dbd..b67a6b5aa8d4 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -30,13 +30,10 @@
 #include "op_counter.h"
 
 #define NUM_COUNTERS 4
-#define NUM_CONTROLS 4
 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 #define NUM_VIRT_COUNTERS 32
-#define NUM_VIRT_CONTROLS 32
 #else
 #define NUM_VIRT_COUNTERS NUM_COUNTERS
-#define NUM_VIRT_CONTROLS NUM_CONTROLS
 #endif
 
 #define OP_EVENT_MASK                   0x0FFF
@@ -105,102 +102,6 @@ static u32 get_ibs_caps(void)
         return ibs_caps;
 }
 
-#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
-
-static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
-                               struct op_msrs const * const msrs)
-{
-        u64 val;
-        int i;
-
-        /* enable active counters */
-        for (i = 0; i < NUM_COUNTERS; ++i) {
-                int virt = op_x86_phys_to_virt(i);
-                if (!reset_value[virt])
-                        continue;
-                rdmsrl(msrs->controls[i].addr, val);
-                val &= model->reserved;
-                val |= op_x86_get_ctrl(model, &counter_config[virt]);
-                wrmsrl(msrs->controls[i].addr, val);
-        }
-}
-
-#endif
-
-/* functions for op_amd_spec */
-
-static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
-{
-        int i;
-
-        for (i = 0; i < NUM_COUNTERS; i++) {
-                if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
-                        msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
-        }
-
-        for (i = 0; i < NUM_CONTROLS; i++) {
-                if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
-                        msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
-        }
-}
-
-static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
-                              struct op_msrs const * const msrs)
-{
-        u64 val;
-        int i;
-
-        /* setup reset_value */
-        for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
-                if (counter_config[i].enabled
-                    && msrs->counters[op_x86_virt_to_phys(i)].addr)
-                        reset_value[i] = counter_config[i].count;
-                else
-                        reset_value[i] = 0;
-        }
-
-        /* clear all counters */
-        for (i = 0; i < NUM_CONTROLS; ++i) {
-                if (unlikely(!msrs->controls[i].addr)) {
-                        if (counter_config[i].enabled && !smp_processor_id())
-                                /*
-                                 * counter is reserved, this is on all
-                                 * cpus, so report only for cpu #0
-                                 */
-                                op_x86_warn_reserved(i);
-                        continue;
-                }
-                rdmsrl(msrs->controls[i].addr, val);
-                if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
-                        op_x86_warn_in_use(i);
-                val &= model->reserved;
-                wrmsrl(msrs->controls[i].addr, val);
-        }
-
-        /* avoid a false detection of ctr overflows in NMI handler */
-        for (i = 0; i < NUM_COUNTERS; ++i) {
-                if (unlikely(!msrs->counters[i].addr))
-                        continue;
-                wrmsrl(msrs->counters[i].addr, -1LL);
-        }
-
-        /* enable active counters */
-        for (i = 0; i < NUM_COUNTERS; ++i) {
-                int virt = op_x86_phys_to_virt(i);
-                if (!reset_value[virt])
-                        continue;
-
-                /* setup counter registers */
-                wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
-
-                /* setup control registers */
-                rdmsrl(msrs->controls[i].addr, val);
-                val &= model->reserved;
-                val |= op_x86_get_ctrl(model, &counter_config[virt]);
-                wrmsrl(msrs->controls[i].addr, val);
-        }
-}
-
 /*
  * 16-bit Linear Feedback Shift Register (LFSR)
  *
@@ -365,6 +266,125 @@ static void op_amd_stop_ibs(void)
                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 }
 
+#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+
+static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
+                               struct op_msrs const * const msrs)
+{
+        u64 val;
+        int i;
+
+        /* enable active counters */
+        for (i = 0; i < NUM_COUNTERS; ++i) {
+                int virt = op_x86_phys_to_virt(i);
+                if (!reset_value[virt])
+                        continue;
+                rdmsrl(msrs->controls[i].addr, val);
+                val &= model->reserved;
+                val |= op_x86_get_ctrl(model, &counter_config[virt]);
+                wrmsrl(msrs->controls[i].addr, val);
+        }
+}
+
+#endif
+
+/* functions for op_amd_spec */
+
+static void op_amd_shutdown(struct op_msrs const * const msrs)
+{
+        int i;
+
+        for (i = 0; i < NUM_COUNTERS; ++i) {
+                if (!msrs->counters[i].addr)
+                        continue;
+                release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
+                release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
+        }
+}
+
+static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
+{
+        int i;
+
+        for (i = 0; i < NUM_COUNTERS; i++) {
+                if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
+                        goto fail;
+                if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
+                        release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
+                        goto fail;
+                }
+                /* both registers must be reserved */
+                msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
+                msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
+                continue;
+        fail:
+                if (!counter_config[i].enabled)
+                        continue;
+                op_x86_warn_reserved(i);
+                op_amd_shutdown(msrs);
+                return -EBUSY;
+        }
+
+        return 0;
+}
+
+static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
+                              struct op_msrs const * const msrs)
+{
+        u64 val;
+        int i;
+
+        /* setup reset_value */
+        for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
+                if (counter_config[i].enabled
+                    && msrs->counters[op_x86_virt_to_phys(i)].addr)
+                        reset_value[i] = counter_config[i].count;
+                else
+                        reset_value[i] = 0;
+        }
+
+        /* clear all counters */
+        for (i = 0; i < NUM_COUNTERS; ++i) {
+                if (!msrs->controls[i].addr)
+                        continue;
+                rdmsrl(msrs->controls[i].addr, val);
+                if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
+                        op_x86_warn_in_use(i);
+                val &= model->reserved;
+                wrmsrl(msrs->controls[i].addr, val);
+                /*
+                 * avoid a false detection of ctr overflows in NMI
+                 * handler
+                 */
+                wrmsrl(msrs->counters[i].addr, -1LL);
+        }
+
+        /* enable active counters */
+        for (i = 0; i < NUM_COUNTERS; ++i) {
+                int virt = op_x86_phys_to_virt(i);
+                if (!reset_value[virt])
+                        continue;
+
+                /* setup counter registers */
+                wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
+
+                /* setup control registers */
+                rdmsrl(msrs->controls[i].addr, val);
+                val &= model->reserved;
+                val |= op_x86_get_ctrl(model, &counter_config[virt]);
+                wrmsrl(msrs->controls[i].addr, val);
+        }
+
+        if (ibs_caps)
+                setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
+}
+
+static void op_amd_cpu_shutdown(void)
+{
+        if (ibs_caps)
+                setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
+}
+
 static int op_amd_check_ctrs(struct pt_regs * const regs,
                              struct op_msrs const * const msrs)
 {
@@ -425,42 +445,16 @@ static void op_amd_stop(struct op_msrs const * const msrs)
         op_amd_stop_ibs();
 }
 
-static void op_amd_shutdown(struct op_msrs const * const msrs)
-{
-        int i;
-
-        for (i = 0; i < NUM_COUNTERS; ++i) {
-                if (msrs->counters[i].addr)
-                        release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
-        }
-        for (i = 0; i < NUM_CONTROLS; ++i) {
-                if (msrs->controls[i].addr)
-                        release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
-        }
-}
-
-static u8 ibs_eilvt_off;
-
-static inline void apic_init_ibs_nmi_per_cpu(void *arg)
-{
-        ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
-}
-
-static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
-{
-        setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
-}
-
-static int init_ibs_nmi(void)
+static int __init_ibs_nmi(void)
 {
 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 #define IBSCTL                          0x1cc
         struct pci_dev *cpu_cfg;
         int nodes;
         u32 value = 0;
+        u8 ibs_eilvt_off;
 
-        /* per CPU setup */
-        on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
+        ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 
         nodes = 0;
         cpu_cfg = NULL;
@@ -490,22 +484,15 @@ static int init_ibs_nmi(void)
         return 0;
 }
 
-/* uninitialize the APIC for the IBS interrupts if needed */
-static void clear_ibs_nmi(void)
-{
-        if (ibs_caps)
-                on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
-}
-
 /* initialize the APIC for the IBS interrupts if available */
-static void ibs_init(void)
+static void init_ibs(void)
 {
         ibs_caps = get_ibs_caps();
 
         if (!ibs_caps)
                 return;
 
-        if (init_ibs_nmi()) {
+        if (__init_ibs_nmi()) {
                 ibs_caps = 0;
                 return;
         }
@@ -514,14 +501,6 @@ static void ibs_init(void)
                (unsigned)ibs_caps);
 }
 
-static void ibs_exit(void)
-{
-        if (!ibs_caps)
-                return;
-
-        clear_ibs_nmi();
-}
-
 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 
 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
@@ -570,27 +549,22 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 
 static int op_amd_init(struct oprofile_operations *ops)
 {
-        ibs_init();
+        init_ibs();
         create_arch_files = ops->create_files;
         ops->create_files = setup_ibs_files;
         return 0;
 }
 
-static void op_amd_exit(void)
-{
-        ibs_exit();
-}
-
 struct op_x86_model_spec op_amd_spec = {
         .num_counters           = NUM_COUNTERS,
-        .num_controls           = NUM_CONTROLS,
+        .num_controls           = NUM_COUNTERS,
         .num_virt_counters      = NUM_VIRT_COUNTERS,
         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
         .event_mask             = OP_EVENT_MASK,
         .init                   = op_amd_init,
-        .exit                   = op_amd_exit,
         .fill_in_addresses      = &op_amd_fill_in_addresses,
         .setup_ctrs             = &op_amd_setup_ctrs,
+        .cpu_down               = &op_amd_cpu_shutdown,
         .check_ctrs             = &op_amd_check_ctrs,
         .start                  = &op_amd_start,
         .stop                   = &op_amd_stop,
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index e6a160a4684a..182558dd5515 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -385,8 +385,26 @@ static unsigned int get_stagger(void)
 
 static unsigned long reset_value[NUM_COUNTERS_NON_HT];
 
+static void p4_shutdown(struct op_msrs const * const msrs)
+{
+        int i;
 
-static void p4_fill_in_addresses(struct op_msrs * const msrs)
+        for (i = 0; i < num_counters; ++i) {
+                if (msrs->counters[i].addr)
+                        release_perfctr_nmi(msrs->counters[i].addr);
+        }
+        /*
+         * some of the control registers are specially reserved in
+         * conjunction with the counter registers (hence the starting offset).
+         * This saves a few bits.
+         */
+        for (i = num_counters; i < num_controls; ++i) {
+                if (msrs->controls[i].addr)
+                        release_evntsel_nmi(msrs->controls[i].addr);
+        }
+}
+
+static int p4_fill_in_addresses(struct op_msrs * const msrs)
 {
         unsigned int i;
         unsigned int addr, cccraddr, stag;
@@ -468,6 +486,18 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
                         msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;
                 }
         }
+
+        for (i = 0; i < num_counters; ++i) {
+                if (!counter_config[i].enabled)
+                        continue;
+                if (msrs->controls[i].addr)
+                        continue;
+                op_x86_warn_reserved(i);
+                p4_shutdown(msrs);
+                return -EBUSY;
+        }
+
+        return 0;
 }
 
 
@@ -668,26 +698,6 @@ static void p4_stop(struct op_msrs const * const msrs)
         }
 }
 
-static void p4_shutdown(struct op_msrs const * const msrs)
-{
-        int i;
-
-        for (i = 0; i < num_counters; ++i) {
-                if (msrs->counters[i].addr)
-                        release_perfctr_nmi(msrs->counters[i].addr);
-        }
-        /*
-         * some of the control registers are specially reserved in
-         * conjunction with the counter registers (hence the starting offset).
-         * This saves a few bits.
-         */
-        for (i = num_counters; i < num_controls; ++i) {
-                if (msrs->controls[i].addr)
-                        release_evntsel_nmi(msrs->controls[i].addr);
-        }
-}
-
-
 #ifdef CONFIG_SMP
 struct op_x86_model_spec op_p4_ht2_spec = {
         .num_counters           = NUM_COUNTERS_HT2,
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 2bf90fafa7b5..1fd17cfb956b 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -30,19 +30,46 @@ static int counter_width = 32;
 
 static u64 *reset_value;
 
-static void ppro_fill_in_addresses(struct op_msrs * const msrs)
+static void ppro_shutdown(struct op_msrs const * const msrs)
 {
         int i;
 
-        for (i = 0; i < num_counters; i++) {
-                if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
-                        msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
+        for (i = 0; i < num_counters; ++i) {
+                if (!msrs->counters[i].addr)
+                        continue;
+                release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
+                release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
+        }
+        if (reset_value) {
+                kfree(reset_value);
+                reset_value = NULL;
         }
+}
+
+static int ppro_fill_in_addresses(struct op_msrs * const msrs)
+{
+        int i;
 
         for (i = 0; i < num_counters; i++) {
-                if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
-                        msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
+                if (!reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
+                        goto fail;
+                if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) {
+                        release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
+                        goto fail;
+                }
+                /* both registers must be reserved */
+                msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
+                msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
+                continue;
+        fail:
+                if (!counter_config[i].enabled)
+                        continue;
+                op_x86_warn_reserved(i);
+                ppro_shutdown(msrs);
+                return -EBUSY;
         }
+
+        return 0;
 }
 
 
@@ -78,26 +105,17 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
 
         /* clear all counters */
         for (i = 0; i < num_counters; ++i) {
-                if (unlikely(!msrs->controls[i].addr)) {
-                        if (counter_config[i].enabled && !smp_processor_id())
-                                /*
-                                 * counter is reserved, this is on all
-                                 * cpus, so report only for cpu #0
-                                 */
-                                op_x86_warn_reserved(i);
+                if (!msrs->controls[i].addr)
                         continue;
-                }
                 rdmsrl(msrs->controls[i].addr, val);
                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
                         op_x86_warn_in_use(i);
                 val &= model->reserved;
                 wrmsrl(msrs->controls[i].addr, val);
-        }
-
-        /* avoid a false detection of ctr overflows in NMI handler */
-        for (i = 0; i < num_counters; ++i) {
-                if (unlikely(!msrs->counters[i].addr))
-                        continue;
+                /*
+                 * avoid a false detection of ctr overflows in NMI *
+                 * handler
+                 */
                 wrmsrl(msrs->counters[i].addr, -1LL);
         }
 
@@ -189,25 +207,6 @@ static void ppro_stop(struct op_msrs const * const msrs)
         }
 }
 
-static void ppro_shutdown(struct op_msrs const * const msrs)
-{
-        int i;
-
-        for (i = 0; i < num_counters; ++i) {
-                if (msrs->counters[i].addr)
-                        release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
-        }
-        for (i = 0; i < num_counters; ++i) {
-                if (msrs->controls[i].addr)
-                        release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
-        }
-        if (reset_value) {
-                kfree(reset_value);
-                reset_value = NULL;
-        }
-}
-
-
 struct op_x86_model_spec op_ppro_spec = {
         .num_counters           = 2,
         .num_controls           = 2,
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index ff82a755edd4..89017fa1fd63 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -40,10 +40,10 @@ struct op_x86_model_spec {
         u64             reserved;
         u16             event_mask;
         int             (*init)(struct oprofile_operations *ops);
-        void            (*exit)(void);
-        void            (*fill_in_addresses)(struct op_msrs * const msrs);
+        int             (*fill_in_addresses)(struct op_msrs * const msrs);
         void            (*setup_ctrs)(struct op_x86_model_spec const *model,
                                       struct op_msrs const * const msrs);
+        void            (*cpu_down)(void);
         int             (*check_ctrs)(struct pt_regs * const regs,
                                       struct op_msrs const * const msrs);
         void            (*start)(struct op_msrs const * const msrs);