Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (121 commits)
  perf symbols: Increase symbol KSYM_NAME_LEN size
  perf hists browser: Refuse 'a' hotkey on non symbolic views
  perf ui browser: Use libslang to read keys
  perf tools: Fix tracing info recording
  perf hists browser: Elide DSO column when it is set to just one DSO, ditto for threads
  perf hists: Don't consider filtered entries when calculating column widths
  perf hists: Don't decay total_period for filtered entries
  perf hists browser: Honour symbol_conf.show_{nr_samples,total_period}
  perf hists browser: Do not exit on tab key with single event
  perf annotate browser: Don't change selection line when returning from callq
  perf tools: handle endianness of feature bitmap
  perf tools: Add prelink suggestion to dso update message
  perf script: Fix unknown feature comment
  perf hists browser: Apply the dso and thread filters when merging new batches
  perf hists: Move the dso and thread filters from hist_browser
  perf ui browser: Honour the xterm colors
  perf top tui: Give color hints just on the percentage, like on --stdio
  perf ui browser: Make the colors configurable and change the defaults
  perf tui: Remove unneeded call to newtCls on startup
  perf hists: Don't format the percentage on hist_entry__snprintf
  ...

Fix up conflicts in arch/x86/kernel/kprobes.c manually.

Ingo's tree did the insane "add volatile to const array", which just
doesn't make sense ("volatile const"?).  But we could remove the const
*and* make the array volatile to make doubly sure that gcc doesn't
optimize it away..

Also fix up kernel/trace/ring_buffer.c non-data-conflicts manually: the
reader_lock has been turned into a raw lock by the core locking merge,
and there was a new user of it introduced in this perf core merge.  Make
sure that new use also uses the raw accessor functions.

5 files changed, 22 insertions, 308 deletions

diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 96646b3aeca8..75f9528e0372 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -61,26 +61,15 @@ u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
 }
 
 
-static int profile_exceptions_notify(struct notifier_block *self,
-                                     unsigned long val, void *data)
+static int profile_exceptions_notify(unsigned int val, struct pt_regs *regs)
 {
-        struct die_args *args = (struct die_args *)data;
-        int ret = NOTIFY_DONE;
-
-        switch (val) {
-        case DIE_NMI:
-                if (ctr_running)
-                        model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs));
-                else if (!nmi_enabled)
-                        break;
-                else
-                        model->stop(&__get_cpu_var(cpu_msrs));
-                ret = NOTIFY_STOP;
-                break;
-        default:
-                break;
-        }
-        return ret;
+        if (ctr_running)
+                model->check_ctrs(regs, &__get_cpu_var(cpu_msrs));
+        else if (!nmi_enabled)
+                return NMI_DONE;
+        else
+                model->stop(&__get_cpu_var(cpu_msrs));
+        return NMI_HANDLED;
 }
 
 static void nmi_cpu_save_registers(struct op_msrs *msrs)
@@ -363,12 +352,6 @@ static void nmi_cpu_setup(void *dummy)
         apic_write(APIC_LVTPC, APIC_DM_NMI);
 }
 
-static struct notifier_block profile_exceptions_nb = {
-        .notifier_call = profile_exceptions_notify,
-        .next = NULL,
-        .priority = NMI_LOCAL_LOW_PRIOR,
-};
-
 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 {
         struct op_msr *counters = msrs->counters;
@@ -402,8 +385,6 @@ static void nmi_cpu_shutdown(void *dummy)
         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
         apic_write(APIC_LVTERR, v);
         nmi_cpu_restore_registers(msrs);
-        if (model->cpu_down)
-                model->cpu_down();
 }
 
 static void nmi_cpu_up(void *dummy)
@@ -508,7 +489,8 @@ static int nmi_setup(void)
         ctr_running = 0;
         /* make variables visible to the nmi handler: */
         smp_mb();
-        err = register_die_notifier(&profile_exceptions_nb);
+        err = register_nmi_handler(NMI_LOCAL, profile_exceptions_notify,
+                                        0, "oprofile");
         if (err)
                 goto fail;
 
@@ -538,7 +520,7 @@ static void nmi_shutdown(void)
         put_online_cpus();
         /* make variables visible to the nmi handler: */
         smp_mb();
-        unregister_die_notifier(&profile_exceptions_nb);
+        unregister_nmi_handler(NMI_LOCAL, "oprofile");
         msrs = &get_cpu_var(cpu_msrs);
         model->shutdown(msrs);
         free_msrs();
diff --git a/arch/x86/oprofile/nmi_timer_int.c b/arch/x86/oprofile/nmi_timer_int.c
index 720bf5a53c51..7f8052cd6620 100644
--- a/arch/x86/oprofile/nmi_timer_int.c
+++ b/arch/x86/oprofile/nmi_timer_int.c
@@ -18,32 +18,16 @@
 #include <asm/apic.h>
 #include <asm/ptrace.h>
 
-static int profile_timer_exceptions_notify(struct notifier_block *self,
-                                           unsigned long val, void *data)
+static int profile_timer_exceptions_notify(unsigned int val, struct pt_regs *regs)
 {
-        struct die_args *args = (struct die_args *)data;
-        int ret = NOTIFY_DONE;
-
-        switch (val) {
-        case DIE_NMI:
-                oprofile_add_sample(args->regs, 0);
-                ret = NOTIFY_STOP;
-                break;
-        default:
-                break;
-        }
-        return ret;
+        oprofile_add_sample(regs, 0);
+        return NMI_HANDLED;
 }
 
-static struct notifier_block profile_timer_exceptions_nb = {
-        .notifier_call = profile_timer_exceptions_notify,
-        .next = NULL,
-        .priority = NMI_LOW_PRIOR,
-};
-
 static int timer_start(void)
 {
-        if (register_die_notifier(&profile_timer_exceptions_nb))
+        if (register_nmi_handler(NMI_LOCAL, profile_timer_exceptions_notify,
+                                        0, "oprofile-timer"))
                 return 1;
         return 0;
 }
@@ -51,7 +35,7 @@ static int timer_start(void)
 
 static void timer_stop(void)
 {
-        unregister_die_notifier(&profile_timer_exceptions_nb);
+        unregister_nmi_handler(NMI_LOCAL, "oprofile-timer");
         synchronize_sched();  /* Allow already-started NMIs to complete. */
 }
 
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 9cbb710dc94b..303f08637826 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -29,8 +29,6 @@
 #include "op_x86_model.h"
 #include "op_counter.h"
 
-#define NUM_COUNTERS            4
-#define NUM_COUNTERS_F15H       6
 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 #define NUM_VIRT_COUNTERS       32
 #else
@@ -70,62 +68,12 @@ static struct ibs_config ibs_config;
 static struct ibs_state ibs_state;
 
 /*
- * IBS cpuid feature detection
- */
-
-#define IBS_CPUID_FEATURES              0x8000001b
-
-/*
- * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
- * bit 0 is used to indicate the existence of IBS.
- */
-#define IBS_CAPS_AVAIL                  (1U<<0)
-#define IBS_CAPS_FETCHSAM               (1U<<1)
-#define IBS_CAPS_OPSAM                  (1U<<2)
-#define IBS_CAPS_RDWROPCNT              (1U<<3)
-#define IBS_CAPS_OPCNT                  (1U<<4)
-#define IBS_CAPS_BRNTRGT                (1U<<5)
-#define IBS_CAPS_OPCNTEXT               (1U<<6)
-
-#define IBS_CAPS_DEFAULT                (IBS_CAPS_AVAIL         \
-                                         | IBS_CAPS_FETCHSAM    \
-                                         | IBS_CAPS_OPSAM)
-
-/*
- * IBS APIC setup
- */
-#define IBSCTL                          0x1cc
-#define IBSCTL_LVT_OFFSET_VALID         (1ULL<<8)
-#define IBSCTL_LVT_OFFSET_MASK          0x0F
-
-/*
  * IBS randomization macros
  */
 #define IBS_RANDOM_BITS                 12
 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
 
-static u32 get_ibs_caps(void)
-{
-        u32 ibs_caps;
-        unsigned int max_level;
-
-        if (!boot_cpu_has(X86_FEATURE_IBS))
-                return 0;
-
-        /* check IBS cpuid feature flags */
-        max_level = cpuid_eax(0x80000000);
-        if (max_level < IBS_CPUID_FEATURES)
-                return IBS_CAPS_DEFAULT;
-
-        ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
-        if (!(ibs_caps & IBS_CAPS_AVAIL))
-                /* cpuid flags not valid */
-                return IBS_CAPS_DEFAULT;
-
-        return ibs_caps;
-}
-
 /*
  * 16-bit Linear Feedback Shift Register (LFSR)
  *
@@ -316,81 +264,6 @@ static void op_amd_stop_ibs(void)
                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 }
 
-static inline int get_eilvt(int offset)
-{
-        return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
-}
-
-static inline int put_eilvt(int offset)
-{
-        return !setup_APIC_eilvt(offset, 0, 0, 1);
-}
-
-static inline int ibs_eilvt_valid(void)
-{
-        int offset;
-        u64 val;
-        int valid = 0;
-
-        preempt_disable();
-
-        rdmsrl(MSR_AMD64_IBSCTL, val);
-        offset = val & IBSCTL_LVT_OFFSET_MASK;
-
-        if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
-                pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
-                       smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
-                goto out;
-        }
-
-        if (!get_eilvt(offset)) {
-                pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
-                       smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
-                goto out;
-        }
-
-        valid = 1;
-out:
-        preempt_enable();
-
-        return valid;
-}
-
-static inline int get_ibs_offset(void)
-{
-        u64 val;
-
-        rdmsrl(MSR_AMD64_IBSCTL, val);
-        if (!(val & IBSCTL_LVT_OFFSET_VALID))
-                return -EINVAL;
-
-        return val & IBSCTL_LVT_OFFSET_MASK;
-}
-
-static void setup_APIC_ibs(void)
-{
-        int offset;
-
-        offset = get_ibs_offset();
-        if (offset < 0)
-                goto failed;
-
-        if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
-                return;
-failed:
-        pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
-                smp_processor_id());
-}
-
-static void clear_APIC_ibs(void)
-{
-        int offset;
-
-        offset = get_ibs_offset();
-        if (offset >= 0)
-                setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
-}
-
 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 
 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
@@ -439,7 +312,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
                         goto fail;
                 }
                 /* both registers must be reserved */
-                if (num_counters == NUM_COUNTERS_F15H) {
+                if (num_counters == AMD64_NUM_COUNTERS_F15H) {
                         msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);
                         msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);
                 } else {
@@ -504,15 +377,6 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
                 wrmsrl(msrs->controls[i].addr, val);
         }
-
-        if (ibs_caps)
-                setup_APIC_ibs();
-}
-
-static void op_amd_cpu_shutdown(void)
-{
-        if (ibs_caps)
-                clear_APIC_ibs();
 }
 
 static int op_amd_check_ctrs(struct pt_regs * const regs,
@@ -575,86 +439,6 @@ static void op_amd_stop(struct op_msrs const * const msrs)
         op_amd_stop_ibs();
 }
 
-static int setup_ibs_ctl(int ibs_eilvt_off)
-{
-        struct pci_dev *cpu_cfg;
-        int nodes;
-        u32 value = 0;
-
-        nodes = 0;
-        cpu_cfg = NULL;
-        do {
-                cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
-                                         PCI_DEVICE_ID_AMD_10H_NB_MISC,
-                                         cpu_cfg);
-                if (!cpu_cfg)
-                        break;
-                ++nodes;
-                pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
-                                       | IBSCTL_LVT_OFFSET_VALID);
-                pci_read_config_dword(cpu_cfg, IBSCTL, &value);
-                if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
-                        pci_dev_put(cpu_cfg);
-                        printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
-                               "IBSCTL = 0x%08x\n", value);
-                        return -EINVAL;
-                }
-        } while (1);
-
-        if (!nodes) {
-                printk(KERN_DEBUG "No CPU node configured for IBS\n");
-                return -ENODEV;
-        }
-
-        return 0;
-}
-
-/*
- * This runs only on the current cpu. We try to find an LVT offset and
- * setup the local APIC. For this we must disable preemption. On
- * success we initialize all nodes with this offset. This updates then
- * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
- * the IBS interrupt vector is called from op_amd_setup_ctrs()/op_-
- * amd_cpu_shutdown() using the new offset.
- */
-static int force_ibs_eilvt_setup(void)
-{
-        int offset;
-        int ret;
-
-        preempt_disable();
-        /* find the next free available EILVT entry, skip offset 0 */
-        for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
-                if (get_eilvt(offset))
-                        break;
-        }
-        preempt_enable();
-
-        if (offset == APIC_EILVT_NR_MAX) {
-                printk(KERN_DEBUG "No EILVT entry available\n");
-                return -EBUSY;
-        }
-
-        ret = setup_ibs_ctl(offset);
-        if (ret)
-                goto out;
-
-        if (!ibs_eilvt_valid()) {
-                ret = -EFAULT;
-                goto out;
-        }
-
-        pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
-        pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
-
-        return 0;
-out:
-        preempt_disable();
-        put_eilvt(offset);
-        preempt_enable();
-        return ret;
-}
-
 /*
  * check and reserve APIC extended interrupt LVT offset for IBS if
  * available
@@ -667,17 +451,6 @@ static void init_ibs(void)
         if (!ibs_caps)
                 return;
 
-        if (ibs_eilvt_valid())
-                goto out;
-
-        if (!force_ibs_eilvt_setup())
-                goto out;
-
-        /* Failed to setup ibs */
-        ibs_caps = 0;
-        return;
-
-out:
         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", ibs_caps);
 }
 
@@ -741,9 +514,9 @@ static int op_amd_init(struct oprofile_operations *ops)
         ops->create_files = setup_ibs_files;
 
         if (boot_cpu_data.x86 == 0x15) {
-                num_counters = NUM_COUNTERS_F15H;
+                num_counters = AMD64_NUM_COUNTERS_F15H;
         } else {
-                num_counters = NUM_COUNTERS;
+                num_counters = AMD64_NUM_COUNTERS;
         }
 
         op_amd_spec.num_counters = num_counters;
@@ -760,7 +533,6 @@ struct op_x86_model_spec op_amd_spec = {
         .init                   = op_amd_init,
         .fill_in_addresses      = &op_amd_fill_in_addresses,
         .setup_ctrs             = &op_amd_setup_ctrs,
-        .cpu_down               = &op_amd_cpu_shutdown,
         .check_ctrs             = &op_amd_check_ctrs,
         .start                  = &op_amd_start,
         .stop                   = &op_amd_stop,
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 94b745045e45..d90528ea5412 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -28,7 +28,7 @@ static int counter_width = 32;
 
 #define MSR_PPRO_EVENTSEL_RESERVED      ((0xFFFFFFFFULL<<32)|(1ULL<<21))
 
-static u64 *reset_value;
+static u64 reset_value[OP_MAX_COUNTER];
 
 static void ppro_shutdown(struct op_msrs const * const msrs)
 {
@@ -40,10 +40,6 @@ static void ppro_shutdown(struct op_msrs const * const msrs)
                 release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
                 release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
         }
-        if (reset_value) {
-                kfree(reset_value);
-                reset_value = NULL;
-        }
 }
 
 static int ppro_fill_in_addresses(struct op_msrs * const msrs)
@@ -79,13 +75,6 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
         u64 val;
         int i;
 
-        if (!reset_value) {
-                reset_value = kzalloc(sizeof(reset_value[0]) * num_counters,
-                                        GFP_ATOMIC);
-                if (!reset_value)
-                        return;
-        }
-
         if (cpu_has_arch_perfmon) {
                 union cpuid10_eax eax;
                 eax.full = cpuid_eax(0xa);
@@ -141,13 +130,6 @@ static int ppro_check_ctrs(struct pt_regs * const regs,
         u64 val;
         int i;
 
-        /*
-         * This can happen if perf counters are in use when
-         * we steal the die notifier NMI.
-         */
-        if (unlikely(!reset_value))
-                goto out;
-
         for (i = 0; i < num_counters; ++i) {
                 if (!reset_value[i])
                         continue;
@@ -158,7 +140,6 @@ static int ppro_check_ctrs(struct pt_regs * const regs,
                 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
         }
 
-out:
         /* Only P6 based Pentium M need to re-unmask the apic vector but it
          * doesn't hurt other P6 variant */
         apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
@@ -179,8 +160,6 @@ static void ppro_start(struct op_msrs const * const msrs)
         u64 val;
         int i;
 
-        if (!reset_value)
-                return;
         for (i = 0; i < num_counters; ++i) {
                 if (reset_value[i]) {
                         rdmsrl(msrs->controls[i].addr, val);
@@ -196,8 +175,6 @@ static void ppro_stop(struct op_msrs const * const msrs)
         u64 val;
         int i;
 
-        if (!reset_value)
-                return;
         for (i = 0; i < num_counters; ++i) {
                 if (!reset_value[i])
                         continue;
@@ -242,7 +219,7 @@ static void arch_perfmon_setup_counters(void)
                 eax.split.bit_width = 40;
         }
 
-        num_counters = eax.split.num_counters;
+        num_counters = min((int)eax.split.num_counters, OP_MAX_COUNTER);
 
         op_arch_perfmon_spec.num_counters = num_counters;
         op_arch_perfmon_spec.num_controls = num_counters;
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index 89017fa1fd63..71e8a67337e2 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -43,7 +43,6 @@ struct op_x86_model_spec {
         int             (*fill_in_addresses)(struct op_msrs * const msrs);
         void            (*setup_ctrs)(struct op_x86_model_spec const *model,
                                       struct op_msrs const * const msrs);
-        void            (*cpu_down)(void);
         int             (*check_ctrs)(struct pt_regs * const regs,
                                       struct op_msrs const * const msrs);
         void            (*start)(struct op_msrs const * const msrs);