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authorRobert Richter <robert.richter@amd.com>2009-05-25 09:10:32 -0400
committerRobert Richter <robert.richter@amd.com>2009-06-11 13:42:14 -0400
commit3370d358569755625aba4d9a846a040ce691d9ed (patch)
tree97b712208843a33dd29d1bfd9f90bc8aec30a595 /arch/x86/oprofile/op_x86_model.h
parentef8828ddf828174785421af67c281144d4b8e796 (diff)
x86/oprofile: replace macros to calculate control register
This patch introduces op_x86_get_ctrl() to calculate the value of the performance control register. This is generic code usable for all models. The event and reserved masks are model specific and stored in struct op_x86_model_spec. 64 bit MSR functions are used now. The patch removes many hard to read macros used for ctrl calculation. The function op_x86_get_ctrl() is common code and the first step to further merge performance counter implementations for x86 models. Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/oprofile/op_x86_model.h')
-rw-r--r--arch/x86/oprofile/op_x86_model.h15
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index 6161c7f0e7fb..3220d4ce6322 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -6,21 +6,19 @@
6 * @remark Read the file COPYING 6 * @remark Read the file COPYING
7 * 7 *
8 * @author Graydon Hoare 8 * @author Graydon Hoare
9 * @author Robert Richter <robert.richter@amd.com>
9 */ 10 */
10 11
11#ifndef OP_X86_MODEL_H 12#ifndef OP_X86_MODEL_H
12#define OP_X86_MODEL_H 13#define OP_X86_MODEL_H
13 14
15#include <asm/types.h>
14#include <asm/intel_arch_perfmon.h> 16#include <asm/intel_arch_perfmon.h>
15 17
16#define CTR_IS_RESERVED(msrs, c) ((msrs)->counters[(c)].addr ? 1 : 0) 18#define CTR_IS_RESERVED(msrs, c) ((msrs)->counters[(c)].addr ? 1 : 0)
17#define CTRL_IS_RESERVED(msrs, c) ((msrs)->controls[(c)].addr ? 1 : 0) 19#define CTRL_IS_RESERVED(msrs, c) ((msrs)->controls[(c)].addr ? 1 : 0)
18#define CTRL_SET_ACTIVE(val) ((val) |= ARCH_PERFMON_EVENTSEL0_ENABLE) 20#define CTRL_SET_ACTIVE(val) ((val) |= ARCH_PERFMON_EVENTSEL0_ENABLE)
19#define CTRL_SET_ENABLE(val) ((val) |= ARCH_PERFMON_EVENTSEL_INT)
20#define CTRL_SET_INACTIVE(val) ((val) &= ~ARCH_PERFMON_EVENTSEL0_ENABLE) 21#define CTRL_SET_INACTIVE(val) ((val) &= ~ARCH_PERFMON_EVENTSEL0_ENABLE)
21#define CTRL_SET_KERN(val, k) ((val) |= ((k) ? ARCH_PERFMON_EVENTSEL_OS : 0))
22#define CTRL_SET_USR(val, u) ((val) |= ((u) ? ARCH_PERFMON_EVENTSEL_USR : 0))
23#define CTRL_SET_UM(val, m) ((val) |= ((m) << 8))
24 22
25struct op_saved_msr { 23struct op_saved_msr {
26 unsigned int high; 24 unsigned int high;
@@ -39,12 +37,16 @@ struct op_msrs {
39 37
40struct pt_regs; 38struct pt_regs;
41 39
40struct oprofile_operations;
41
42/* The model vtable abstracts the differences between 42/* The model vtable abstracts the differences between
43 * various x86 CPU models' perfctr support. 43 * various x86 CPU models' perfctr support.
44 */ 44 */
45struct op_x86_model_spec { 45struct op_x86_model_spec {
46 unsigned int num_counters; 46 unsigned int num_counters;
47 unsigned int num_controls; 47 unsigned int num_controls;
48 u64 reserved;
49 u16 event_mask;
48 int (*init)(struct oprofile_operations *ops); 50 int (*init)(struct oprofile_operations *ops);
49 void (*exit)(void); 51 void (*exit)(void);
50 void (*fill_in_addresses)(struct op_msrs * const msrs); 52 void (*fill_in_addresses)(struct op_msrs * const msrs);
@@ -57,6 +59,11 @@ struct op_x86_model_spec {
57 void (*shutdown)(struct op_msrs const * const msrs); 59 void (*shutdown)(struct op_msrs const * const msrs);
58}; 60};
59 61
62struct op_counter_config;
63
64extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
65 struct op_counter_config *counter_config);
66
60extern struct op_x86_model_spec const op_ppro_spec; 67extern struct op_x86_model_spec const op_ppro_spec;
61extern struct op_x86_model_spec const op_p4_spec; 68extern struct op_x86_model_spec const op_p4_spec;
62extern struct op_x86_model_spec const op_p4_ht2_spec; 69extern struct op_x86_model_spec const op_p4_ht2_spec;