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authorRobert Richter <robert.richter@amd.com>2008-07-22 15:09:03 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-26 05:48:10 -0400
commit87f0baccc2e4f194c931186d3c8499314494a484 (patch)
tree00aec316dffb7ac58d3b5ef2ffaebdb22e37ff02 /arch/x86/oprofile/op_model_athlon.c
parenta4c408a41167949f820e2740e56a8f2f7bb6177c (diff)
x86/oprofile: macro definition cleanup in op_model_athlon.c
Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: oprofile-list <oprofile-list@lists.sourceforge.net> Cc: Barry Kasindorf <barry.kasindorf@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/oprofile/op_model_athlon.c')
-rw-r--r--arch/x86/oprofile/op_model_athlon.c46
1 files changed, 17 insertions, 29 deletions
diff --git a/arch/x86/oprofile/op_model_athlon.c b/arch/x86/oprofile/op_model_athlon.c
index 1acb067bd343..a3a2058c372c 100644
--- a/arch/x86/oprofile/op_model_athlon.c
+++ b/arch/x86/oprofile/op_model_athlon.c
@@ -47,32 +47,20 @@
47#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9)) 47#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
48#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8)) 48#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
49 49
50#define IBS_FETCH_CTL_HIGH_MASK 0xFFFFFFFF 50/* IbsFetchCtl bits/masks */
51/* high dword bit IbsFetchCtl[bit 49] */ 51#define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
52#define IBS_FETCH_VALID_BIT (1UL << 17) 52#define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
53/* high dword bit IbsFetchCtl[bit 52] */ 53#define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */
54#define IBS_FETCH_PHY_ADDR_VALID_BIT (1UL << 20)
55/* high dword bit IbsFetchCtl[bit 48] */
56#define IBS_FETCH_ENABLE (1UL << 16)
57 54
58#define IBS_FETCH_CTL_CNT_MASK 0x00000000FFFF0000UL 55/*IbsOpCtl bits */
59#define IBS_FETCH_CTL_MAX_CNT_MASK 0x000000000000FFFFUL 56#define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */
60 57#define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */
61/*IbsOpCtl masks/bits */
62#define IBS_OP_VALID_BIT (1ULL<<18) /* IbsOpCtl[bit18] */
63#define IBS_OP_ENABLE (1ULL<<17) /* IBS_OP_ENABLE[bit17]*/
64 58
65/* Codes used in cpu_buffer.c */ 59/* Codes used in cpu_buffer.c */
60/* This produces duplicate code, need to be fixed */
66#define IBS_FETCH_BEGIN 3 61#define IBS_FETCH_BEGIN 3
67#define IBS_OP_BEGIN 4 62#define IBS_OP_BEGIN 4
68 63
69/*IbsOpData3 masks */
70#define IBS_CTL_LVT_OFFSET_VALID_BIT (1ULL<<8)
71
72/*PCI Extended Configuration Constants */
73/* MSR to set the IBS control register APIC LVT offset */
74#define IBS_LVT_OFFSET_PCI 0x1CC
75
76/* The function interface needs to be fixed, something like add 64/* The function interface needs to be fixed, something like add
77 data. Should then be added to linux/oprofile.h. */ 65 data. Should then be added to linux/oprofile.h. */
78extern void oprofile_add_ibs_sample(struct pt_regs *const regs, 66extern void oprofile_add_ibs_sample(struct pt_regs *const regs,
@@ -213,7 +201,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
213 201
214 if (ibs_config.fetch_enabled) { 202 if (ibs_config.fetch_enabled) {
215 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); 203 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
216 if (high & IBS_FETCH_VALID_BIT) { 204 if (high & IBS_FETCH_HIGH_VALID_BIT) {
217 ibs_fetch.ibs_fetch_ctl_high = high; 205 ibs_fetch.ibs_fetch_ctl_high = high;
218 ibs_fetch.ibs_fetch_ctl_low = low; 206 ibs_fetch.ibs_fetch_ctl_low = low;
219 rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high); 207 rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
@@ -229,16 +217,16 @@ op_amd_handle_ibs(struct pt_regs * const regs,
229 217
230 /*reenable the IRQ */ 218 /*reenable the IRQ */
231 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); 219 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
232 high &= ~(IBS_FETCH_VALID_BIT); 220 high &= ~IBS_FETCH_HIGH_VALID_BIT;
233 high |= IBS_FETCH_ENABLE; 221 high |= IBS_FETCH_HIGH_ENABLE;
234 low &= IBS_FETCH_CTL_MAX_CNT_MASK; 222 low &= IBS_FETCH_LOW_MAX_CNT_MASK;
235 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); 223 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
236 } 224 }
237 } 225 }
238 226
239 if (ibs_config.op_enabled) { 227 if (ibs_config.op_enabled) {
240 rdmsr(MSR_AMD64_IBSOPCTL, low, high); 228 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
241 if (low & IBS_OP_VALID_BIT) { 229 if (low & IBS_OP_LOW_VALID_BIT) {
242 rdmsr(MSR_AMD64_IBSOPRIP, low, high); 230 rdmsr(MSR_AMD64_IBSOPRIP, low, high);
243 ibs_op.ibs_op_rip_low = low; 231 ibs_op.ibs_op_rip_low = low;
244 ibs_op.ibs_op_rip_high = high; 232 ibs_op.ibs_op_rip_high = high;
@@ -263,8 +251,8 @@ op_amd_handle_ibs(struct pt_regs * const regs,
263 (unsigned int *)&ibs_op, 251 (unsigned int *)&ibs_op,
264 IBS_OP_BEGIN); 252 IBS_OP_BEGIN);
265 rdmsr(MSR_AMD64_IBSOPCTL, low, high); 253 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
266 low &= ~(IBS_OP_VALID_BIT); 254 low &= ~IBS_OP_LOW_VALID_BIT;
267 low |= IBS_OP_ENABLE; 255 low |= IBS_OP_LOW_ENABLE;
268 wrmsr(MSR_AMD64_IBSOPCTL, low, high); 256 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
269 } 257 }
270 } 258 }
@@ -307,12 +295,12 @@ static void op_amd_start(struct op_msrs const * const msrs)
307 } 295 }
308 if (ibs_allowed && ibs_config.fetch_enabled) { 296 if (ibs_allowed && ibs_config.fetch_enabled) {
309 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; 297 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
310 high = IBS_FETCH_ENABLE; 298 high = IBS_FETCH_HIGH_ENABLE;
311 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); 299 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
312 } 300 }
313 301
314 if (ibs_allowed && ibs_config.op_enabled) { 302 if (ibs_allowed && ibs_config.op_enabled) {
315 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) + IBS_OP_ENABLE; 303 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) + IBS_OP_LOW_ENABLE;
316 high = 0; 304 high = 0;
317 wrmsr(MSR_AMD64_IBSOPCTL, low, high); 305 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
318 } 306 }