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authorRobert Richter <robert.richter@amd.com>2009-07-07 13:30:25 -0400
committerRobert Richter <robert.richter@amd.com>2009-07-14 09:30:03 -0400
commit8045a4c293d36c61656a20d581b11f7f0cd7acd5 (patch)
tree33d201b0916c44a3cf952f96d9fee10b7b6f857b /arch/x86/oprofile/op_model_amd.c
parentdebc6a6927dcd833a30750b07a4c2b456b71f1be (diff)
x86/oprofile: Fix cast of counter value
When casting the counter value to a 64 bit value in 32 bit mode, sign extension may lead to broken counter values. This patch fixes this by casting to (u64) instead of (s64). Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/oprofile/op_model_amd.c')
-rw-r--r--arch/x86/oprofile/op_model_amd.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index e95268eb9220..7ca8306aefae 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -111,7 +111,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
111 if (counter_config[i].enabled && msrs->counters[i].addr) { 111 if (counter_config[i].enabled && msrs->counters[i].addr) {
112 reset_value[i] = counter_config[i].count; 112 reset_value[i] = counter_config[i].count;
113 wrmsrl(msrs->counters[i].addr, 113 wrmsrl(msrs->counters[i].addr,
114 -(s64)counter_config[i].count); 114 -(u64)counter_config[i].count);
115 rdmsrl(msrs->controls[i].addr, val); 115 rdmsrl(msrs->controls[i].addr, val);
116 val &= model->reserved; 116 val &= model->reserved;
117 val |= op_x86_get_ctrl(model, &counter_config[i]); 117 val |= op_x86_get_ctrl(model, &counter_config[i]);
@@ -237,7 +237,7 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
237 if (val & OP_CTR_OVERFLOW) 237 if (val & OP_CTR_OVERFLOW)
238 continue; 238 continue;
239 oprofile_add_sample(regs, i); 239 oprofile_add_sample(regs, i);
240 wrmsrl(msrs->counters[i].addr, -(s64)reset_value[i]); 240 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[i]);
241 } 241 }
242 242
243 op_amd_handle_ibs(regs, msrs); 243 op_amd_handle_ibs(regs, msrs);