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authorIngo Molnar <mingo@elte.hu>2009-03-13 00:54:43 -0400
committerIngo Molnar <mingo@elte.hu>2009-03-13 00:54:43 -0400
commit17d85bc7564571a1cce23ffdb2d2a33301876925 (patch)
tree815bfc3a02e94303c7c834770bf2a17012c10bf8 /arch/x86/mm
parentd95c3578120e5bc4784069439f00ccb1b5f87717 (diff)
parent041b62374c7fedc11a8a1eeda2868612d3d1436c (diff)
Merge commit 'v2.6.29-rc8' into cpus4096
Diffstat (limited to 'arch/x86/mm')
-rw-r--r--arch/x86/mm/pageattr.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 8253bc97587e..9c4294986af7 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -522,6 +522,17 @@ static int split_large_page(pte_t *kpte, unsigned long address)
522 * primary protection behavior: 522 * primary protection behavior:
523 */ 523 */
524 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); 524 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
525
526 /*
527 * Intel Atom errata AAH41 workaround.
528 *
529 * The real fix should be in hw or in a microcode update, but
530 * we also probabilistically try to reduce the window of having
531 * a large TLB mixed with 4K TLBs while instruction fetches are
532 * going on.
533 */
534 __flush_tlb_all();
535
525 base = NULL; 536 base = NULL;
526 537
527out_unlock: 538out_unlock: