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authorIngo Molnar <mingo@elte.hu>2008-03-19 15:30:40 -0400
committerIngo Molnar <mingo@elte.hu>2008-04-24 17:57:30 -0400
commit1ec1fe73dfb711f9ea5a0ef8a7e3af5b6ac8b653 (patch)
tree8bd9c69ef81e161feae599580bbab84b58f11761 /arch/x86/mm
parent4f76cd382213b29dd3658e3e1ea47c0c2be06f3c (diff)
x86: xen unify x86 add common mm pgtable c fix
Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/mm')
-rw-r--r--arch/x86/mm/pgtable.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index d526b46ae188..ed16b7704a3c 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -200,6 +200,24 @@ static int pgd_prepopulate_pmd(struct mm_struct *mm, pgd_t *pgd)
200 200
201 return 1; 201 return 1;
202} 202}
203
204void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
205{
206 paravirt_alloc_pd(mm, __pa(pmd) >> PAGE_SHIFT);
207
208 /* Note: almost everything apart from _PAGE_PRESENT is
209 reserved at the pmd (PDPT) level. */
210 set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
211
212 /*
213 * According to Intel App note "TLBs, Paging-Structure Caches,
214 * and Their Invalidation", April 2007, document 317080-001,
215 * section 8.1: in PAE mode we explicitly have to flush the
216 * TLB via cr3 if the top-level pgd is changed...
217 */
218 if (mm == current->active_mm)
219 write_cr3(read_cr3());
220}
203#else /* !CONFIG_X86_PAE */ 221#else /* !CONFIG_X86_PAE */
204/* No need to prepopulate any pagetable entries in non-PAE modes. */ 222/* No need to prepopulate any pagetable entries in non-PAE modes. */
205static int pgd_prepopulate_pmd(struct mm_struct *mm, pgd_t *pgd) 223static int pgd_prepopulate_pmd(struct mm_struct *mm, pgd_t *pgd)