diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-06-01 04:01:03 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-06-01 04:01:39 -0400 |
commit | 23db9f430be9325a861c7762c1ffadad9ca528a8 (patch) | |
tree | 1ebb681611c96f17aa4f96e28d6923824a8b210f /arch/x86/mm | |
parent | 27b9613b7be39412775d0ab80f57229aa73bb07d (diff) | |
parent | 3218911f839b6c85acbf872ad264ea69aa4d89ad (diff) |
Merge branch 'linus' into perfcounters/core
Merge reason: merge almost-rc8 into perfcounters/core, which was -rc6
based - to pick up the latest upstream fixes.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/mm')
-rw-r--r-- | arch/x86/mm/hugetlbpage.c | 6 | ||||
-rw-r--r-- | arch/x86/mm/pageattr.c | 13 |
2 files changed, 9 insertions, 10 deletions
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c index 8f307d914c2e..f46c340727b8 100644 --- a/arch/x86/mm/hugetlbpage.c +++ b/arch/x86/mm/hugetlbpage.c | |||
@@ -26,12 +26,16 @@ static unsigned long page_table_shareable(struct vm_area_struct *svma, | |||
26 | unsigned long sbase = saddr & PUD_MASK; | 26 | unsigned long sbase = saddr & PUD_MASK; |
27 | unsigned long s_end = sbase + PUD_SIZE; | 27 | unsigned long s_end = sbase + PUD_SIZE; |
28 | 28 | ||
29 | /* Allow segments to share if only one is marked locked */ | ||
30 | unsigned long vm_flags = vma->vm_flags & ~VM_LOCKED; | ||
31 | unsigned long svm_flags = svma->vm_flags & ~VM_LOCKED; | ||
32 | |||
29 | /* | 33 | /* |
30 | * match the virtual addresses, permission and the alignment of the | 34 | * match the virtual addresses, permission and the alignment of the |
31 | * page table page. | 35 | * page table page. |
32 | */ | 36 | */ |
33 | if (pmd_index(addr) != pmd_index(saddr) || | 37 | if (pmd_index(addr) != pmd_index(saddr) || |
34 | vma->vm_flags != svma->vm_flags || | 38 | vm_flags != svm_flags || |
35 | sbase < svma->vm_start || svma->vm_end < s_end) | 39 | sbase < svma->vm_start || svma->vm_end < s_end) |
36 | return 0; | 40 | return 0; |
37 | 41 | ||
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 797f9f107cb6..e17efed088c5 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c | |||
@@ -153,7 +153,7 @@ static void __cpa_flush_all(void *arg) | |||
153 | */ | 153 | */ |
154 | __flush_tlb_all(); | 154 | __flush_tlb_all(); |
155 | 155 | ||
156 | if (cache && boot_cpu_data.x86_model >= 4) | 156 | if (cache && boot_cpu_data.x86 >= 4) |
157 | wbinvd(); | 157 | wbinvd(); |
158 | } | 158 | } |
159 | 159 | ||
@@ -208,20 +208,15 @@ static void cpa_flush_array(unsigned long *start, int numpages, int cache, | |||
208 | int in_flags, struct page **pages) | 208 | int in_flags, struct page **pages) |
209 | { | 209 | { |
210 | unsigned int i, level; | 210 | unsigned int i, level; |
211 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ | ||
211 | 212 | ||
212 | BUG_ON(irqs_disabled()); | 213 | BUG_ON(irqs_disabled()); |
213 | 214 | ||
214 | on_each_cpu(__cpa_flush_range, NULL, 1); | 215 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
215 | 216 | ||
216 | if (!cache) | 217 | if (!cache || do_wbinvd) |
217 | return; | 218 | return; |
218 | 219 | ||
219 | /* 4M threshold */ | ||
220 | if (numpages >= 1024) { | ||
221 | if (boot_cpu_data.x86_model >= 4) | ||
222 | wbinvd(); | ||
223 | return; | ||
224 | } | ||
225 | /* | 220 | /* |
226 | * We only need to flush on one CPU, | 221 | * We only need to flush on one CPU, |
227 | * clflush is a MESI-coherent instruction that | 222 | * clflush is a MESI-coherent instruction that |