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authorThomas Gleixner <tglx@linutronix.de>2007-10-11 05:16:53 -0400
committerThomas Gleixner <tglx@linutronix.de>2007-10-11 05:16:53 -0400
commit9402e12b8fef1efe9cf949fc020dcda22d9d8667 (patch)
tree4dbb4edda5e14edebc981200380d00f6ab0c3f70 /arch/x86/mach-voyager
parent9702785a747aa27baf46ff504beab6528f21f2dd (diff)
i386: move mach-voyager
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/mach-voyager')
-rw-r--r--arch/x86/mach-voyager/Makefile8
-rw-r--r--arch/x86/mach-voyager/setup.c125
-rw-r--r--arch/x86/mach-voyager/voyager_basic.c331
-rw-r--r--arch/x86/mach-voyager/voyager_cat.c1180
-rw-r--r--arch/x86/mach-voyager/voyager_smp.c1952
-rw-r--r--arch/x86/mach-voyager/voyager_thread.c134
6 files changed, 3730 insertions, 0 deletions
diff --git a/arch/x86/mach-voyager/Makefile b/arch/x86/mach-voyager/Makefile
new file mode 100644
index 000000000000..33b74cf0dd22
--- /dev/null
+++ b/arch/x86/mach-voyager/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5EXTRA_CFLAGS := -Iarch/i386/kernel
6obj-y := setup.o voyager_basic.o voyager_thread.o
7
8obj-$(CONFIG_SMP) += voyager_smp.o voyager_cat.o
diff --git a/arch/x86/mach-voyager/setup.c b/arch/x86/mach-voyager/setup.c
new file mode 100644
index 000000000000..2b55694e6400
--- /dev/null
+++ b/arch/x86/mach-voyager/setup.c
@@ -0,0 +1,125 @@
1/*
2 * Machine specific setup for generic
3 */
4
5#include <linux/init.h>
6#include <linux/interrupt.h>
7#include <asm/arch_hooks.h>
8#include <asm/voyager.h>
9#include <asm/e820.h>
10#include <asm/io.h>
11#include <asm/setup.h>
12
13void __init pre_intr_init_hook(void)
14{
15 init_ISA_irqs();
16}
17
18/*
19 * IRQ2 is cascade interrupt to second interrupt controller
20 */
21static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
22
23void __init intr_init_hook(void)
24{
25#ifdef CONFIG_SMP
26 smp_intr_init();
27#endif
28
29 setup_irq(2, &irq2);
30}
31
32void __init pre_setup_arch_hook(void)
33{
34 /* Voyagers run their CPUs from independent clocks, so disable
35 * the TSC code because we can't sync them */
36 tsc_disable = 1;
37}
38
39void __init trap_init_hook(void)
40{
41}
42
43static struct irqaction irq0 = {
44 .handler = timer_interrupt,
45 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL,
46 .mask = CPU_MASK_NONE,
47 .name = "timer"
48};
49
50void __init time_init_hook(void)
51{
52 irq0.mask = cpumask_of_cpu(safe_smp_processor_id());
53 setup_irq(0, &irq0);
54}
55
56/* Hook for machine specific memory setup. */
57
58char * __init machine_specific_memory_setup(void)
59{
60 char *who;
61
62 who = "NOT VOYAGER";
63
64 if(voyager_level == 5) {
65 __u32 addr, length;
66 int i;
67
68 who = "Voyager-SUS";
69
70 e820.nr_map = 0;
71 for(i=0; voyager_memory_detect(i, &addr, &length); i++) {
72 add_memory_region(addr, length, E820_RAM);
73 }
74 return who;
75 } else if(voyager_level == 4) {
76 __u32 tom;
77 __u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT)<<8;
78 /* select the DINO config space */
79 outb(VOYAGER_DINO, VOYAGER_CAT_CONFIG_PORT);
80 /* Read DINO top of memory register */
81 tom = ((inb(catbase + 0x4) & 0xf0) << 16)
82 + ((inb(catbase + 0x5) & 0x7f) << 24);
83
84 if(inb(catbase) != VOYAGER_DINO) {
85 printk(KERN_ERR "Voyager: Failed to get DINO for L4, setting tom to EXT_MEM_K\n");
86 tom = (EXT_MEM_K)<<10;
87 }
88 who = "Voyager-TOM";
89 add_memory_region(0, 0x9f000, E820_RAM);
90 /* map from 1M to top of memory */
91 add_memory_region(1*1024*1024, tom - 1*1024*1024, E820_RAM);
92 /* FIXME: Should check the ASICs to see if I need to
93 * take out the 8M window. Just do it at the moment
94 * */
95 add_memory_region(8*1024*1024, 8*1024*1024, E820_RESERVED);
96 return who;
97 }
98
99 who = "BIOS-e820";
100
101 /*
102 * Try to copy the BIOS-supplied E820-map.
103 *
104 * Otherwise fake a memory map; one section from 0k->640k,
105 * the next section from 1mb->appropriate_mem_k
106 */
107 sanitize_e820_map(E820_MAP, &E820_MAP_NR);
108 if (copy_e820_map(E820_MAP, E820_MAP_NR) < 0) {
109 unsigned long mem_size;
110
111 /* compare results from other methods and take the greater */
112 if (ALT_MEM_K < EXT_MEM_K) {
113 mem_size = EXT_MEM_K;
114 who = "BIOS-88";
115 } else {
116 mem_size = ALT_MEM_K;
117 who = "BIOS-e801";
118 }
119
120 e820.nr_map = 0;
121 add_memory_region(0, LOWMEMSIZE(), E820_RAM);
122 add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM);
123 }
124 return who;
125}
diff --git a/arch/x86/mach-voyager/voyager_basic.c b/arch/x86/mach-voyager/voyager_basic.c
new file mode 100644
index 000000000000..9b77b39b71a6
--- /dev/null
+++ b/arch/x86/mach-voyager/voyager_basic.c
@@ -0,0 +1,331 @@
1/* Copyright (C) 1999,2001
2 *
3 * Author: J.E.J.Bottomley@HansenPartnership.com
4 *
5 * linux/arch/i386/kernel/voyager.c
6 *
7 * This file contains all the voyager specific routines for getting
8 * initialisation of the architecture to function. For additional
9 * features see:
10 *
11 * voyager_cat.c - Voyager CAT bus interface
12 * voyager_smp.c - Voyager SMP hal (emulates linux smp.c)
13 */
14
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/sched.h>
18#include <linux/ptrace.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/reboot.h>
24#include <linux/sysrq.h>
25#include <linux/smp.h>
26#include <linux/nodemask.h>
27#include <asm/io.h>
28#include <asm/voyager.h>
29#include <asm/vic.h>
30#include <linux/pm.h>
31#include <asm/tlbflush.h>
32#include <asm/arch_hooks.h>
33#include <asm/i8253.h>
34
35/*
36 * Power off function, if any
37 */
38void (*pm_power_off)(void);
39EXPORT_SYMBOL(pm_power_off);
40
41int voyager_level = 0;
42
43struct voyager_SUS *voyager_SUS = NULL;
44
45#ifdef CONFIG_SMP
46static void
47voyager_dump(int dummy1, struct tty_struct *dummy3)
48{
49 /* get here via a sysrq */
50 voyager_smp_dump();
51}
52
53static struct sysrq_key_op sysrq_voyager_dump_op = {
54 .handler = voyager_dump,
55 .help_msg = "Voyager",
56 .action_msg = "Dump Voyager Status",
57};
58#endif
59
60void
61voyager_detect(struct voyager_bios_info *bios)
62{
63 if(bios->len != 0xff) {
64 int class = (bios->class_1 << 8)
65 | (bios->class_2 & 0xff);
66
67 printk("Voyager System detected.\n"
68 " Class %x, Revision %d.%d\n",
69 class, bios->major, bios->minor);
70 if(class == VOYAGER_LEVEL4)
71 voyager_level = 4;
72 else if(class < VOYAGER_LEVEL5_AND_ABOVE)
73 voyager_level = 3;
74 else
75 voyager_level = 5;
76 printk(" Architecture Level %d\n", voyager_level);
77 if(voyager_level < 4)
78 printk("\n**WARNING**: Voyager HAL only supports Levels 4 and 5 Architectures at the moment\n\n");
79 /* install the power off handler */
80 pm_power_off = voyager_power_off;
81#ifdef CONFIG_SMP
82 register_sysrq_key('v', &sysrq_voyager_dump_op);
83#endif
84 } else {
85 printk("\n\n**WARNING**: No Voyager Subsystem Found\n");
86 }
87}
88
89void
90voyager_system_interrupt(int cpl, void *dev_id)
91{
92 printk("Voyager: detected system interrupt\n");
93}
94
95/* Routine to read information from the extended CMOS area */
96__u8
97voyager_extended_cmos_read(__u16 addr)
98{
99 outb(addr & 0xff, 0x74);
100 outb((addr >> 8) & 0xff, 0x75);
101 return inb(0x76);
102}
103
104/* internal definitions for the SUS Click Map of memory */
105
106#define CLICK_ENTRIES 16
107#define CLICK_SIZE 4096 /* click to byte conversion for Length */
108
109typedef struct ClickMap {
110 struct Entry {
111 __u32 Address;
112 __u32 Length;
113 } Entry[CLICK_ENTRIES];
114} ClickMap_t;
115
116
117/* This routine is pretty much an awful hack to read the bios clickmap by
118 * mapping it into page 0. There are usually three regions in the map:
119 * Base Memory
120 * Extended Memory
121 * zero length marker for end of map
122 *
123 * Returns are 0 for failure and 1 for success on extracting region.
124 */
125int __init
126voyager_memory_detect(int region, __u32 *start, __u32 *length)
127{
128 int i;
129 int retval = 0;
130 __u8 cmos[4];
131 ClickMap_t *map;
132 unsigned long map_addr;
133 unsigned long old;
134
135 if(region >= CLICK_ENTRIES) {
136 printk("Voyager: Illegal ClickMap region %d\n", region);
137 return 0;
138 }
139
140 for(i = 0; i < sizeof(cmos); i++)
141 cmos[i] = voyager_extended_cmos_read(VOYAGER_MEMORY_CLICKMAP + i);
142
143 map_addr = *(unsigned long *)cmos;
144
145 /* steal page 0 for this */
146 old = pg0[0];
147 pg0[0] = ((map_addr & PAGE_MASK) | _PAGE_RW | _PAGE_PRESENT);
148 local_flush_tlb();
149 /* now clear everything out but page 0 */
150 map = (ClickMap_t *)(map_addr & (~PAGE_MASK));
151
152 /* zero length is the end of the clickmap */
153 if(map->Entry[region].Length != 0) {
154 *length = map->Entry[region].Length * CLICK_SIZE;
155 *start = map->Entry[region].Address;
156 retval = 1;
157 }
158
159 /* replace the mapping */
160 pg0[0] = old;
161 local_flush_tlb();
162 return retval;
163}
164
165/* voyager specific handling code for timer interrupts. Used to hand
166 * off the timer tick to the SMP code, since the VIC doesn't have an
167 * internal timer (The QIC does, but that's another story). */
168void
169voyager_timer_interrupt(void)
170{
171 if((jiffies & 0x3ff) == 0) {
172
173 /* There seems to be something flaky in either
174 * hardware or software that is resetting the timer 0
175 * count to something much higher than it should be
176 * This seems to occur in the boot sequence, just
177 * before root is mounted. Therefore, every 10
178 * seconds or so, we sanity check the timer zero count
179 * and kick it back to where it should be.
180 *
181 * FIXME: This is the most awful hack yet seen. I
182 * should work out exactly what is interfering with
183 * the timer count settings early in the boot sequence
184 * and swiftly introduce it to something sharp and
185 * pointy. */
186 __u16 val;
187
188 spin_lock(&i8253_lock);
189
190 outb_p(0x00, 0x43);
191 val = inb_p(0x40);
192 val |= inb(0x40) << 8;
193 spin_unlock(&i8253_lock);
194
195 if(val > LATCH) {
196 printk("\nVOYAGER: countdown timer value too high (%d), resetting\n\n", val);
197 spin_lock(&i8253_lock);
198 outb(0x34,0x43);
199 outb_p(LATCH & 0xff , 0x40); /* LSB */
200 outb(LATCH >> 8 , 0x40); /* MSB */
201 spin_unlock(&i8253_lock);
202 }
203 }
204#ifdef CONFIG_SMP
205 smp_vic_timer_interrupt();
206#endif
207}
208
209void
210voyager_power_off(void)
211{
212 printk("VOYAGER Power Off\n");
213
214 if(voyager_level == 5) {
215 voyager_cat_power_off();
216 } else if(voyager_level == 4) {
217 /* This doesn't apparently work on most L4 machines,
218 * but the specs say to do this to get automatic power
219 * off. Unfortunately, if it doesn't power off the
220 * machine, it ends up doing a cold restart, which
221 * isn't really intended, so comment out the code */
222#if 0
223 int port;
224
225
226 /* enable the voyager Configuration Space */
227 outb((inb(VOYAGER_MC_SETUP) & 0xf0) | 0x8,
228 VOYAGER_MC_SETUP);
229 /* the port for the power off flag is an offset from the
230 floating base */
231 port = (inb(VOYAGER_SSPB_RELOCATION_PORT) << 8) + 0x21;
232 /* set the power off flag */
233 outb(inb(port) | 0x1, port);
234#endif
235 }
236 /* and wait for it to happen */
237 local_irq_disable();
238 for(;;)
239 halt();
240}
241
242/* copied from process.c */
243static inline void
244kb_wait(void)
245{
246 int i;
247
248 for (i=0; i<0x10000; i++)
249 if ((inb_p(0x64) & 0x02) == 0)
250 break;
251}
252
253void
254machine_shutdown(void)
255{
256 /* Architecture specific shutdown needed before a kexec */
257}
258
259void
260machine_restart(char *cmd)
261{
262 printk("Voyager Warm Restart\n");
263 kb_wait();
264
265 if(voyager_level == 5) {
266 /* write magic values to the RTC to inform system that
267 * shutdown is beginning */
268 outb(0x8f, 0x70);
269 outb(0x5 , 0x71);
270
271 udelay(50);
272 outb(0xfe,0x64); /* pull reset low */
273 } else if(voyager_level == 4) {
274 __u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT)<<8;
275 __u8 basebd = inb(VOYAGER_MC_SETUP);
276
277 outb(basebd | 0x08, VOYAGER_MC_SETUP);
278 outb(0x02, catbase + 0x21);
279 }
280 local_irq_disable();
281 for(;;)
282 halt();
283}
284
285void
286machine_emergency_restart(void)
287{
288 /*for now, just hook this to a warm restart */
289 machine_restart(NULL);
290}
291
292void
293mca_nmi_hook(void)
294{
295 __u8 dumpval __maybe_unused = inb(0xf823);
296 __u8 swnmi __maybe_unused = inb(0xf813);
297
298 /* FIXME: assume dump switch pressed */
299 /* check to see if the dump switch was pressed */
300 VDEBUG(("VOYAGER: dumpval = 0x%x, swnmi = 0x%x\n", dumpval, swnmi));
301 /* clear swnmi */
302 outb(0xff, 0xf813);
303 /* tell SUS to ignore dump */
304 if(voyager_level == 5 && voyager_SUS != NULL) {
305 if(voyager_SUS->SUS_mbox == VOYAGER_DUMP_BUTTON_NMI) {
306 voyager_SUS->kernel_mbox = VOYAGER_NO_COMMAND;
307 voyager_SUS->kernel_flags |= VOYAGER_OS_IN_PROGRESS;
308 udelay(1000);
309 voyager_SUS->kernel_mbox = VOYAGER_IGNORE_DUMP;
310 voyager_SUS->kernel_flags &= ~VOYAGER_OS_IN_PROGRESS;
311 }
312 }
313 printk(KERN_ERR "VOYAGER: Dump switch pressed, printing CPU%d tracebacks\n", smp_processor_id());
314 show_stack(NULL, NULL);
315 show_state();
316}
317
318
319
320void
321machine_halt(void)
322{
323 /* treat a halt like a power off */
324 machine_power_off();
325}
326
327void machine_power_off(void)
328{
329 if (pm_power_off)
330 pm_power_off();
331}
diff --git a/arch/x86/mach-voyager/voyager_cat.c b/arch/x86/mach-voyager/voyager_cat.c
new file mode 100644
index 000000000000..26a2d4c54b68
--- /dev/null
+++ b/arch/x86/mach-voyager/voyager_cat.c
@@ -0,0 +1,1180 @@
1/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 1999,2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/kernel/voyager_cat.c
8 *
9 * This file contains all the logic for manipulating the CAT bus
10 * in a level 5 machine.
11 *
12 * The CAT bus is a serial configuration and test bus. Its primary
13 * uses are to probe the initial configuration of the system and to
14 * diagnose error conditions when a system interrupt occurs. The low
15 * level interface is fairly primitive, so most of this file consists
16 * of bit shift manipulations to send and receive packets on the
17 * serial bus */
18
19#include <linux/types.h>
20#include <linux/completion.h>
21#include <linux/sched.h>
22#include <asm/voyager.h>
23#include <asm/vic.h>
24#include <linux/ioport.h>
25#include <linux/init.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <asm/io.h>
29
30#ifdef VOYAGER_CAT_DEBUG
31#define CDEBUG(x) printk x
32#else
33#define CDEBUG(x)
34#endif
35
36/* the CAT command port */
37#define CAT_CMD (sspb + 0xe)
38/* the CAT data port */
39#define CAT_DATA (sspb + 0xd)
40
41/* the internal cat functions */
42static void cat_pack(__u8 *msg, __u16 start_bit, __u8 *data,
43 __u16 num_bits);
44static void cat_unpack(__u8 *msg, __u16 start_bit, __u8 *data,
45 __u16 num_bits);
46static void cat_build_header(__u8 *header, const __u16 len,
47 const __u16 smallest_reg_bits,
48 const __u16 longest_reg_bits);
49static int cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp,
50 __u8 reg, __u8 op);
51static int cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp,
52 __u8 reg, __u8 *value);
53static int cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes,
54 __u8 pad_bits);
55static int cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
56 __u8 value);
57static int cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
58 __u8 *value);
59static int cat_subread(voyager_module_t *modp, voyager_asic_t *asicp,
60 __u16 offset, __u16 len, void *buf);
61static int cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp,
62 __u8 reg, __u8 value);
63static int cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp);
64static int cat_connect(voyager_module_t *modp, voyager_asic_t *asicp);
65
66static inline const char *
67cat_module_name(int module_id)
68{
69 switch(module_id) {
70 case 0x10:
71 return "Processor Slot 0";
72 case 0x11:
73 return "Processor Slot 1";
74 case 0x12:
75 return "Processor Slot 2";
76 case 0x13:
77 return "Processor Slot 4";
78 case 0x14:
79 return "Memory Slot 0";
80 case 0x15:
81 return "Memory Slot 1";
82 case 0x18:
83 return "Primary Microchannel";
84 case 0x19:
85 return "Secondary Microchannel";
86 case 0x1a:
87 return "Power Supply Interface";
88 case 0x1c:
89 return "Processor Slot 5";
90 case 0x1d:
91 return "Processor Slot 6";
92 case 0x1e:
93 return "Processor Slot 7";
94 case 0x1f:
95 return "Processor Slot 8";
96 default:
97 return "Unknown Module";
98 }
99}
100
101static int sspb = 0; /* stores the super port location */
102int voyager_8slot = 0; /* set to true if a 51xx monster */
103
104voyager_module_t *voyager_cat_list;
105
106/* the I/O port assignments for the VIC and QIC */
107static struct resource vic_res = {
108 .name = "Voyager Interrupt Controller",
109 .start = 0xFC00,
110 .end = 0xFC6F
111};
112static struct resource qic_res = {
113 .name = "Quad Interrupt Controller",
114 .start = 0xFC70,
115 .end = 0xFCFF
116};
117
118/* This function is used to pack a data bit stream inside a message.
119 * It writes num_bits of the data buffer in msg starting at start_bit.
120 * Note: This function assumes that any unused bit in the data stream
121 * is set to zero so that the ors will work correctly */
122static void
123cat_pack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits)
124{
125 /* compute initial shift needed */
126 const __u16 offset = start_bit % BITS_PER_BYTE;
127 __u16 len = num_bits / BITS_PER_BYTE;
128 __u16 byte = start_bit / BITS_PER_BYTE;
129 __u16 residue = (num_bits % BITS_PER_BYTE) + offset;
130 int i;
131
132 /* adjust if we have more than a byte of residue */
133 if(residue >= BITS_PER_BYTE) {
134 residue -= BITS_PER_BYTE;
135 len++;
136 }
137
138 /* clear out the bits. We assume here that if len==0 then
139 * residue >= offset. This is always true for the catbus
140 * operations */
141 msg[byte] &= 0xff << (BITS_PER_BYTE - offset);
142 msg[byte++] |= data[0] >> offset;
143 if(len == 0)
144 return;
145 for(i = 1; i < len; i++)
146 msg[byte++] = (data[i-1] << (BITS_PER_BYTE - offset))
147 | (data[i] >> offset);
148 if(residue != 0) {
149 __u8 mask = 0xff >> residue;
150 __u8 last_byte = data[i-1] << (BITS_PER_BYTE - offset)
151 | (data[i] >> offset);
152
153 last_byte &= ~mask;
154 msg[byte] &= mask;
155 msg[byte] |= last_byte;
156 }
157 return;
158}
159/* unpack the data again (same arguments as cat_pack()). data buffer
160 * must be zero populated.
161 *
162 * Function: given a message string move to start_bit and copy num_bits into
163 * data (starting at bit 0 in data).
164 */
165static void
166cat_unpack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits)
167{
168 /* compute initial shift needed */
169 const __u16 offset = start_bit % BITS_PER_BYTE;
170 __u16 len = num_bits / BITS_PER_BYTE;
171 const __u8 last_bits = num_bits % BITS_PER_BYTE;
172 __u16 byte = start_bit / BITS_PER_BYTE;
173 int i;
174
175 if(last_bits != 0)
176 len++;
177
178 /* special case: want < 8 bits from msg and we can get it from
179 * a single byte of the msg */
180 if(len == 0 && BITS_PER_BYTE - offset >= num_bits) {
181 data[0] = msg[byte] << offset;
182 data[0] &= 0xff >> (BITS_PER_BYTE - num_bits);
183 return;
184 }
185 for(i = 0; i < len; i++) {
186 /* this annoying if has to be done just in case a read of
187 * msg one beyond the array causes a panic */
188 if(offset != 0) {
189 data[i] = msg[byte++] << offset;
190 data[i] |= msg[byte] >> (BITS_PER_BYTE - offset);
191 }
192 else {
193 data[i] = msg[byte++];
194 }
195 }
196 /* do we need to truncate the final byte */
197 if(last_bits != 0) {
198 data[i-1] &= 0xff << (BITS_PER_BYTE - last_bits);
199 }
200 return;
201}
202
203static void
204cat_build_header(__u8 *header, const __u16 len, const __u16 smallest_reg_bits,
205 const __u16 longest_reg_bits)
206{
207 int i;
208 __u16 start_bit = (smallest_reg_bits - 1) % BITS_PER_BYTE;
209 __u8 *last_byte = &header[len - 1];
210
211 if(start_bit == 0)
212 start_bit = 1; /* must have at least one bit in the hdr */
213
214 for(i=0; i < len; i++)
215 header[i] = 0;
216
217 for(i = start_bit; i > 0; i--)
218 *last_byte = ((*last_byte) << 1) + 1;
219
220}
221
222static int
223cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 op)
224{
225 __u8 parity, inst, inst_buf[4] = { 0 };
226 __u8 iseq[VOYAGER_MAX_SCAN_PATH], hseq[VOYAGER_MAX_REG_SIZE];
227 __u16 ibytes, hbytes, padbits;
228 int i;
229
230 /*
231 * Parity is the parity of the register number + 1 (READ_REGISTER
232 * and WRITE_REGISTER always add '1' to the number of bits == 1)
233 */
234 parity = (__u8)(1 + (reg & 0x01) +
235 ((__u8)(reg & 0x02) >> 1) +
236 ((__u8)(reg & 0x04) >> 2) +
237 ((__u8)(reg & 0x08) >> 3)) % 2;
238
239 inst = ((parity << 7) | (reg << 2) | op);
240
241 outb(VOYAGER_CAT_IRCYC, CAT_CMD);
242 if(!modp->scan_path_connected) {
243 if(asicp->asic_id != VOYAGER_CAT_ID) {
244 printk("**WARNING***: cat_sendinst has disconnected scan path not to CAT asic\n");
245 return 1;
246 }
247 outb(VOYAGER_CAT_HEADER, CAT_DATA);
248 outb(inst, CAT_DATA);
249 if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) {
250 CDEBUG(("VOYAGER CAT: cat_sendinst failed to get CAT_HEADER\n"));
251 return 1;
252 }
253 return 0;
254 }
255 ibytes = modp->inst_bits / BITS_PER_BYTE;
256 if((padbits = modp->inst_bits % BITS_PER_BYTE) != 0) {
257 padbits = BITS_PER_BYTE - padbits;
258 ibytes++;
259 }
260 hbytes = modp->largest_reg / BITS_PER_BYTE;
261 if(modp->largest_reg % BITS_PER_BYTE)
262 hbytes++;
263 CDEBUG(("cat_sendinst: ibytes=%d, hbytes=%d\n", ibytes, hbytes));
264 /* initialise the instruction sequence to 0xff */
265 for(i=0; i < ibytes + hbytes; i++)
266 iseq[i] = 0xff;
267 cat_build_header(hseq, hbytes, modp->smallest_reg, modp->largest_reg);
268 cat_pack(iseq, modp->inst_bits, hseq, hbytes * BITS_PER_BYTE);
269 inst_buf[0] = inst;
270 inst_buf[1] = 0xFF >> (modp->largest_reg % BITS_PER_BYTE);
271 cat_pack(iseq, asicp->bit_location, inst_buf, asicp->ireg_length);
272#ifdef VOYAGER_CAT_DEBUG
273 printk("ins = 0x%x, iseq: ", inst);
274 for(i=0; i< ibytes + hbytes; i++)
275 printk("0x%x ", iseq[i]);
276 printk("\n");
277#endif
278 if(cat_shiftout(iseq, ibytes, hbytes, padbits)) {
279 CDEBUG(("VOYAGER CAT: cat_sendinst: cat_shiftout failed\n"));
280 return 1;
281 }
282 CDEBUG(("CAT SHIFTOUT DONE\n"));
283 return 0;
284}
285
286static int
287cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
288 __u8 *value)
289{
290 if(!modp->scan_path_connected) {
291 if(asicp->asic_id != VOYAGER_CAT_ID) {
292 CDEBUG(("VOYAGER CAT: ERROR: cat_getdata to CAT asic with scan path connected\n"));
293 return 1;
294 }
295 if(reg > VOYAGER_SUBADDRHI)
296 outb(VOYAGER_CAT_RUN, CAT_CMD);
297 outb(VOYAGER_CAT_DRCYC, CAT_CMD);
298 outb(VOYAGER_CAT_HEADER, CAT_DATA);
299 *value = inb(CAT_DATA);
300 outb(0xAA, CAT_DATA);
301 if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) {
302 CDEBUG(("cat_getdata: failed to get VOYAGER_CAT_HEADER\n"));
303 return 1;
304 }
305 return 0;
306 }
307 else {
308 __u16 sbits = modp->num_asics -1 + asicp->ireg_length;
309 __u16 sbytes = sbits / BITS_PER_BYTE;
310 __u16 tbytes;
311 __u8 string[VOYAGER_MAX_SCAN_PATH], trailer[VOYAGER_MAX_REG_SIZE];
312 __u8 padbits;
313 int i;
314
315 outb(VOYAGER_CAT_DRCYC, CAT_CMD);
316
317 if((padbits = sbits % BITS_PER_BYTE) != 0) {
318 padbits = BITS_PER_BYTE - padbits;
319 sbytes++;
320 }
321 tbytes = asicp->ireg_length / BITS_PER_BYTE;
322 if(asicp->ireg_length % BITS_PER_BYTE)
323 tbytes++;
324 CDEBUG(("cat_getdata: tbytes = %d, sbytes = %d, padbits = %d\n",
325 tbytes, sbytes, padbits));
326 cat_build_header(trailer, tbytes, 1, asicp->ireg_length);
327
328
329 for(i = tbytes - 1; i >= 0; i--) {
330 outb(trailer[i], CAT_DATA);
331 string[sbytes + i] = inb(CAT_DATA);
332 }
333
334 for(i = sbytes - 1; i >= 0; i--) {
335 outb(0xaa, CAT_DATA);
336 string[i] = inb(CAT_DATA);
337 }
338 *value = 0;
339 cat_unpack(string, padbits + (tbytes * BITS_PER_BYTE) + asicp->asic_location, value, asicp->ireg_length);
340#ifdef VOYAGER_CAT_DEBUG
341 printk("value=0x%x, string: ", *value);
342 for(i=0; i< tbytes+sbytes; i++)
343 printk("0x%x ", string[i]);
344 printk("\n");
345#endif
346
347 /* sanity check the rest of the return */
348 for(i=0; i < tbytes; i++) {
349 __u8 input = 0;
350
351 cat_unpack(string, padbits + (i * BITS_PER_BYTE), &input, BITS_PER_BYTE);
352 if(trailer[i] != input) {
353 CDEBUG(("cat_getdata: failed to sanity check rest of ret(%d) 0x%x != 0x%x\n", i, input, trailer[i]));
354 return 1;
355 }
356 }
357 CDEBUG(("cat_getdata DONE\n"));
358 return 0;
359 }
360}
361
362static int
363cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, __u8 pad_bits)
364{
365 int i;
366
367 for(i = data_bytes + header_bytes - 1; i >= header_bytes; i--)
368 outb(data[i], CAT_DATA);
369
370 for(i = header_bytes - 1; i >= 0; i--) {
371 __u8 header = 0;
372 __u8 input;
373
374 outb(data[i], CAT_DATA);
375 input = inb(CAT_DATA);
376 CDEBUG(("cat_shiftout: returned 0x%x\n", input));
377 cat_unpack(data, ((data_bytes + i) * BITS_PER_BYTE) - pad_bits,
378 &header, BITS_PER_BYTE);
379 if(input != header) {
380 CDEBUG(("VOYAGER CAT: cat_shiftout failed to return header 0x%x != 0x%x\n", input, header));
381 return 1;
382 }
383 }
384 return 0;
385}
386
387static int
388cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp,
389 __u8 reg, __u8 value)
390{
391 outb(VOYAGER_CAT_DRCYC, CAT_CMD);
392 if(!modp->scan_path_connected) {
393 if(asicp->asic_id != VOYAGER_CAT_ID) {
394 CDEBUG(("VOYAGER CAT: ERROR: scan path disconnected when asic != CAT\n"));
395 return 1;
396 }
397 outb(VOYAGER_CAT_HEADER, CAT_DATA);
398 outb(value, CAT_DATA);
399 if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) {
400 CDEBUG(("cat_senddata: failed to get correct header response to sent data\n"));
401 return 1;
402 }
403 if(reg > VOYAGER_SUBADDRHI) {
404 outb(VOYAGER_CAT_RUN, CAT_CMD);
405 outb(VOYAGER_CAT_END, CAT_CMD);
406 outb(VOYAGER_CAT_RUN, CAT_CMD);
407 }
408
409 return 0;
410 }
411 else {
412 __u16 hbytes = asicp->ireg_length / BITS_PER_BYTE;
413 __u16 dbytes = (modp->num_asics - 1 + asicp->ireg_length)/BITS_PER_BYTE;
414 __u8 padbits, dseq[VOYAGER_MAX_SCAN_PATH],
415 hseq[VOYAGER_MAX_REG_SIZE];
416 int i;
417
418 if((padbits = (modp->num_asics - 1
419 + asicp->ireg_length) % BITS_PER_BYTE) != 0) {
420 padbits = BITS_PER_BYTE - padbits;
421 dbytes++;
422 }
423 if(asicp->ireg_length % BITS_PER_BYTE)
424 hbytes++;
425
426 cat_build_header(hseq, hbytes, 1, asicp->ireg_length);
427
428 for(i = 0; i < dbytes + hbytes; i++)
429 dseq[i] = 0xff;
430 CDEBUG(("cat_senddata: dbytes=%d, hbytes=%d, padbits=%d\n",
431 dbytes, hbytes, padbits));
432 cat_pack(dseq, modp->num_asics - 1 + asicp->ireg_length,
433 hseq, hbytes * BITS_PER_BYTE);
434 cat_pack(dseq, asicp->asic_location, &value,
435 asicp->ireg_length);
436#ifdef VOYAGER_CAT_DEBUG
437 printk("dseq ");
438 for(i=0; i<hbytes+dbytes; i++) {
439 printk("0x%x ", dseq[i]);
440 }
441 printk("\n");
442#endif
443 return cat_shiftout(dseq, dbytes, hbytes, padbits);
444 }
445}
446
447static int
448cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
449 __u8 value)
450{
451 if(cat_sendinst(modp, asicp, reg, VOYAGER_WRITE_CONFIG))
452 return 1;
453 return cat_senddata(modp, asicp, reg, value);
454}
455
456static int
457cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
458 __u8 *value)
459{
460 if(cat_sendinst(modp, asicp, reg, VOYAGER_READ_CONFIG))
461 return 1;
462 return cat_getdata(modp, asicp, reg, value);
463}
464
465static int
466cat_subaddrsetup(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset,
467 __u16 len)
468{
469 __u8 val;
470
471 if(len > 1) {
472 /* set auto increment */
473 __u8 newval;
474
475 if(cat_read(modp, asicp, VOYAGER_AUTO_INC_REG, &val)) {
476 CDEBUG(("cat_subaddrsetup: read of VOYAGER_AUTO_INC_REG failed\n"));
477 return 1;
478 }
479 CDEBUG(("cat_subaddrsetup: VOYAGER_AUTO_INC_REG = 0x%x\n", val));
480 newval = val | VOYAGER_AUTO_INC;
481 if(newval != val) {
482 if(cat_write(modp, asicp, VOYAGER_AUTO_INC_REG, val)) {
483 CDEBUG(("cat_subaddrsetup: write to VOYAGER_AUTO_INC_REG failed\n"));
484 return 1;
485 }
486 }
487 }
488 if(cat_write(modp, asicp, VOYAGER_SUBADDRLO, (__u8)(offset &0xff))) {
489 CDEBUG(("cat_subaddrsetup: write to SUBADDRLO failed\n"));
490 return 1;
491 }
492 if(asicp->subaddr > VOYAGER_SUBADDR_LO) {
493 if(cat_write(modp, asicp, VOYAGER_SUBADDRHI, (__u8)(offset >> 8))) {
494 CDEBUG(("cat_subaddrsetup: write to SUBADDRHI failed\n"));
495 return 1;
496 }
497 cat_read(modp, asicp, VOYAGER_SUBADDRHI, &val);
498 CDEBUG(("cat_subaddrsetup: offset = %d, hi = %d\n", offset, val));
499 }
500 cat_read(modp, asicp, VOYAGER_SUBADDRLO, &val);
501 CDEBUG(("cat_subaddrsetup: offset = %d, lo = %d\n", offset, val));
502 return 0;
503}
504
505static int
506cat_subwrite(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset,
507 __u16 len, void *buf)
508{
509 int i, retval;
510
511 /* FIXME: need special actions for VOYAGER_CAT_ID here */
512 if(asicp->asic_id == VOYAGER_CAT_ID) {
513 CDEBUG(("cat_subwrite: ATTEMPT TO WRITE TO CAT ASIC\n"));
514 /* FIXME -- This is supposed to be handled better
515 * There is a problem writing to the cat asic in the
516 * PSI. The 30us delay seems to work, though */
517 udelay(30);
518 }
519
520 if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) {
521 printk("cat_subwrite: cat_subaddrsetup FAILED\n");
522 return retval;
523 }
524
525 if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_WRITE_CONFIG)) {
526 printk("cat_subwrite: cat_sendinst FAILED\n");
527 return 1;
528 }
529 for(i = 0; i < len; i++) {
530 if(cat_senddata(modp, asicp, 0xFF, ((__u8 *)buf)[i])) {
531 printk("cat_subwrite: cat_sendata element at %d FAILED\n", i);
532 return 1;
533 }
534 }
535 return 0;
536}
537static int
538cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset,
539 __u16 len, void *buf)
540{
541 int i, retval;
542
543 if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) {
544 CDEBUG(("cat_subread: cat_subaddrsetup FAILED\n"));
545 return retval;
546 }
547
548 if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_READ_CONFIG)) {
549 CDEBUG(("cat_subread: cat_sendinst failed\n"));
550 return 1;
551 }
552 for(i = 0; i < len; i++) {
553 if(cat_getdata(modp, asicp, 0xFF,
554 &((__u8 *)buf)[i])) {
555 CDEBUG(("cat_subread: cat_getdata element %d failed\n", i));
556 return 1;
557 }
558 }
559 return 0;
560}
561
562
563/* buffer for storing EPROM data read in during initialisation */
564static __initdata __u8 eprom_buf[0xFFFF];
565static voyager_module_t *voyager_initial_module;
566
567/* Initialise the cat bus components. We assume this is called by the
568 * boot cpu *after* all memory initialisation has been done (so we can
569 * use kmalloc) but before smp initialisation, so we can probe the SMP
570 * configuration and pick up necessary information. */
571void
572voyager_cat_init(void)
573{
574 voyager_module_t **modpp = &voyager_initial_module;
575 voyager_asic_t **asicpp;
576 voyager_asic_t *qabc_asic = NULL;
577 int i, j;
578 unsigned long qic_addr = 0;
579 __u8 qabc_data[0x20];
580 __u8 num_submodules, val;
581 voyager_eprom_hdr_t *eprom_hdr = (voyager_eprom_hdr_t *)&eprom_buf[0];
582
583 __u8 cmos[4];
584 unsigned long addr;
585
586 /* initiallise the SUS mailbox */
587 for(i=0; i<sizeof(cmos); i++)
588 cmos[i] = voyager_extended_cmos_read(VOYAGER_DUMP_LOCATION + i);
589 addr = *(unsigned long *)cmos;
590 if((addr & 0xff000000) != 0xff000000) {
591 printk(KERN_ERR "Voyager failed to get SUS mailbox (addr = 0x%lx\n", addr);
592 } else {
593 static struct resource res;
594
595 res.name = "voyager SUS";
596 res.start = addr;
597 res.end = addr+0x3ff;
598
599 request_resource(&iomem_resource, &res);
600 voyager_SUS = (struct voyager_SUS *)
601 ioremap(addr, 0x400);
602 printk(KERN_NOTICE "Voyager SUS mailbox version 0x%x\n",
603 voyager_SUS->SUS_version);
604 voyager_SUS->kernel_version = VOYAGER_MAILBOX_VERSION;
605 voyager_SUS->kernel_flags = VOYAGER_OS_HAS_SYSINT;
606 }
607
608 /* clear the processor counts */
609 voyager_extended_vic_processors = 0;
610 voyager_quad_processors = 0;
611
612
613
614 printk("VOYAGER: beginning CAT bus probe\n");
615 /* set up the SuperSet Port Block which tells us where the
616 * CAT communication port is */
617 sspb = inb(VOYAGER_SSPB_RELOCATION_PORT) * 0x100;
618 VDEBUG(("VOYAGER DEBUG: sspb = 0x%x\n", sspb));
619
620 /* now find out if were 8 slot or normal */
621 if((inb(VIC_PROC_WHO_AM_I) & EIGHT_SLOT_IDENTIFIER)
622 == EIGHT_SLOT_IDENTIFIER) {
623 voyager_8slot = 1;
624 printk(KERN_NOTICE "Voyager: Eight slot 51xx configuration detected\n");
625 }
626
627 for(i = VOYAGER_MIN_MODULE;
628 i <= VOYAGER_MAX_MODULE; i++) {
629 __u8 input;
630 int asic;
631 __u16 eprom_size;
632 __u16 sp_offset;
633
634 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
635 outb(i, VOYAGER_CAT_CONFIG_PORT);
636
637 /* check the presence of the module */
638 outb(VOYAGER_CAT_RUN, CAT_CMD);
639 outb(VOYAGER_CAT_IRCYC, CAT_CMD);
640 outb(VOYAGER_CAT_HEADER, CAT_DATA);
641 /* stream series of alternating 1's and 0's to stimulate
642 * response */
643 outb(0xAA, CAT_DATA);
644 input = inb(CAT_DATA);
645 outb(VOYAGER_CAT_END, CAT_CMD);
646 if(input != VOYAGER_CAT_HEADER) {
647 continue;
648 }
649 CDEBUG(("VOYAGER DEBUG: found module id 0x%x, %s\n", i,
650 cat_module_name(i)));
651 *modpp = kmalloc(sizeof(voyager_module_t), GFP_KERNEL); /*&voyager_module_storage[cat_count++];*/
652 if(*modpp == NULL) {
653 printk("**WARNING** kmalloc failure in cat_init\n");
654 continue;
655 }
656 memset(*modpp, 0, sizeof(voyager_module_t));
657 /* need temporary asic for cat_subread. It will be
658 * filled in correctly later */
659 (*modpp)->asic = kmalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count];*/
660 if((*modpp)->asic == NULL) {
661 printk("**WARNING** kmalloc failure in cat_init\n");
662 continue;
663 }
664 memset((*modpp)->asic, 0, sizeof(voyager_asic_t));
665 (*modpp)->asic->asic_id = VOYAGER_CAT_ID;
666 (*modpp)->asic->subaddr = VOYAGER_SUBADDR_HI;
667 (*modpp)->module_addr = i;
668 (*modpp)->scan_path_connected = 0;
669 if(i == VOYAGER_PSI) {
670 /* Exception leg for modules with no EEPROM */
671 printk("Module \"%s\"\n", cat_module_name(i));
672 continue;
673 }
674
675 CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET));
676 outb(VOYAGER_CAT_RUN, CAT_CMD);
677 cat_disconnect(*modpp, (*modpp)->asic);
678 if(cat_subread(*modpp, (*modpp)->asic,
679 VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size),
680 &eprom_size)) {
681 printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i);
682 outb(VOYAGER_CAT_END, CAT_CMD);
683 continue;
684 }
685 if(eprom_size > sizeof(eprom_buf)) {
686 printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size);
687 outb(VOYAGER_CAT_END, CAT_CMD);
688 continue;
689 }
690 outb(VOYAGER_CAT_END, CAT_CMD);
691 outb(VOYAGER_CAT_RUN, CAT_CMD);
692 CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size));
693 if(cat_subread(*modpp, (*modpp)->asic, 0,
694 eprom_size, eprom_buf)) {
695 outb(VOYAGER_CAT_END, CAT_CMD);
696 continue;
697 }
698 outb(VOYAGER_CAT_END, CAT_CMD);
699 printk("Module \"%s\", version 0x%x, tracer 0x%x, asics %d\n",
700 cat_module_name(i), eprom_hdr->version_id,
701 *((__u32 *)eprom_hdr->tracer), eprom_hdr->num_asics);
702 (*modpp)->ee_size = eprom_hdr->ee_size;
703 (*modpp)->num_asics = eprom_hdr->num_asics;
704 asicpp = &((*modpp)->asic);
705 sp_offset = eprom_hdr->scan_path_offset;
706 /* All we really care about are the Quad cards. We
707 * identify them because they are in a processor slot
708 * and have only four asics */
709 if((i < 0x10 || (i>=0x14 && i < 0x1c) || i>0x1f)) {
710 modpp = &((*modpp)->next);
711 continue;
712 }
713 /* Now we know it's in a processor slot, does it have
714 * a quad baseboard submodule */
715 outb(VOYAGER_CAT_RUN, CAT_CMD);
716 cat_read(*modpp, (*modpp)->asic, VOYAGER_SUBMODPRESENT,
717 &num_submodules);
718 /* lowest two bits, active low */
719 num_submodules = ~(0xfc | num_submodules);
720 CDEBUG(("VOYAGER CAT: %d submodules present\n", num_submodules));
721 if(num_submodules == 0) {
722 /* fill in the dyadic extended processors */
723 __u8 cpu = i & 0x07;
724
725 printk("Module \"%s\": Dyadic Processor Card\n",
726 cat_module_name(i));
727 voyager_extended_vic_processors |= (1<<cpu);
728 cpu += 4;
729 voyager_extended_vic_processors |= (1<<cpu);
730 outb(VOYAGER_CAT_END, CAT_CMD);
731 continue;
732 }
733
734 /* now we want to read the asics on the first submodule,
735 * which should be the quad base board */
736
737 cat_read(*modpp, (*modpp)->asic, VOYAGER_SUBMODSELECT, &val);
738 CDEBUG(("cat_init: SUBMODSELECT value = 0x%x\n", val));
739 val = (val & 0x7c) | VOYAGER_QUAD_BASEBOARD;
740 cat_write(*modpp, (*modpp)->asic, VOYAGER_SUBMODSELECT, val);
741
742 outb(VOYAGER_CAT_END, CAT_CMD);
743
744
745 CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET));
746 outb(VOYAGER_CAT_RUN, CAT_CMD);
747 cat_disconnect(*modpp, (*modpp)->asic);
748 if(cat_subread(*modpp, (*modpp)->asic,
749 VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size),
750 &eprom_size)) {
751 printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i);
752 outb(VOYAGER_CAT_END, CAT_CMD);
753 continue;
754 }
755 if(eprom_size > sizeof(eprom_buf)) {
756 printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size);
757 outb(VOYAGER_CAT_END, CAT_CMD);
758 continue;
759 }
760 outb(VOYAGER_CAT_END, CAT_CMD);
761 outb(VOYAGER_CAT_RUN, CAT_CMD);
762 CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size));
763 if(cat_subread(*modpp, (*modpp)->asic, 0,
764 eprom_size, eprom_buf)) {
765 outb(VOYAGER_CAT_END, CAT_CMD);
766 continue;
767 }
768 outb(VOYAGER_CAT_END, CAT_CMD);
769 /* Now do everything for the QBB submodule 1 */
770 (*modpp)->ee_size = eprom_hdr->ee_size;
771 (*modpp)->num_asics = eprom_hdr->num_asics;
772 asicpp = &((*modpp)->asic);
773 sp_offset = eprom_hdr->scan_path_offset;
774 /* get rid of the dummy CAT asic and read the real one */
775 kfree((*modpp)->asic);
776 for(asic=0; asic < (*modpp)->num_asics; asic++) {
777 int j;
778 voyager_asic_t *asicp = *asicpp
779 = kzalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count++];*/
780 voyager_sp_table_t *sp_table;
781 voyager_at_t *asic_table;
782 voyager_jtt_t *jtag_table;
783
784 if(asicp == NULL) {
785 printk("**WARNING** kmalloc failure in cat_init\n");
786 continue;
787 }
788 asicpp = &(asicp->next);
789 asicp->asic_location = asic;
790 sp_table = (voyager_sp_table_t *)(eprom_buf + sp_offset);
791 asicp->asic_id = sp_table->asic_id;
792 asic_table = (voyager_at_t *)(eprom_buf + sp_table->asic_data_offset);
793 for(j=0; j<4; j++)
794 asicp->jtag_id[j] = asic_table->jtag_id[j];
795 jtag_table = (voyager_jtt_t *)(eprom_buf + asic_table->jtag_offset);
796 asicp->ireg_length = jtag_table->ireg_len;
797 asicp->bit_location = (*modpp)->inst_bits;
798 (*modpp)->inst_bits += asicp->ireg_length;
799 if(asicp->ireg_length > (*modpp)->largest_reg)
800 (*modpp)->largest_reg = asicp->ireg_length;
801 if (asicp->ireg_length < (*modpp)->smallest_reg ||
802 (*modpp)->smallest_reg == 0)
803 (*modpp)->smallest_reg = asicp->ireg_length;
804 CDEBUG(("asic 0x%x, ireg_length=%d, bit_location=%d\n",
805 asicp->asic_id, asicp->ireg_length,
806 asicp->bit_location));
807 if(asicp->asic_id == VOYAGER_QUAD_QABC) {
808 CDEBUG(("VOYAGER CAT: QABC ASIC found\n"));
809 qabc_asic = asicp;
810 }
811 sp_offset += sizeof(voyager_sp_table_t);
812 }
813 CDEBUG(("Module inst_bits = %d, largest_reg = %d, smallest_reg=%d\n",
814 (*modpp)->inst_bits, (*modpp)->largest_reg,
815 (*modpp)->smallest_reg));
816 /* OK, now we have the QUAD ASICs set up, use them.
817 * we need to:
818 *
819 * 1. Find the Memory area for the Quad CPIs.
820 * 2. Find the Extended VIC processor
821 * 3. Configure a second extended VIC processor (This
822 * cannot be done for the 51xx.
823 * */
824 outb(VOYAGER_CAT_RUN, CAT_CMD);
825 cat_connect(*modpp, (*modpp)->asic);
826 CDEBUG(("CAT CONNECTED!!\n"));
827 cat_subread(*modpp, qabc_asic, 0, sizeof(qabc_data), qabc_data);
828 qic_addr = qabc_data[5] << 8;
829 qic_addr = (qic_addr | qabc_data[6]) << 8;
830 qic_addr = (qic_addr | qabc_data[7]) << 8;
831 printk("Module \"%s\": Quad Processor Card; CPI 0x%lx, SET=0x%x\n",
832 cat_module_name(i), qic_addr, qabc_data[8]);
833#if 0 /* plumbing fails---FIXME */
834 if((qabc_data[8] & 0xf0) == 0) {
835 /* FIXME: 32 way 8 CPU slot monster cannot be
836 * plumbed this way---need to check for it */
837
838 printk("Plumbing second Extended Quad Processor\n");
839 /* second VIC line hardwired to Quad CPU 1 */
840 qabc_data[8] |= 0x20;
841 cat_subwrite(*modpp, qabc_asic, 8, 1, &qabc_data[8]);
842#ifdef VOYAGER_CAT_DEBUG
843 /* verify plumbing */
844 cat_subread(*modpp, qabc_asic, 8, 1, &qabc_data[8]);
845 if((qabc_data[8] & 0xf0) == 0) {
846 CDEBUG(("PLUMBING FAILED: 0x%x\n", qabc_data[8]));
847 }
848#endif
849 }
850#endif
851
852 {
853 struct resource *res = kzalloc(sizeof(struct resource),GFP_KERNEL);
854 res->name = kmalloc(128, GFP_KERNEL);
855 sprintf((char *)res->name, "Voyager %s Quad CPI", cat_module_name(i));
856 res->start = qic_addr;
857 res->end = qic_addr + 0x3ff;
858 request_resource(&iomem_resource, res);
859 }
860
861 qic_addr = (unsigned long)ioremap(qic_addr, 0x400);
862
863 for(j = 0; j < 4; j++) {
864 __u8 cpu;
865
866 if(voyager_8slot) {
867 /* 8 slot has a different mapping,
868 * each slot has only one vic line, so
869 * 1 cpu in each slot must be < 8 */
870 cpu = (i & 0x07) + j*8;
871 } else {
872 cpu = (i & 0x03) + j*4;
873 }
874 if( (qabc_data[8] & (1<<j))) {
875 voyager_extended_vic_processors |= (1<<cpu);
876 }
877 if(qabc_data[8] & (1<<(j+4)) ) {
878 /* Second SET register plumbed: Quad
879 * card has two VIC connected CPUs.
880 * Secondary cannot be booted as a VIC
881 * CPU */
882 voyager_extended_vic_processors |= (1<<cpu);
883 voyager_allowed_boot_processors &= (~(1<<cpu));
884 }
885
886 voyager_quad_processors |= (1<<cpu);
887 voyager_quad_cpi_addr[cpu] = (struct voyager_qic_cpi *)
888 (qic_addr+(j<<8));
889 CDEBUG(("CPU%d: CPI address 0x%lx\n", cpu,
890 (unsigned long)voyager_quad_cpi_addr[cpu]));
891 }
892 outb(VOYAGER_CAT_END, CAT_CMD);
893
894
895
896 *asicpp = NULL;
897 modpp = &((*modpp)->next);
898 }
899 *modpp = NULL;
900 printk("CAT Bus Initialisation finished: extended procs 0x%x, quad procs 0x%x, allowed vic boot = 0x%x\n", voyager_extended_vic_processors, voyager_quad_processors, voyager_allowed_boot_processors);
901 request_resource(&ioport_resource, &vic_res);
902 if(voyager_quad_processors)
903 request_resource(&ioport_resource, &qic_res);
904 /* set up the front power switch */
905}
906
907int
908voyager_cat_readb(__u8 module, __u8 asic, int reg)
909{
910 return 0;
911}
912
913static int
914cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp)
915{
916 __u8 val;
917 int err = 0;
918
919 if(!modp->scan_path_connected)
920 return 0;
921 if(asicp->asic_id != VOYAGER_CAT_ID) {
922 CDEBUG(("cat_disconnect: ASIC is not CAT\n"));
923 return 1;
924 }
925 err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val);
926 if(err) {
927 CDEBUG(("cat_disconnect: failed to read SCANPATH\n"));
928 return err;
929 }
930 val &= VOYAGER_DISCONNECT_ASIC;
931 err = cat_write(modp, asicp, VOYAGER_SCANPATH, val);
932 if(err) {
933 CDEBUG(("cat_disconnect: failed to write SCANPATH\n"));
934 return err;
935 }
936 outb(VOYAGER_CAT_END, CAT_CMD);
937 outb(VOYAGER_CAT_RUN, CAT_CMD);
938 modp->scan_path_connected = 0;
939
940 return 0;
941}
942
943static int
944cat_connect(voyager_module_t *modp, voyager_asic_t *asicp)
945{
946 __u8 val;
947 int err = 0;
948
949 if(modp->scan_path_connected)
950 return 0;
951 if(asicp->asic_id != VOYAGER_CAT_ID) {
952 CDEBUG(("cat_connect: ASIC is not CAT\n"));
953 return 1;
954 }
955
956 err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val);
957 if(err) {
958 CDEBUG(("cat_connect: failed to read SCANPATH\n"));
959 return err;
960 }
961 val |= VOYAGER_CONNECT_ASIC;
962 err = cat_write(modp, asicp, VOYAGER_SCANPATH, val);
963 if(err) {
964 CDEBUG(("cat_connect: failed to write SCANPATH\n"));
965 return err;
966 }
967 outb(VOYAGER_CAT_END, CAT_CMD);
968 outb(VOYAGER_CAT_RUN, CAT_CMD);
969 modp->scan_path_connected = 1;
970
971 return 0;
972}
973
974void
975voyager_cat_power_off(void)
976{
977 /* Power the machine off by writing to the PSI over the CAT
978 * bus */
979 __u8 data;
980 voyager_module_t psi = { 0 };
981 voyager_asic_t psi_asic = { 0 };
982
983 psi.asic = &psi_asic;
984 psi.asic->asic_id = VOYAGER_CAT_ID;
985 psi.asic->subaddr = VOYAGER_SUBADDR_HI;
986 psi.module_addr = VOYAGER_PSI;
987 psi.scan_path_connected = 0;
988
989 outb(VOYAGER_CAT_END, CAT_CMD);
990 /* Connect the PSI to the CAT Bus */
991 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
992 outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT);
993 outb(VOYAGER_CAT_RUN, CAT_CMD);
994 cat_disconnect(&psi, &psi_asic);
995 /* Read the status */
996 cat_subread(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data);
997 outb(VOYAGER_CAT_END, CAT_CMD);
998 CDEBUG(("PSI STATUS 0x%x\n", data));
999 /* These two writes are power off prep and perform */
1000 data = PSI_CLEAR;
1001 outb(VOYAGER_CAT_RUN, CAT_CMD);
1002 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data);
1003 outb(VOYAGER_CAT_END, CAT_CMD);
1004 data = PSI_POWER_DOWN;
1005 outb(VOYAGER_CAT_RUN, CAT_CMD);
1006 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data);
1007 outb(VOYAGER_CAT_END, CAT_CMD);
1008}
1009
1010struct voyager_status voyager_status = { 0 };
1011
1012void
1013voyager_cat_psi(__u8 cmd, __u16 reg, __u8 *data)
1014{
1015 voyager_module_t psi = { 0 };
1016 voyager_asic_t psi_asic = { 0 };
1017
1018 psi.asic = &psi_asic;
1019 psi.asic->asic_id = VOYAGER_CAT_ID;
1020 psi.asic->subaddr = VOYAGER_SUBADDR_HI;
1021 psi.module_addr = VOYAGER_PSI;
1022 psi.scan_path_connected = 0;
1023
1024 outb(VOYAGER_CAT_END, CAT_CMD);
1025 /* Connect the PSI to the CAT Bus */
1026 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
1027 outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT);
1028 outb(VOYAGER_CAT_RUN, CAT_CMD);
1029 cat_disconnect(&psi, &psi_asic);
1030 switch(cmd) {
1031 case VOYAGER_PSI_READ:
1032 cat_read(&psi, &psi_asic, reg, data);
1033 break;
1034 case VOYAGER_PSI_WRITE:
1035 cat_write(&psi, &psi_asic, reg, *data);
1036 break;
1037 case VOYAGER_PSI_SUBREAD:
1038 cat_subread(&psi, &psi_asic, reg, 1, data);
1039 break;
1040 case VOYAGER_PSI_SUBWRITE:
1041 cat_subwrite(&psi, &psi_asic, reg, 1, data);
1042 break;
1043 default:
1044 printk(KERN_ERR "Voyager PSI, unrecognised command %d\n", cmd);
1045 break;
1046 }
1047 outb(VOYAGER_CAT_END, CAT_CMD);
1048}
1049
1050void
1051voyager_cat_do_common_interrupt(void)
1052{
1053 /* This is caused either by a memory parity error or something
1054 * in the PSI */
1055 __u8 data;
1056 voyager_module_t psi = { 0 };
1057 voyager_asic_t psi_asic = { 0 };
1058 struct voyager_psi psi_reg;
1059 int i;
1060 re_read:
1061 psi.asic = &psi_asic;
1062 psi.asic->asic_id = VOYAGER_CAT_ID;
1063 psi.asic->subaddr = VOYAGER_SUBADDR_HI;
1064 psi.module_addr = VOYAGER_PSI;
1065 psi.scan_path_connected = 0;
1066
1067 outb(VOYAGER_CAT_END, CAT_CMD);
1068 /* Connect the PSI to the CAT Bus */
1069 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
1070 outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT);
1071 outb(VOYAGER_CAT_RUN, CAT_CMD);
1072 cat_disconnect(&psi, &psi_asic);
1073 /* Read the status. NOTE: Need to read *all* the PSI regs here
1074 * otherwise the cmn int will be reasserted */
1075 for(i = 0; i < sizeof(psi_reg.regs); i++) {
1076 cat_read(&psi, &psi_asic, i, &((__u8 *)&psi_reg.regs)[i]);
1077 }
1078 outb(VOYAGER_CAT_END, CAT_CMD);
1079 if((psi_reg.regs.checkbit & 0x02) == 0) {
1080 psi_reg.regs.checkbit |= 0x02;
1081 cat_write(&psi, &psi_asic, 5, psi_reg.regs.checkbit);
1082 printk("VOYAGER RE-READ PSI\n");
1083 goto re_read;
1084 }
1085 outb(VOYAGER_CAT_RUN, CAT_CMD);
1086 for(i = 0; i < sizeof(psi_reg.subregs); i++) {
1087 /* This looks strange, but the PSI doesn't do auto increment
1088 * correctly */
1089 cat_subread(&psi, &psi_asic, VOYAGER_PSI_SUPPLY_REG + i,
1090 1, &((__u8 *)&psi_reg.subregs)[i]);
1091 }
1092 outb(VOYAGER_CAT_END, CAT_CMD);
1093#ifdef VOYAGER_CAT_DEBUG
1094 printk("VOYAGER PSI: ");
1095 for(i=0; i<sizeof(psi_reg.regs); i++)
1096 printk("%02x ", ((__u8 *)&psi_reg.regs)[i]);
1097 printk("\n ");
1098 for(i=0; i<sizeof(psi_reg.subregs); i++)
1099 printk("%02x ", ((__u8 *)&psi_reg.subregs)[i]);
1100 printk("\n");
1101#endif
1102 if(psi_reg.regs.intstatus & PSI_MON) {
1103 /* switch off or power fail */
1104
1105 if(psi_reg.subregs.supply & PSI_SWITCH_OFF) {
1106 if(voyager_status.switch_off) {
1107 printk(KERN_ERR "Voyager front panel switch turned off again---Immediate power off!\n");
1108 voyager_cat_power_off();
1109 /* not reached */
1110 } else {
1111 printk(KERN_ERR "Voyager front panel switch turned off\n");
1112 voyager_status.switch_off = 1;
1113 voyager_status.request_from_kernel = 1;
1114 wake_up_process(voyager_thread);
1115 }
1116 /* Tell the hardware we're taking care of the
1117 * shutdown, otherwise it will power the box off
1118 * within 3 seconds of the switch being pressed and,
1119 * which is much more important to us, continue to
1120 * assert the common interrupt */
1121 data = PSI_CLR_SWITCH_OFF;
1122 outb(VOYAGER_CAT_RUN, CAT_CMD);
1123 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_SUPPLY_REG,
1124 1, &data);
1125 outb(VOYAGER_CAT_END, CAT_CMD);
1126 } else {
1127
1128 VDEBUG(("Voyager ac fail reg 0x%x\n",
1129 psi_reg.subregs.ACfail));
1130 if((psi_reg.subregs.ACfail & AC_FAIL_STAT_CHANGE) == 0) {
1131 /* No further update */
1132 return;
1133 }
1134#if 0
1135 /* Don't bother trying to find out who failed.
1136 * FIXME: This probably makes the code incorrect on
1137 * anything other than a 345x */
1138 for(i=0; i< 5; i++) {
1139 if( psi_reg.subregs.ACfail &(1<<i)) {
1140 break;
1141 }
1142 }
1143 printk(KERN_NOTICE "AC FAIL IN SUPPLY %d\n", i);
1144#endif
1145 /* DON'T do this: it shuts down the AC PSI
1146 outb(VOYAGER_CAT_RUN, CAT_CMD);
1147 data = PSI_MASK_MASK | i;
1148 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_MASK,
1149 1, &data);
1150 outb(VOYAGER_CAT_END, CAT_CMD);
1151 */
1152 printk(KERN_ERR "Voyager AC power failure\n");
1153 outb(VOYAGER_CAT_RUN, CAT_CMD);
1154 data = PSI_COLD_START;
1155 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG,
1156 1, &data);
1157 outb(VOYAGER_CAT_END, CAT_CMD);
1158 voyager_status.power_fail = 1;
1159 voyager_status.request_from_kernel = 1;
1160 wake_up_process(voyager_thread);
1161 }
1162
1163
1164 } else if(psi_reg.regs.intstatus & PSI_FAULT) {
1165 /* Major fault! */
1166 printk(KERN_ERR "Voyager PSI Detected major fault, immediate power off!\n");
1167 voyager_cat_power_off();
1168 /* not reached */
1169 } else if(psi_reg.regs.intstatus & (PSI_DC_FAIL | PSI_ALARM
1170 | PSI_CURRENT | PSI_DVM
1171 | PSI_PSCFAULT | PSI_STAT_CHG)) {
1172 /* other psi fault */
1173
1174 printk(KERN_WARNING "Voyager PSI status 0x%x\n", data);
1175 /* clear the PSI fault */
1176 outb(VOYAGER_CAT_RUN, CAT_CMD);
1177 cat_write(&psi, &psi_asic, VOYAGER_PSI_STATUS_REG, 0);
1178 outb(VOYAGER_CAT_END, CAT_CMD);
1179 }
1180}
diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c
new file mode 100644
index 000000000000..b87f8548e75a
--- /dev/null
+++ b/arch/x86/mach-voyager/voyager_smp.c
@@ -0,0 +1,1952 @@
1/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 1999,2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/kernel/voyager_smp.c
8 *
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
11 */
12#include <linux/module.h>
13#include <linux/mm.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/mc146818rtc.h>
17#include <linux/cache.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/bootmem.h>
22#include <linux/completion.h>
23#include <asm/desc.h>
24#include <asm/voyager.h>
25#include <asm/vic.h>
26#include <asm/mtrr.h>
27#include <asm/pgalloc.h>
28#include <asm/tlbflush.h>
29#include <asm/arch_hooks.h>
30
31/* TLB state -- visible externally, indexed physically */
32DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
33
34/* CPU IRQ affinity -- set to all ones initially */
35static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
36
37/* per CPU data structure (for /proc/cpuinfo et al), visible externally
38 * indexed physically */
39struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
40EXPORT_SYMBOL(cpu_data);
41
42/* physical ID of the CPU used to boot the system */
43unsigned char boot_cpu_id;
44
45/* The memory line addresses for the Quad CPIs */
46struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
47
48/* The masks for the Extended VIC processors, filled in by cat_init */
49__u32 voyager_extended_vic_processors = 0;
50
51/* Masks for the extended Quad processors which cannot be VIC booted */
52__u32 voyager_allowed_boot_processors = 0;
53
54/* The mask for the Quad Processors (both extended and non-extended) */
55__u32 voyager_quad_processors = 0;
56
57/* Total count of live CPUs, used in process.c to display
58 * the CPU information and in irq.c for the per CPU irq
59 * activity count. Finally exported by i386_ksyms.c */
60static int voyager_extended_cpus = 1;
61
62/* Have we found an SMP box - used by time.c to do the profiling
63 interrupt for timeslicing; do not set to 1 until the per CPU timer
64 interrupt is active */
65int smp_found_config = 0;
66
67/* Used for the invalidate map that's also checked in the spinlock */
68static volatile unsigned long smp_invalidate_needed;
69
70/* Bitmask of currently online CPUs - used by setup.c for
71 /proc/cpuinfo, visible externally but still physical */
72cpumask_t cpu_online_map = CPU_MASK_NONE;
73EXPORT_SYMBOL(cpu_online_map);
74
75/* Bitmask of CPUs present in the system - exported by i386_syms.c, used
76 * by scheduler but indexed physically */
77cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
78
79
80/* The internal functions */
81static void send_CPI(__u32 cpuset, __u8 cpi);
82static void ack_CPI(__u8 cpi);
83static int ack_QIC_CPI(__u8 cpi);
84static void ack_special_QIC_CPI(__u8 cpi);
85static void ack_VIC_CPI(__u8 cpi);
86static void send_CPI_allbutself(__u8 cpi);
87static void mask_vic_irq(unsigned int irq);
88static void unmask_vic_irq(unsigned int irq);
89static unsigned int startup_vic_irq(unsigned int irq);
90static void enable_local_vic_irq(unsigned int irq);
91static void disable_local_vic_irq(unsigned int irq);
92static void before_handle_vic_irq(unsigned int irq);
93static void after_handle_vic_irq(unsigned int irq);
94static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
95static void ack_vic_irq(unsigned int irq);
96static void vic_enable_cpi(void);
97static void do_boot_cpu(__u8 cpuid);
98static void do_quad_bootstrap(void);
99
100int hard_smp_processor_id(void);
101int safe_smp_processor_id(void);
102
103/* Inline functions */
104static inline void
105send_one_QIC_CPI(__u8 cpu, __u8 cpi)
106{
107 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
108 (smp_processor_id() << 16) + cpi;
109}
110
111static inline void
112send_QIC_CPI(__u32 cpuset, __u8 cpi)
113{
114 int cpu;
115
116 for_each_online_cpu(cpu) {
117 if(cpuset & (1<<cpu)) {
118#ifdef VOYAGER_DEBUG
119 if(!cpu_isset(cpu, cpu_online_map))
120 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
121#endif
122 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
123 }
124 }
125}
126
127static inline void
128wrapper_smp_local_timer_interrupt(void)
129{
130 irq_enter();
131 smp_local_timer_interrupt();
132 irq_exit();
133}
134
135static inline void
136send_one_CPI(__u8 cpu, __u8 cpi)
137{
138 if(voyager_quad_processors & (1<<cpu))
139 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
140 else
141 send_CPI(1<<cpu, cpi);
142}
143
144static inline void
145send_CPI_allbutself(__u8 cpi)
146{
147 __u8 cpu = smp_processor_id();
148 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
149 send_CPI(mask, cpi);
150}
151
152static inline int
153is_cpu_quad(void)
154{
155 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
156 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
157}
158
159static inline int
160is_cpu_extended(void)
161{
162 __u8 cpu = hard_smp_processor_id();
163
164 return(voyager_extended_vic_processors & (1<<cpu));
165}
166
167static inline int
168is_cpu_vic_boot(void)
169{
170 __u8 cpu = hard_smp_processor_id();
171
172 return(voyager_extended_vic_processors
173 & voyager_allowed_boot_processors & (1<<cpu));
174}
175
176
177static inline void
178ack_CPI(__u8 cpi)
179{
180 switch(cpi) {
181 case VIC_CPU_BOOT_CPI:
182 if(is_cpu_quad() && !is_cpu_vic_boot())
183 ack_QIC_CPI(cpi);
184 else
185 ack_VIC_CPI(cpi);
186 break;
187 case VIC_SYS_INT:
188 case VIC_CMN_INT:
189 /* These are slightly strange. Even on the Quad card,
190 * They are vectored as VIC CPIs */
191 if(is_cpu_quad())
192 ack_special_QIC_CPI(cpi);
193 else
194 ack_VIC_CPI(cpi);
195 break;
196 default:
197 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
198 break;
199 }
200}
201
202/* local variables */
203
204/* The VIC IRQ descriptors -- these look almost identical to the
205 * 8259 IRQs except that masks and things must be kept per processor
206 */
207static struct irq_chip vic_chip = {
208 .name = "VIC",
209 .startup = startup_vic_irq,
210 .mask = mask_vic_irq,
211 .unmask = unmask_vic_irq,
212 .set_affinity = set_vic_irq_affinity,
213};
214
215/* used to count up as CPUs are brought on line (starts at 0) */
216static int cpucount = 0;
217
218/* steal a page from the bottom of memory for the trampoline and
219 * squirrel its address away here. This will be in kernel virtual
220 * space */
221static __u32 trampoline_base;
222
223/* The per cpu profile stuff - used in smp_local_timer_interrupt */
224static DEFINE_PER_CPU(int, prof_multiplier) = 1;
225static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
226static DEFINE_PER_CPU(int, prof_counter) = 1;
227
228/* the map used to check if a CPU has booted */
229static __u32 cpu_booted_map;
230
231/* the synchronize flag used to hold all secondary CPUs spinning in
232 * a tight loop until the boot sequence is ready for them */
233static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
234
235/* This is for the new dynamic CPU boot code */
236cpumask_t cpu_callin_map = CPU_MASK_NONE;
237cpumask_t cpu_callout_map = CPU_MASK_NONE;
238EXPORT_SYMBOL(cpu_callout_map);
239cpumask_t cpu_possible_map = CPU_MASK_NONE;
240EXPORT_SYMBOL(cpu_possible_map);
241
242/* The per processor IRQ masks (these are usually kept in sync) */
243static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
244
245/* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
246static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
247
248/* Lock for enable/disable of VIC interrupts */
249static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
250
251/* The boot processor is correctly set up in PC mode when it
252 * comes up, but the secondaries need their master/slave 8259
253 * pairs initializing correctly */
254
255/* Interrupt counters (per cpu) and total - used to try to
256 * even up the interrupt handling routines */
257static long vic_intr_total = 0;
258static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
259static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
260
261/* Since we can only use CPI0, we fake all the other CPIs */
262static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
263
264/* debugging routine to read the isr of the cpu's pic */
265static inline __u16
266vic_read_isr(void)
267{
268 __u16 isr;
269
270 outb(0x0b, 0xa0);
271 isr = inb(0xa0) << 8;
272 outb(0x0b, 0x20);
273 isr |= inb(0x20);
274
275 return isr;
276}
277
278static __init void
279qic_setup(void)
280{
281 if(!is_cpu_quad()) {
282 /* not a quad, no setup */
283 return;
284 }
285 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
286 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
287
288 if(is_cpu_extended()) {
289 /* the QIC duplicate of the VIC base register */
290 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
291 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
292
293 /* FIXME: should set up the QIC timer and memory parity
294 * error vectors here */
295 }
296}
297
298static __init void
299vic_setup_pic(void)
300{
301 outb(1, VIC_REDIRECT_REGISTER_1);
302 /* clear the claim registers for dynamic routing */
303 outb(0, VIC_CLAIM_REGISTER_0);
304 outb(0, VIC_CLAIM_REGISTER_1);
305
306 outb(0, VIC_PRIORITY_REGISTER);
307 /* Set the Primary and Secondary Microchannel vector
308 * bases to be the same as the ordinary interrupts
309 *
310 * FIXME: This would be more efficient using separate
311 * vectors. */
312 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
313 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
314 /* Now initiallise the master PIC belonging to this CPU by
315 * sending the four ICWs */
316
317 /* ICW1: level triggered, ICW4 needed */
318 outb(0x19, 0x20);
319
320 /* ICW2: vector base */
321 outb(FIRST_EXTERNAL_VECTOR, 0x21);
322
323 /* ICW3: slave at line 2 */
324 outb(0x04, 0x21);
325
326 /* ICW4: 8086 mode */
327 outb(0x01, 0x21);
328
329 /* now the same for the slave PIC */
330
331 /* ICW1: level trigger, ICW4 needed */
332 outb(0x19, 0xA0);
333
334 /* ICW2: slave vector base */
335 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
336
337 /* ICW3: slave ID */
338 outb(0x02, 0xA1);
339
340 /* ICW4: 8086 mode */
341 outb(0x01, 0xA1);
342}
343
344static void
345do_quad_bootstrap(void)
346{
347 if(is_cpu_quad() && is_cpu_vic_boot()) {
348 int i;
349 unsigned long flags;
350 __u8 cpuid = hard_smp_processor_id();
351
352 local_irq_save(flags);
353
354 for(i = 0; i<4; i++) {
355 /* FIXME: this would be >>3 &0x7 on the 32 way */
356 if(((cpuid >> 2) & 0x03) == i)
357 /* don't lower our own mask! */
358 continue;
359
360 /* masquerade as local Quad CPU */
361 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
362 /* enable the startup CPI */
363 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
364 /* restore cpu id */
365 outb(0, QIC_PROCESSOR_ID);
366 }
367 local_irq_restore(flags);
368 }
369}
370
371
372/* Set up all the basic stuff: read the SMP config and make all the
373 * SMP information reflect only the boot cpu. All others will be
374 * brought on-line later. */
375void __init
376find_smp_config(void)
377{
378 int i;
379
380 boot_cpu_id = hard_smp_processor_id();
381
382 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
383
384 /* initialize the CPU structures (moved from smp_boot_cpus) */
385 for(i=0; i<NR_CPUS; i++) {
386 cpu_irq_affinity[i] = ~0;
387 }
388 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
389
390 /* The boot CPU must be extended */
391 voyager_extended_vic_processors = 1<<boot_cpu_id;
392 /* initially, all of the first 8 cpu's can boot */
393 voyager_allowed_boot_processors = 0xff;
394 /* set up everything for just this CPU, we can alter
395 * this as we start the other CPUs later */
396 /* now get the CPU disposition from the extended CMOS */
397 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
398 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
399 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
400 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
401 cpu_possible_map = phys_cpu_present_map;
402 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
403 /* Here we set up the VIC to enable SMP */
404 /* enable the CPIs by writing the base vector to their register */
405 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
406 outb(1, VIC_REDIRECT_REGISTER_1);
407 /* set the claim registers for static routing --- Boot CPU gets
408 * all interrupts untill all other CPUs started */
409 outb(0xff, VIC_CLAIM_REGISTER_0);
410 outb(0xff, VIC_CLAIM_REGISTER_1);
411 /* Set the Primary and Secondary Microchannel vector
412 * bases to be the same as the ordinary interrupts
413 *
414 * FIXME: This would be more efficient using separate
415 * vectors. */
416 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
417 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
418
419 /* Finally tell the firmware that we're driving */
420 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
421 VOYAGER_SUS_IN_CONTROL_PORT);
422
423 current_thread_info()->cpu = boot_cpu_id;
424 x86_write_percpu(cpu_number, boot_cpu_id);
425}
426
427/*
428 * The bootstrap kernel entry code has set these up. Save them
429 * for a given CPU, id is physical */
430void __init
431smp_store_cpu_info(int id)
432{
433 struct cpuinfo_x86 *c=&cpu_data[id];
434
435 *c = boot_cpu_data;
436
437 identify_secondary_cpu(c);
438}
439
440/* set up the trampoline and return the physical address of the code */
441static __u32 __init
442setup_trampoline(void)
443{
444 /* these two are global symbols in trampoline.S */
445 extern __u8 trampoline_end[];
446 extern __u8 trampoline_data[];
447
448 memcpy((__u8 *)trampoline_base, trampoline_data,
449 trampoline_end - trampoline_data);
450 return virt_to_phys((__u8 *)trampoline_base);
451}
452
453/* Routine initially called when a non-boot CPU is brought online */
454static void __init
455start_secondary(void *unused)
456{
457 __u8 cpuid = hard_smp_processor_id();
458 /* external functions not defined in the headers */
459 extern void calibrate_delay(void);
460
461 cpu_init();
462
463 /* OK, we're in the routine */
464 ack_CPI(VIC_CPU_BOOT_CPI);
465
466 /* setup the 8259 master slave pair belonging to this CPU ---
467 * we won't actually receive any until the boot CPU
468 * relinquishes it's static routing mask */
469 vic_setup_pic();
470
471 qic_setup();
472
473 if(is_cpu_quad() && !is_cpu_vic_boot()) {
474 /* clear the boot CPI */
475 __u8 dummy;
476
477 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
478 printk("read dummy %d\n", dummy);
479 }
480
481 /* lower the mask to receive CPIs */
482 vic_enable_cpi();
483
484 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
485
486 /* enable interrupts */
487 local_irq_enable();
488
489 /* get our bogomips */
490 calibrate_delay();
491
492 /* save our processor parameters */
493 smp_store_cpu_info(cpuid);
494
495 /* if we're a quad, we may need to bootstrap other CPUs */
496 do_quad_bootstrap();
497
498 /* FIXME: this is rather a poor hack to prevent the CPU
499 * activating softirqs while it's supposed to be waiting for
500 * permission to proceed. Without this, the new per CPU stuff
501 * in the softirqs will fail */
502 local_irq_disable();
503 cpu_set(cpuid, cpu_callin_map);
504
505 /* signal that we're done */
506 cpu_booted_map = 1;
507
508 while (!cpu_isset(cpuid, smp_commenced_mask))
509 rep_nop();
510 local_irq_enable();
511
512 local_flush_tlb();
513
514 cpu_set(cpuid, cpu_online_map);
515 wmb();
516 cpu_idle();
517}
518
519
520/* Routine to kick start the given CPU and wait for it to report ready
521 * (or timeout in startup). When this routine returns, the requested
522 * CPU is either fully running and configured or known to be dead.
523 *
524 * We call this routine sequentially 1 CPU at a time, so no need for
525 * locking */
526
527static void __init
528do_boot_cpu(__u8 cpu)
529{
530 struct task_struct *idle;
531 int timeout;
532 unsigned long flags;
533 int quad_boot = (1<<cpu) & voyager_quad_processors
534 & ~( voyager_extended_vic_processors
535 & voyager_allowed_boot_processors);
536
537 /* This is an area in head.S which was used to set up the
538 * initial kernel stack. We need to alter this to give the
539 * booting CPU a new stack (taken from its idle process) */
540 extern struct {
541 __u8 *esp;
542 unsigned short ss;
543 } stack_start;
544 /* This is the format of the CPI IDT gate (in real mode) which
545 * we're hijacking to boot the CPU */
546 union IDTFormat {
547 struct seg {
548 __u16 Offset;
549 __u16 Segment;
550 } idt;
551 __u32 val;
552 } hijack_source;
553
554 __u32 *hijack_vector;
555 __u32 start_phys_address = setup_trampoline();
556
557 /* There's a clever trick to this: The linux trampoline is
558 * compiled to begin at absolute location zero, so make the
559 * address zero but have the data segment selector compensate
560 * for the actual address */
561 hijack_source.idt.Offset = start_phys_address & 0x000F;
562 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
563
564 cpucount++;
565 alternatives_smp_switch(1);
566
567 idle = fork_idle(cpu);
568 if(IS_ERR(idle))
569 panic("failed fork for CPU%d", cpu);
570 idle->thread.eip = (unsigned long) start_secondary;
571 /* init_tasks (in sched.c) is indexed logically */
572 stack_start.esp = (void *) idle->thread.esp;
573
574 init_gdt(cpu);
575 per_cpu(current_task, cpu) = idle;
576 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
577 irq_ctx_init(cpu);
578
579 /* Note: Don't modify initial ss override */
580 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
581 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
582 hijack_source.idt.Offset, stack_start.esp));
583
584 /* init lowmem identity mapping */
585 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
586 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
587 flush_tlb_all();
588
589 if(quad_boot) {
590 printk("CPU %d: non extended Quad boot\n", cpu);
591 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
592 *hijack_vector = hijack_source.val;
593 } else {
594 printk("CPU%d: extended VIC boot\n", cpu);
595 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
596 *hijack_vector = hijack_source.val;
597 /* VIC errata, may also receive interrupt at this address */
598 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
599 *hijack_vector = hijack_source.val;
600 }
601 /* All non-boot CPUs start with interrupts fully masked. Need
602 * to lower the mask of the CPI we're about to send. We do
603 * this in the VIC by masquerading as the processor we're
604 * about to boot and lowering its interrupt mask */
605 local_irq_save(flags);
606 if(quad_boot) {
607 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
608 } else {
609 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
610 /* here we're altering registers belonging to `cpu' */
611
612 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
613 /* now go back to our original identity */
614 outb(boot_cpu_id, VIC_PROCESSOR_ID);
615
616 /* and boot the CPU */
617
618 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
619 }
620 cpu_booted_map = 0;
621 local_irq_restore(flags);
622
623 /* now wait for it to become ready (or timeout) */
624 for(timeout = 0; timeout < 50000; timeout++) {
625 if(cpu_booted_map)
626 break;
627 udelay(100);
628 }
629 /* reset the page table */
630 zap_low_mappings();
631
632 if (cpu_booted_map) {
633 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
634 cpu, smp_processor_id()));
635
636 printk("CPU%d: ", cpu);
637 print_cpu_info(&cpu_data[cpu]);
638 wmb();
639 cpu_set(cpu, cpu_callout_map);
640 cpu_set(cpu, cpu_present_map);
641 }
642 else {
643 printk("CPU%d FAILED TO BOOT: ", cpu);
644 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
645 printk("Stuck.\n");
646 else
647 printk("Not responding.\n");
648
649 cpucount--;
650 }
651}
652
653void __init
654smp_boot_cpus(void)
655{
656 int i;
657
658 /* CAT BUS initialisation must be done after the memory */
659 /* FIXME: The L4 has a catbus too, it just needs to be
660 * accessed in a totally different way */
661 if(voyager_level == 5) {
662 voyager_cat_init();
663
664 /* now that the cat has probed the Voyager System Bus, sanity
665 * check the cpu map */
666 if( ((voyager_quad_processors | voyager_extended_vic_processors)
667 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
668 /* should panic */
669 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
670 }
671 } else if(voyager_level == 4)
672 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
673
674 /* this sets up the idle task to run on the current cpu */
675 voyager_extended_cpus = 1;
676 /* Remove the global_irq_holder setting, it triggers a BUG() on
677 * schedule at the moment */
678 //global_irq_holder = boot_cpu_id;
679
680 /* FIXME: Need to do something about this but currently only works
681 * on CPUs with a tsc which none of mine have.
682 smp_tune_scheduling();
683 */
684 smp_store_cpu_info(boot_cpu_id);
685 printk("CPU%d: ", boot_cpu_id);
686 print_cpu_info(&cpu_data[boot_cpu_id]);
687
688 if(is_cpu_quad()) {
689 /* booting on a Quad CPU */
690 printk("VOYAGER SMP: Boot CPU is Quad\n");
691 qic_setup();
692 do_quad_bootstrap();
693 }
694
695 /* enable our own CPIs */
696 vic_enable_cpi();
697
698 cpu_set(boot_cpu_id, cpu_online_map);
699 cpu_set(boot_cpu_id, cpu_callout_map);
700
701 /* loop over all the extended VIC CPUs and boot them. The
702 * Quad CPUs must be bootstrapped by their extended VIC cpu */
703 for(i = 0; i < NR_CPUS; i++) {
704 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
705 continue;
706 do_boot_cpu(i);
707 /* This udelay seems to be needed for the Quad boots
708 * don't remove unless you know what you're doing */
709 udelay(1000);
710 }
711 /* we could compute the total bogomips here, but why bother?,
712 * Code added from smpboot.c */
713 {
714 unsigned long bogosum = 0;
715 for (i = 0; i < NR_CPUS; i++)
716 if (cpu_isset(i, cpu_online_map))
717 bogosum += cpu_data[i].loops_per_jiffy;
718 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
719 cpucount+1,
720 bogosum/(500000/HZ),
721 (bogosum/(5000/HZ))%100);
722 }
723 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
724 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
725 /* that's it, switch to symmetric mode */
726 outb(0, VIC_PRIORITY_REGISTER);
727 outb(0, VIC_CLAIM_REGISTER_0);
728 outb(0, VIC_CLAIM_REGISTER_1);
729
730 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
731}
732
733/* Reload the secondary CPUs task structure (this function does not
734 * return ) */
735void __init
736initialize_secondary(void)
737{
738#if 0
739 // AC kernels only
740 set_current(hard_get_current());
741#endif
742
743 /*
744 * We don't actually need to load the full TSS,
745 * basically just the stack pointer and the eip.
746 */
747
748 asm volatile(
749 "movl %0,%%esp\n\t"
750 "jmp *%1"
751 :
752 :"r" (current->thread.esp),"r" (current->thread.eip));
753}
754
755/* handle a Voyager SYS_INT -- If we don't, the base board will
756 * panic the system.
757 *
758 * System interrupts occur because some problem was detected on the
759 * various busses. To find out what you have to probe all the
760 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
761fastcall void
762smp_vic_sys_interrupt(struct pt_regs *regs)
763{
764 ack_CPI(VIC_SYS_INT);
765 printk("Voyager SYSTEM INTERRUPT\n");
766}
767
768/* Handle a voyager CMN_INT; These interrupts occur either because of
769 * a system status change or because a single bit memory error
770 * occurred. FIXME: At the moment, ignore all this. */
771fastcall void
772smp_vic_cmn_interrupt(struct pt_regs *regs)
773{
774 static __u8 in_cmn_int = 0;
775 static DEFINE_SPINLOCK(cmn_int_lock);
776
777 /* common ints are broadcast, so make sure we only do this once */
778 _raw_spin_lock(&cmn_int_lock);
779 if(in_cmn_int)
780 goto unlock_end;
781
782 in_cmn_int++;
783 _raw_spin_unlock(&cmn_int_lock);
784
785 VDEBUG(("Voyager COMMON INTERRUPT\n"));
786
787 if(voyager_level == 5)
788 voyager_cat_do_common_interrupt();
789
790 _raw_spin_lock(&cmn_int_lock);
791 in_cmn_int = 0;
792 unlock_end:
793 _raw_spin_unlock(&cmn_int_lock);
794 ack_CPI(VIC_CMN_INT);
795}
796
797/*
798 * Reschedule call back. Nothing to do, all the work is done
799 * automatically when we return from the interrupt. */
800static void
801smp_reschedule_interrupt(void)
802{
803 /* do nothing */
804}
805
806static struct mm_struct * flush_mm;
807static unsigned long flush_va;
808static DEFINE_SPINLOCK(tlbstate_lock);
809#define FLUSH_ALL 0xffffffff
810
811/*
812 * We cannot call mmdrop() because we are in interrupt context,
813 * instead update mm->cpu_vm_mask.
814 *
815 * We need to reload %cr3 since the page tables may be going
816 * away from under us..
817 */
818static inline void
819leave_mm (unsigned long cpu)
820{
821 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
822 BUG();
823 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
824 load_cr3(swapper_pg_dir);
825}
826
827
828/*
829 * Invalidate call-back
830 */
831static void
832smp_invalidate_interrupt(void)
833{
834 __u8 cpu = smp_processor_id();
835
836 if (!test_bit(cpu, &smp_invalidate_needed))
837 return;
838 /* This will flood messages. Don't uncomment unless you see
839 * Problems with cross cpu invalidation
840 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
841 smp_processor_id()));
842 */
843
844 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
845 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
846 if (flush_va == FLUSH_ALL)
847 local_flush_tlb();
848 else
849 __flush_tlb_one(flush_va);
850 } else
851 leave_mm(cpu);
852 }
853 smp_mb__before_clear_bit();
854 clear_bit(cpu, &smp_invalidate_needed);
855 smp_mb__after_clear_bit();
856}
857
858/* All the new flush operations for 2.4 */
859
860
861/* This routine is called with a physical cpu mask */
862static void
863voyager_flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
864 unsigned long va)
865{
866 int stuck = 50000;
867
868 if (!cpumask)
869 BUG();
870 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
871 BUG();
872 if (cpumask & (1 << smp_processor_id()))
873 BUG();
874 if (!mm)
875 BUG();
876
877 spin_lock(&tlbstate_lock);
878
879 flush_mm = mm;
880 flush_va = va;
881 atomic_set_mask(cpumask, &smp_invalidate_needed);
882 /*
883 * We have to send the CPI only to
884 * CPUs affected.
885 */
886 send_CPI(cpumask, VIC_INVALIDATE_CPI);
887
888 while (smp_invalidate_needed) {
889 mb();
890 if(--stuck == 0) {
891 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
892 break;
893 }
894 }
895
896 /* Uncomment only to debug invalidation problems
897 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
898 */
899
900 flush_mm = NULL;
901 flush_va = 0;
902 spin_unlock(&tlbstate_lock);
903}
904
905void
906flush_tlb_current_task(void)
907{
908 struct mm_struct *mm = current->mm;
909 unsigned long cpu_mask;
910
911 preempt_disable();
912
913 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
914 local_flush_tlb();
915 if (cpu_mask)
916 voyager_flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
917
918 preempt_enable();
919}
920
921
922void
923flush_tlb_mm (struct mm_struct * mm)
924{
925 unsigned long cpu_mask;
926
927 preempt_disable();
928
929 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
930
931 if (current->active_mm == mm) {
932 if (current->mm)
933 local_flush_tlb();
934 else
935 leave_mm(smp_processor_id());
936 }
937 if (cpu_mask)
938 voyager_flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
939
940 preempt_enable();
941}
942
943void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
944{
945 struct mm_struct *mm = vma->vm_mm;
946 unsigned long cpu_mask;
947
948 preempt_disable();
949
950 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
951 if (current->active_mm == mm) {
952 if(current->mm)
953 __flush_tlb_one(va);
954 else
955 leave_mm(smp_processor_id());
956 }
957
958 if (cpu_mask)
959 voyager_flush_tlb_others(cpu_mask, mm, va);
960
961 preempt_enable();
962}
963EXPORT_SYMBOL(flush_tlb_page);
964
965/* enable the requested IRQs */
966static void
967smp_enable_irq_interrupt(void)
968{
969 __u8 irq;
970 __u8 cpu = get_cpu();
971
972 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
973 vic_irq_enable_mask[cpu]));
974
975 spin_lock(&vic_irq_lock);
976 for(irq = 0; irq < 16; irq++) {
977 if(vic_irq_enable_mask[cpu] & (1<<irq))
978 enable_local_vic_irq(irq);
979 }
980 vic_irq_enable_mask[cpu] = 0;
981 spin_unlock(&vic_irq_lock);
982
983 put_cpu_no_resched();
984}
985
986/*
987 * CPU halt call-back
988 */
989static void
990smp_stop_cpu_function(void *dummy)
991{
992 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
993 cpu_clear(smp_processor_id(), cpu_online_map);
994 local_irq_disable();
995 for(;;)
996 halt();
997}
998
999static DEFINE_SPINLOCK(call_lock);
1000
1001struct call_data_struct {
1002 void (*func) (void *info);
1003 void *info;
1004 volatile unsigned long started;
1005 volatile unsigned long finished;
1006 int wait;
1007};
1008
1009static struct call_data_struct * call_data;
1010
1011/* execute a thread on a new CPU. The function to be called must be
1012 * previously set up. This is used to schedule a function for
1013 * execution on all CPU's - set up the function then broadcast a
1014 * function_interrupt CPI to come here on each CPU */
1015static void
1016smp_call_function_interrupt(void)
1017{
1018 void (*func) (void *info) = call_data->func;
1019 void *info = call_data->info;
1020 /* must take copy of wait because call_data may be replaced
1021 * unless the function is waiting for us to finish */
1022 int wait = call_data->wait;
1023 __u8 cpu = smp_processor_id();
1024
1025 /*
1026 * Notify initiating CPU that I've grabbed the data and am
1027 * about to execute the function
1028 */
1029 mb();
1030 if(!test_and_clear_bit(cpu, &call_data->started)) {
1031 /* If the bit wasn't set, this could be a replay */
1032 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1033 return;
1034 }
1035 /*
1036 * At this point the info structure may be out of scope unless wait==1
1037 */
1038 irq_enter();
1039 (*func)(info);
1040 irq_exit();
1041 if (wait) {
1042 mb();
1043 clear_bit(cpu, &call_data->finished);
1044 }
1045}
1046
1047static int
1048voyager_smp_call_function_mask (cpumask_t cpumask,
1049 void (*func) (void *info), void *info,
1050 int wait)
1051{
1052 struct call_data_struct data;
1053 u32 mask = cpus_addr(cpumask)[0];
1054
1055 mask &= ~(1<<smp_processor_id());
1056
1057 if (!mask)
1058 return 0;
1059
1060 /* Can deadlock when called with interrupts disabled */
1061 WARN_ON(irqs_disabled());
1062
1063 data.func = func;
1064 data.info = info;
1065 data.started = mask;
1066 data.wait = wait;
1067 if (wait)
1068 data.finished = mask;
1069
1070 spin_lock(&call_lock);
1071 call_data = &data;
1072 wmb();
1073 /* Send a message to all other CPUs and wait for them to respond */
1074 send_CPI(mask, VIC_CALL_FUNCTION_CPI);
1075
1076 /* Wait for response */
1077 while (data.started)
1078 barrier();
1079
1080 if (wait)
1081 while (data.finished)
1082 barrier();
1083
1084 spin_unlock(&call_lock);
1085
1086 return 0;
1087}
1088
1089/* Sorry about the name. In an APIC based system, the APICs
1090 * themselves are programmed to send a timer interrupt. This is used
1091 * by linux to reschedule the processor. Voyager doesn't have this,
1092 * so we use the system clock to interrupt one processor, which in
1093 * turn, broadcasts a timer CPI to all the others --- we receive that
1094 * CPI here. We don't use this actually for counting so losing
1095 * ticks doesn't matter
1096 *
1097 * FIXME: For those CPU's which actually have a local APIC, we could
1098 * try to use it to trigger this interrupt instead of having to
1099 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1100 * no local APIC, so I can't do this
1101 *
1102 * This function is currently a placeholder and is unused in the code */
1103fastcall void
1104smp_apic_timer_interrupt(struct pt_regs *regs)
1105{
1106 struct pt_regs *old_regs = set_irq_regs(regs);
1107 wrapper_smp_local_timer_interrupt();
1108 set_irq_regs(old_regs);
1109}
1110
1111/* All of the QUAD interrupt GATES */
1112fastcall void
1113smp_qic_timer_interrupt(struct pt_regs *regs)
1114{
1115 struct pt_regs *old_regs = set_irq_regs(regs);
1116 ack_QIC_CPI(QIC_TIMER_CPI);
1117 wrapper_smp_local_timer_interrupt();
1118 set_irq_regs(old_regs);
1119}
1120
1121fastcall void
1122smp_qic_invalidate_interrupt(struct pt_regs *regs)
1123{
1124 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1125 smp_invalidate_interrupt();
1126}
1127
1128fastcall void
1129smp_qic_reschedule_interrupt(struct pt_regs *regs)
1130{
1131 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1132 smp_reschedule_interrupt();
1133}
1134
1135fastcall void
1136smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1137{
1138 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1139 smp_enable_irq_interrupt();
1140}
1141
1142fastcall void
1143smp_qic_call_function_interrupt(struct pt_regs *regs)
1144{
1145 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1146 smp_call_function_interrupt();
1147}
1148
1149fastcall void
1150smp_vic_cpi_interrupt(struct pt_regs *regs)
1151{
1152 struct pt_regs *old_regs = set_irq_regs(regs);
1153 __u8 cpu = smp_processor_id();
1154
1155 if(is_cpu_quad())
1156 ack_QIC_CPI(VIC_CPI_LEVEL0);
1157 else
1158 ack_VIC_CPI(VIC_CPI_LEVEL0);
1159
1160 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1161 wrapper_smp_local_timer_interrupt();
1162 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1163 smp_invalidate_interrupt();
1164 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1165 smp_reschedule_interrupt();
1166 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1167 smp_enable_irq_interrupt();
1168 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1169 smp_call_function_interrupt();
1170 set_irq_regs(old_regs);
1171}
1172
1173static void
1174do_flush_tlb_all(void* info)
1175{
1176 unsigned long cpu = smp_processor_id();
1177
1178 __flush_tlb_all();
1179 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1180 leave_mm(cpu);
1181}
1182
1183
1184/* flush the TLB of every active CPU in the system */
1185void
1186flush_tlb_all(void)
1187{
1188 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1189}
1190
1191/* used to set up the trampoline for other CPUs when the memory manager
1192 * is sorted out */
1193void __init
1194smp_alloc_memory(void)
1195{
1196 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1197 if(__pa(trampoline_base) >= 0x93000)
1198 BUG();
1199}
1200
1201/* send a reschedule CPI to one CPU by physical CPU number*/
1202static void
1203voyager_smp_send_reschedule(int cpu)
1204{
1205 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1206}
1207
1208
1209int
1210hard_smp_processor_id(void)
1211{
1212 __u8 i;
1213 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1214 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1215 return cpumask & 0x1F;
1216
1217 for(i = 0; i < 8; i++) {
1218 if(cpumask & (1<<i))
1219 return i;
1220 }
1221 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1222 return 0;
1223}
1224
1225int
1226safe_smp_processor_id(void)
1227{
1228 return hard_smp_processor_id();
1229}
1230
1231/* broadcast a halt to all other CPUs */
1232static void
1233voyager_smp_send_stop(void)
1234{
1235 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1236}
1237
1238/* this function is triggered in time.c when a clock tick fires
1239 * we need to re-broadcast the tick to all CPUs */
1240void
1241smp_vic_timer_interrupt(void)
1242{
1243 send_CPI_allbutself(VIC_TIMER_CPI);
1244 smp_local_timer_interrupt();
1245}
1246
1247/* local (per CPU) timer interrupt. It does both profiling and
1248 * process statistics/rescheduling.
1249 *
1250 * We do profiling in every local tick, statistics/rescheduling
1251 * happen only every 'profiling multiplier' ticks. The default
1252 * multiplier is 1 and it can be changed by writing the new multiplier
1253 * value into /proc/profile.
1254 */
1255void
1256smp_local_timer_interrupt(void)
1257{
1258 int cpu = smp_processor_id();
1259 long weight;
1260
1261 profile_tick(CPU_PROFILING);
1262 if (--per_cpu(prof_counter, cpu) <= 0) {
1263 /*
1264 * The multiplier may have changed since the last time we got
1265 * to this point as a result of the user writing to
1266 * /proc/profile. In this case we need to adjust the APIC
1267 * timer accordingly.
1268 *
1269 * Interrupts are already masked off at this point.
1270 */
1271 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1272 if (per_cpu(prof_counter, cpu) !=
1273 per_cpu(prof_old_multiplier, cpu)) {
1274 /* FIXME: need to update the vic timer tick here */
1275 per_cpu(prof_old_multiplier, cpu) =
1276 per_cpu(prof_counter, cpu);
1277 }
1278
1279 update_process_times(user_mode_vm(get_irq_regs()));
1280 }
1281
1282 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1283 /* only extended VIC processors participate in
1284 * interrupt distribution */
1285 return;
1286
1287 /*
1288 * We take the 'long' return path, and there every subsystem
1289 * grabs the apropriate locks (kernel lock/ irq lock).
1290 *
1291 * we might want to decouple profiling from the 'long path',
1292 * and do the profiling totally in assembly.
1293 *
1294 * Currently this isn't too much of an issue (performance wise),
1295 * we can take more than 100K local irqs per second on a 100 MHz P5.
1296 */
1297
1298 if((++vic_tick[cpu] & 0x7) != 0)
1299 return;
1300 /* get here every 16 ticks (about every 1/6 of a second) */
1301
1302 /* Change our priority to give someone else a chance at getting
1303 * the IRQ. The algorithm goes like this:
1304 *
1305 * In the VIC, the dynamically routed interrupt is always
1306 * handled by the lowest priority eligible (i.e. receiving
1307 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1308 * lowest processor number gets it.
1309 *
1310 * The priority of a CPU is controlled by a special per-CPU
1311 * VIC priority register which is 3 bits wide 0 being lowest
1312 * and 7 highest priority..
1313 *
1314 * Therefore we subtract the average number of interrupts from
1315 * the number we've fielded. If this number is negative, we
1316 * lower the activity count and if it is positive, we raise
1317 * it.
1318 *
1319 * I'm afraid this still leads to odd looking interrupt counts:
1320 * the totals are all roughly equal, but the individual ones
1321 * look rather skewed.
1322 *
1323 * FIXME: This algorithm is total crap when mixed with SMP
1324 * affinity code since we now try to even up the interrupt
1325 * counts when an affinity binding is keeping them on a
1326 * particular CPU*/
1327 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1328 - vic_intr_total) >> 4;
1329 weight += 4;
1330 if(weight > 7)
1331 weight = 7;
1332 if(weight < 0)
1333 weight = 0;
1334
1335 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1336
1337#ifdef VOYAGER_DEBUG
1338 if((vic_tick[cpu] & 0xFFF) == 0) {
1339 /* print this message roughly every 25 secs */
1340 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1341 cpu, vic_tick[cpu], weight);
1342 }
1343#endif
1344}
1345
1346/* setup the profiling timer */
1347int
1348setup_profiling_timer(unsigned int multiplier)
1349{
1350 int i;
1351
1352 if ( (!multiplier))
1353 return -EINVAL;
1354
1355 /*
1356 * Set the new multiplier for each CPU. CPUs don't start using the
1357 * new values until the next timer interrupt in which they do process
1358 * accounting.
1359 */
1360 for (i = 0; i < NR_CPUS; ++i)
1361 per_cpu(prof_multiplier, i) = multiplier;
1362
1363 return 0;
1364}
1365
1366/* This is a bit of a mess, but forced on us by the genirq changes
1367 * there's no genirq handler that really does what voyager wants
1368 * so hack it up with the simple IRQ handler */
1369static void fastcall
1370handle_vic_irq(unsigned int irq, struct irq_desc *desc)
1371{
1372 before_handle_vic_irq(irq);
1373 handle_simple_irq(irq, desc);
1374 after_handle_vic_irq(irq);
1375}
1376
1377
1378/* The CPIs are handled in the per cpu 8259s, so they must be
1379 * enabled to be received: FIX: enabling the CPIs in the early
1380 * boot sequence interferes with bug checking; enable them later
1381 * on in smp_init */
1382#define VIC_SET_GATE(cpi, vector) \
1383 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1384#define QIC_SET_GATE(cpi, vector) \
1385 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1386
1387void __init
1388smp_intr_init(void)
1389{
1390 int i;
1391
1392 /* initialize the per cpu irq mask to all disabled */
1393 for(i = 0; i < NR_CPUS; i++)
1394 vic_irq_mask[i] = 0xFFFF;
1395
1396 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1397
1398 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1399 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1400
1401 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1402 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1403 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1404 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1405 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1406
1407
1408 /* now put the VIC descriptor into the first 48 IRQs
1409 *
1410 * This is for later: first 16 correspond to PC IRQs; next 16
1411 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1412 for(i = 0; i < 48; i++)
1413 set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq);
1414}
1415
1416/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1417 * processor to receive CPI */
1418static void
1419send_CPI(__u32 cpuset, __u8 cpi)
1420{
1421 int cpu;
1422 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1423
1424 if(cpi < VIC_START_FAKE_CPI) {
1425 /* fake CPI are only used for booting, so send to the
1426 * extended quads as well---Quads must be VIC booted */
1427 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1428 return;
1429 }
1430 if(quad_cpuset)
1431 send_QIC_CPI(quad_cpuset, cpi);
1432 cpuset &= ~quad_cpuset;
1433 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1434 if(cpuset == 0)
1435 return;
1436 for_each_online_cpu(cpu) {
1437 if(cpuset & (1<<cpu))
1438 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1439 }
1440 if(cpuset)
1441 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1442}
1443
1444/* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1445 * set the cache line to shared by reading it.
1446 *
1447 * DON'T make this inline otherwise the cache line read will be
1448 * optimised away
1449 * */
1450static int
1451ack_QIC_CPI(__u8 cpi) {
1452 __u8 cpu = hard_smp_processor_id();
1453
1454 cpi &= 7;
1455
1456 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1457 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1458}
1459
1460static void
1461ack_special_QIC_CPI(__u8 cpi)
1462{
1463 switch(cpi) {
1464 case VIC_CMN_INT:
1465 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1466 break;
1467 case VIC_SYS_INT:
1468 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1469 break;
1470 }
1471 /* also clear at the VIC, just in case (nop for non-extended proc) */
1472 ack_VIC_CPI(cpi);
1473}
1474
1475/* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1476static void
1477ack_VIC_CPI(__u8 cpi)
1478{
1479#ifdef VOYAGER_DEBUG
1480 unsigned long flags;
1481 __u16 isr;
1482 __u8 cpu = smp_processor_id();
1483
1484 local_irq_save(flags);
1485 isr = vic_read_isr();
1486 if((isr & (1<<(cpi &7))) == 0) {
1487 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1488 }
1489#endif
1490 /* send specific EOI; the two system interrupts have
1491 * bit 4 set for a separate vector but behave as the
1492 * corresponding 3 bit intr */
1493 outb_p(0x60|(cpi & 7),0x20);
1494
1495#ifdef VOYAGER_DEBUG
1496 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1497 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1498 }
1499 local_irq_restore(flags);
1500#endif
1501}
1502
1503/* cribbed with thanks from irq.c */
1504#define __byte(x,y) (((unsigned char *)&(y))[x])
1505#define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1506#define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1507
1508static unsigned int
1509startup_vic_irq(unsigned int irq)
1510{
1511 unmask_vic_irq(irq);
1512
1513 return 0;
1514}
1515
1516/* The enable and disable routines. This is where we run into
1517 * conflicting architectural philosophy. Fundamentally, the voyager
1518 * architecture does not expect to have to disable interrupts globally
1519 * (the IRQ controllers belong to each CPU). The processor masquerade
1520 * which is used to start the system shouldn't be used in a running OS
1521 * since it will cause great confusion if two separate CPUs drive to
1522 * the same IRQ controller (I know, I've tried it).
1523 *
1524 * The solution is a variant on the NCR lazy SPL design:
1525 *
1526 * 1) To disable an interrupt, do nothing (other than set the
1527 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1528 *
1529 * 2) If the interrupt dares to come in, raise the local mask against
1530 * it (this will result in all the CPU masks being raised
1531 * eventually).
1532 *
1533 * 3) To enable the interrupt, lower the mask on the local CPU and
1534 * broadcast an Interrupt enable CPI which causes all other CPUs to
1535 * adjust their masks accordingly. */
1536
1537static void
1538unmask_vic_irq(unsigned int irq)
1539{
1540 /* linux doesn't to processor-irq affinity, so enable on
1541 * all CPUs we know about */
1542 int cpu = smp_processor_id(), real_cpu;
1543 __u16 mask = (1<<irq);
1544 __u32 processorList = 0;
1545 unsigned long flags;
1546
1547 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1548 irq, cpu, cpu_irq_affinity[cpu]));
1549 spin_lock_irqsave(&vic_irq_lock, flags);
1550 for_each_online_cpu(real_cpu) {
1551 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1552 continue;
1553 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1554 /* irq has no affinity for this CPU, ignore */
1555 continue;
1556 }
1557 if(real_cpu == cpu) {
1558 enable_local_vic_irq(irq);
1559 }
1560 else if(vic_irq_mask[real_cpu] & mask) {
1561 vic_irq_enable_mask[real_cpu] |= mask;
1562 processorList |= (1<<real_cpu);
1563 }
1564 }
1565 spin_unlock_irqrestore(&vic_irq_lock, flags);
1566 if(processorList)
1567 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1568}
1569
1570static void
1571mask_vic_irq(unsigned int irq)
1572{
1573 /* lazy disable, do nothing */
1574}
1575
1576static void
1577enable_local_vic_irq(unsigned int irq)
1578{
1579 __u8 cpu = smp_processor_id();
1580 __u16 mask = ~(1 << irq);
1581 __u16 old_mask = vic_irq_mask[cpu];
1582
1583 vic_irq_mask[cpu] &= mask;
1584 if(vic_irq_mask[cpu] == old_mask)
1585 return;
1586
1587 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1588 irq, cpu));
1589
1590 if (irq & 8) {
1591 outb_p(cached_A1(cpu),0xA1);
1592 (void)inb_p(0xA1);
1593 }
1594 else {
1595 outb_p(cached_21(cpu),0x21);
1596 (void)inb_p(0x21);
1597 }
1598}
1599
1600static void
1601disable_local_vic_irq(unsigned int irq)
1602{
1603 __u8 cpu = smp_processor_id();
1604 __u16 mask = (1 << irq);
1605 __u16 old_mask = vic_irq_mask[cpu];
1606
1607 if(irq == 7)
1608 return;
1609
1610 vic_irq_mask[cpu] |= mask;
1611 if(old_mask == vic_irq_mask[cpu])
1612 return;
1613
1614 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1615 irq, cpu));
1616
1617 if (irq & 8) {
1618 outb_p(cached_A1(cpu),0xA1);
1619 (void)inb_p(0xA1);
1620 }
1621 else {
1622 outb_p(cached_21(cpu),0x21);
1623 (void)inb_p(0x21);
1624 }
1625}
1626
1627/* The VIC is level triggered, so the ack can only be issued after the
1628 * interrupt completes. However, we do Voyager lazy interrupt
1629 * handling here: It is an extremely expensive operation to mask an
1630 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1631 * this interrupt actually comes in, then we mask and ack here to push
1632 * the interrupt off to another CPU */
1633static void
1634before_handle_vic_irq(unsigned int irq)
1635{
1636 irq_desc_t *desc = irq_desc + irq;
1637 __u8 cpu = smp_processor_id();
1638
1639 _raw_spin_lock(&vic_irq_lock);
1640 vic_intr_total++;
1641 vic_intr_count[cpu]++;
1642
1643 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1644 /* The irq is not in our affinity mask, push it off
1645 * onto another CPU */
1646 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1647 irq, cpu));
1648 disable_local_vic_irq(irq);
1649 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1650 * actually calling the interrupt routine */
1651 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1652 } else if(desc->status & IRQ_DISABLED) {
1653 /* Damn, the interrupt actually arrived, do the lazy
1654 * disable thing. The interrupt routine in irq.c will
1655 * not handle a IRQ_DISABLED interrupt, so nothing more
1656 * need be done here */
1657 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1658 irq, cpu));
1659 disable_local_vic_irq(irq);
1660 desc->status |= IRQ_REPLAY;
1661 } else {
1662 desc->status &= ~IRQ_REPLAY;
1663 }
1664
1665 _raw_spin_unlock(&vic_irq_lock);
1666}
1667
1668/* Finish the VIC interrupt: basically mask */
1669static void
1670after_handle_vic_irq(unsigned int irq)
1671{
1672 irq_desc_t *desc = irq_desc + irq;
1673
1674 _raw_spin_lock(&vic_irq_lock);
1675 {
1676 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1677#ifdef VOYAGER_DEBUG
1678 __u16 isr;
1679#endif
1680
1681 desc->status = status;
1682 if ((status & IRQ_DISABLED))
1683 disable_local_vic_irq(irq);
1684#ifdef VOYAGER_DEBUG
1685 /* DEBUG: before we ack, check what's in progress */
1686 isr = vic_read_isr();
1687 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1688 int i;
1689 __u8 cpu = smp_processor_id();
1690 __u8 real_cpu;
1691 int mask; /* Um... initialize me??? --RR */
1692
1693 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1694 cpu, irq);
1695 for_each_possible_cpu(real_cpu, mask) {
1696
1697 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1698 VIC_PROCESSOR_ID);
1699 isr = vic_read_isr();
1700 if(isr & (1<<irq)) {
1701 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1702 real_cpu, irq);
1703 ack_vic_irq(irq);
1704 }
1705 outb(cpu, VIC_PROCESSOR_ID);
1706 }
1707 }
1708#endif /* VOYAGER_DEBUG */
1709 /* as soon as we ack, the interrupt is eligible for
1710 * receipt by another CPU so everything must be in
1711 * order here */
1712 ack_vic_irq(irq);
1713 if(status & IRQ_REPLAY) {
1714 /* replay is set if we disable the interrupt
1715 * in the before_handle_vic_irq() routine, so
1716 * clear the in progress bit here to allow the
1717 * next CPU to handle this correctly */
1718 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1719 }
1720#ifdef VOYAGER_DEBUG
1721 isr = vic_read_isr();
1722 if((isr & (1<<irq)) != 0)
1723 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1724 irq, isr);
1725#endif /* VOYAGER_DEBUG */
1726 }
1727 _raw_spin_unlock(&vic_irq_lock);
1728
1729 /* All code after this point is out of the main path - the IRQ
1730 * may be intercepted by another CPU if reasserted */
1731}
1732
1733
1734/* Linux processor - interrupt affinity manipulations.
1735 *
1736 * For each processor, we maintain a 32 bit irq affinity mask.
1737 * Initially it is set to all 1's so every processor accepts every
1738 * interrupt. In this call, we change the processor's affinity mask:
1739 *
1740 * Change from enable to disable:
1741 *
1742 * If the interrupt ever comes in to the processor, we will disable it
1743 * and ack it to push it off to another CPU, so just accept the mask here.
1744 *
1745 * Change from disable to enable:
1746 *
1747 * change the mask and then do an interrupt enable CPI to re-enable on
1748 * the selected processors */
1749
1750void
1751set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1752{
1753 /* Only extended processors handle interrupts */
1754 unsigned long real_mask;
1755 unsigned long irq_mask = 1 << irq;
1756 int cpu;
1757
1758 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1759
1760 if(cpus_addr(mask)[0] == 0)
1761 /* can't have no cpu's to accept the interrupt -- extremely
1762 * bad things will happen */
1763 return;
1764
1765 if(irq == 0)
1766 /* can't change the affinity of the timer IRQ. This
1767 * is due to the constraint in the voyager
1768 * architecture that the CPI also comes in on and IRQ
1769 * line and we have chosen IRQ0 for this. If you
1770 * raise the mask on this interrupt, the processor
1771 * will no-longer be able to accept VIC CPIs */
1772 return;
1773
1774 if(irq >= 32)
1775 /* You can only have 32 interrupts in a voyager system
1776 * (and 32 only if you have a secondary microchannel
1777 * bus) */
1778 return;
1779
1780 for_each_online_cpu(cpu) {
1781 unsigned long cpu_mask = 1 << cpu;
1782
1783 if(cpu_mask & real_mask) {
1784 /* enable the interrupt for this cpu */
1785 cpu_irq_affinity[cpu] |= irq_mask;
1786 } else {
1787 /* disable the interrupt for this cpu */
1788 cpu_irq_affinity[cpu] &= ~irq_mask;
1789 }
1790 }
1791 /* this is magic, we now have the correct affinity maps, so
1792 * enable the interrupt. This will send an enable CPI to
1793 * those cpu's who need to enable it in their local masks,
1794 * causing them to correct for the new affinity . If the
1795 * interrupt is currently globally disabled, it will simply be
1796 * disabled again as it comes in (voyager lazy disable). If
1797 * the affinity map is tightened to disable the interrupt on a
1798 * cpu, it will be pushed off when it comes in */
1799 unmask_vic_irq(irq);
1800}
1801
1802static void
1803ack_vic_irq(unsigned int irq)
1804{
1805 if (irq & 8) {
1806 outb(0x62,0x20); /* Specific EOI to cascade */
1807 outb(0x60|(irq & 7),0xA0);
1808 } else {
1809 outb(0x60 | (irq & 7),0x20);
1810 }
1811}
1812
1813/* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1814 * but are not vectored by it. This means that the 8259 mask must be
1815 * lowered to receive them */
1816static __init void
1817vic_enable_cpi(void)
1818{
1819 __u8 cpu = smp_processor_id();
1820
1821 /* just take a copy of the current mask (nop for boot cpu) */
1822 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1823
1824 enable_local_vic_irq(VIC_CPI_LEVEL0);
1825 enable_local_vic_irq(VIC_CPI_LEVEL1);
1826 /* for sys int and cmn int */
1827 enable_local_vic_irq(7);
1828
1829 if(is_cpu_quad()) {
1830 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1831 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1832 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1833 cpu, QIC_CPI_ENABLE));
1834 }
1835
1836 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1837 cpu, vic_irq_mask[cpu]));
1838}
1839
1840void
1841voyager_smp_dump()
1842{
1843 int old_cpu = smp_processor_id(), cpu;
1844
1845 /* dump the interrupt masks of each processor */
1846 for_each_online_cpu(cpu) {
1847 __u16 imr, isr, irr;
1848 unsigned long flags;
1849
1850 local_irq_save(flags);
1851 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1852 imr = (inb(0xa1) << 8) | inb(0x21);
1853 outb(0x0a, 0xa0);
1854 irr = inb(0xa0) << 8;
1855 outb(0x0a, 0x20);
1856 irr |= inb(0x20);
1857 outb(0x0b, 0xa0);
1858 isr = inb(0xa0) << 8;
1859 outb(0x0b, 0x20);
1860 isr |= inb(0x20);
1861 outb(old_cpu, VIC_PROCESSOR_ID);
1862 local_irq_restore(flags);
1863 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1864 cpu, vic_irq_mask[cpu], imr, irr, isr);
1865#if 0
1866 /* These lines are put in to try to unstick an un ack'd irq */
1867 if(isr != 0) {
1868 int irq;
1869 for(irq=0; irq<16; irq++) {
1870 if(isr & (1<<irq)) {
1871 printk("\tCPU%d: ack irq %d\n",
1872 cpu, irq);
1873 local_irq_save(flags);
1874 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1875 VIC_PROCESSOR_ID);
1876 ack_vic_irq(irq);
1877 outb(old_cpu, VIC_PROCESSOR_ID);
1878 local_irq_restore(flags);
1879 }
1880 }
1881 }
1882#endif
1883 }
1884}
1885
1886void
1887smp_voyager_power_off(void *dummy)
1888{
1889 if(smp_processor_id() == boot_cpu_id)
1890 voyager_power_off();
1891 else
1892 smp_stop_cpu_function(NULL);
1893}
1894
1895static void __init
1896voyager_smp_prepare_cpus(unsigned int max_cpus)
1897{
1898 /* FIXME: ignore max_cpus for now */
1899 smp_boot_cpus();
1900}
1901
1902static void __devinit voyager_smp_prepare_boot_cpu(void)
1903{
1904 init_gdt(smp_processor_id());
1905 switch_to_new_gdt();
1906
1907 cpu_set(smp_processor_id(), cpu_online_map);
1908 cpu_set(smp_processor_id(), cpu_callout_map);
1909 cpu_set(smp_processor_id(), cpu_possible_map);
1910 cpu_set(smp_processor_id(), cpu_present_map);
1911}
1912
1913static int __devinit
1914voyager_cpu_up(unsigned int cpu)
1915{
1916 /* This only works at boot for x86. See "rewrite" above. */
1917 if (cpu_isset(cpu, smp_commenced_mask))
1918 return -ENOSYS;
1919
1920 /* In case one didn't come up */
1921 if (!cpu_isset(cpu, cpu_callin_map))
1922 return -EIO;
1923 /* Unleash the CPU! */
1924 cpu_set(cpu, smp_commenced_mask);
1925 while (!cpu_isset(cpu, cpu_online_map))
1926 mb();
1927 return 0;
1928}
1929
1930static void __init
1931voyager_smp_cpus_done(unsigned int max_cpus)
1932{
1933 zap_low_mappings();
1934}
1935
1936void __init
1937smp_setup_processor_id(void)
1938{
1939 current_thread_info()->cpu = hard_smp_processor_id();
1940 x86_write_percpu(cpu_number, hard_smp_processor_id());
1941}
1942
1943struct smp_ops smp_ops = {
1944 .smp_prepare_boot_cpu = voyager_smp_prepare_boot_cpu,
1945 .smp_prepare_cpus = voyager_smp_prepare_cpus,
1946 .cpu_up = voyager_cpu_up,
1947 .smp_cpus_done = voyager_smp_cpus_done,
1948
1949 .smp_send_stop = voyager_smp_send_stop,
1950 .smp_send_reschedule = voyager_smp_send_reschedule,
1951 .smp_call_function_mask = voyager_smp_call_function_mask,
1952};
diff --git a/arch/x86/mach-voyager/voyager_thread.c b/arch/x86/mach-voyager/voyager_thread.c
new file mode 100644
index 000000000000..f9d595338159
--- /dev/null
+++ b/arch/x86/mach-voyager/voyager_thread.c
@@ -0,0 +1,134 @@
1/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/kernel/voyager_thread.c
8 *
9 * This module provides the machine status monitor thread for the
10 * voyager architecture. This allows us to monitor the machine
11 * environment (temp, voltage, fan function) and the front panel and
12 * internal UPS. If a fault is detected, this thread takes corrective
13 * action (usually just informing init)
14 * */
15
16#include <linux/module.h>
17#include <linux/mm.h>
18#include <linux/kernel_stat.h>
19#include <linux/delay.h>
20#include <linux/mc146818rtc.h>
21#include <linux/init.h>
22#include <linux/bootmem.h>
23#include <linux/kmod.h>
24#include <linux/completion.h>
25#include <linux/sched.h>
26#include <linux/kthread.h>
27#include <asm/desc.h>
28#include <asm/voyager.h>
29#include <asm/vic.h>
30#include <asm/mtrr.h>
31#include <asm/msr.h>
32
33
34struct task_struct *voyager_thread;
35static __u8 set_timeout;
36
37static int
38execute(const char *string)
39{
40 int ret;
41
42 char *envp[] = {
43 "HOME=/",
44 "TERM=linux",
45 "PATH=/sbin:/usr/sbin:/bin:/usr/bin",
46 NULL,
47 };
48 char *argv[] = {
49 "/bin/bash",
50 "-c",
51 (char *)string,
52 NULL,
53 };
54
55 if ((ret = call_usermodehelper(argv[0], argv, envp, UMH_WAIT_PROC)) != 0) {
56 printk(KERN_ERR "Voyager failed to run \"%s\": %i\n",
57 string, ret);
58 }
59 return ret;
60}
61
62static void
63check_from_kernel(void)
64{
65 if(voyager_status.switch_off) {
66
67 /* FIXME: This should be configureable via proc */
68 execute("umask 600; echo 0 > /etc/initrunlvl; kill -HUP 1");
69 } else if(voyager_status.power_fail) {
70 VDEBUG(("Voyager daemon detected AC power failure\n"));
71
72 /* FIXME: This should be configureable via proc */
73 execute("umask 600; echo F > /etc/powerstatus; kill -PWR 1");
74 set_timeout = 1;
75 }
76}
77
78static void
79check_continuing_condition(void)
80{
81 if(voyager_status.power_fail) {
82 __u8 data;
83 voyager_cat_psi(VOYAGER_PSI_SUBREAD,
84 VOYAGER_PSI_AC_FAIL_REG, &data);
85 if((data & 0x1f) == 0) {
86 /* all power restored */
87 printk(KERN_NOTICE "VOYAGER AC power restored, cancelling shutdown\n");
88 /* FIXME: should be user configureable */
89 execute("umask 600; echo O > /etc/powerstatus; kill -PWR 1");
90 set_timeout = 0;
91 }
92 }
93}
94
95static int
96thread(void *unused)
97{
98 printk(KERN_NOTICE "Voyager starting monitor thread\n");
99
100 for (;;) {
101 set_current_state(TASK_INTERRUPTIBLE);
102 schedule_timeout(set_timeout ? HZ : MAX_SCHEDULE_TIMEOUT);
103
104 VDEBUG(("Voyager Daemon awoken\n"));
105 if(voyager_status.request_from_kernel == 0) {
106 /* probably awoken from timeout */
107 check_continuing_condition();
108 } else {
109 check_from_kernel();
110 voyager_status.request_from_kernel = 0;
111 }
112 }
113}
114
115static int __init
116voyager_thread_start(void)
117{
118 voyager_thread = kthread_run(thread, NULL, "kvoyagerd");
119 if (IS_ERR(voyager_thread)) {
120 printk(KERN_ERR "Voyager: Failed to create system monitor thread.\n");
121 return PTR_ERR(voyager_thread);
122 }
123 return 0;
124}
125
126
127static void __exit
128voyager_thread_stop(void)
129{
130 kthread_stop(voyager_thread);
131}
132
133module_init(voyager_thread_start);
134module_exit(voyager_thread_stop);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 00:22:12 -0500