x86: clean up esr_disable() methods

Impact: cleanup

Most subarchitectures want to disable the APIC ESR (Error Status Register),
because they generally have hardware hacks that wrap standard CPUs into
a bigger system and hence the APIC bus is quite non-standard and weirdnesses
(lockups) have been seen with ESR reporting.

Remove the esr_disable macros and put the desired flag into each
subarchitecture's genapic template directly.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/x86/mach-generic/default.c b/arch/x86/mach-generic/default.c
index a483e22273e5..c30141a9aca0 100644
--- a/arch/x86/mach-generic/default.c
+++ b/arch/x86/mach-generic/default.c
@@ -36,7 +36,7 @@ struct genapic apic_default = {
         .irq_dest_mode                  = 1,
 
         .target_cpus                    = default_target_cpus,
-        .ESR_DISABLE                    = esr_disable,
+        .ESR_DISABLE                    = 0,
         .apic_destination_logical       = APIC_DEST_LOGICAL,
         .check_apicid_used              = check_apicid_used,
         .check_apicid_present           = check_apicid_present,