x86: clean up esr_disable() methods

Impact: cleanup

Most subarchitectures want to disable the APIC ESR (Error Status Register),
because they generally have hardware hacks that wrap standard CPUs into
a bigger system and hence the APIC bus is quite non-standard and weirdnesses
(lockups) have been seen with ESR reporting.

Remove the esr_disable macros and put the desired flag into each
subarchitecture's genapic template directly.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/x86/mach-generic/bigsmp.c b/arch/x86/mach-generic/bigsmp.c
index d3cead2d2fc8..f0bb72674f73 100644
--- a/arch/x86/mach-generic/bigsmp.c
+++ b/arch/x86/mach-generic/bigsmp.c
@@ -69,7 +69,7 @@ struct genapic apic_bigsmp = {
         .irq_dest_mode                  = 0,
 
         .target_cpus                    = bigsmp_target_cpus,
-        .ESR_DISABLE                    = esr_disable,
+        .ESR_DISABLE                    = 1,
         .apic_destination_logical       = APIC_DEST_LOGICAL,
         .check_apicid_used              = check_apicid_used,
         .check_apicid_present           = check_apicid_present,