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authorAndre Przywara <andre.przywara@amd.com>2009-07-02 09:04:14 -0400
committerAvi Kivity <avi@redhat.com>2009-09-10 01:33:10 -0400
commitf7c6d140032ae7e80df36d350c6edc41f92b2f94 (patch)
tree4d69b6bc63e25b2e6599575c7377af71f82ea58d /arch/x86/kvm/x86.c
parentf691fe1da7e2715137d21ae5a80bec64db4625db (diff)
KVM: fix MMIO_CONF_BASE MSR access
Some Windows versions check whether the BIOS has setup MMI/O for config space accesses on AMD Fam10h CPUs, we say "no" by returning 0 on reads and only allow disabling of MMI/O CfgSpace setup by igoring "0" writes. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'arch/x86/kvm/x86.c')
-rw-r--r--arch/x86/kvm/x86.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 0e74d98641a0..95fa45c0f16e 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -844,6 +844,13 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
844 return 1; 844 return 1;
845 } 845 }
846 break; 846 break;
847 case MSR_FAM10H_MMIO_CONF_BASE:
848 if (data != 0) {
849 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
850 "0x%llx\n", data);
851 return 1;
852 }
853 break;
847 case MSR_AMD64_NB_CFG: 854 case MSR_AMD64_NB_CFG:
848 break; 855 break;
849 case MSR_IA32_DEBUGCTLMSR: 856 case MSR_IA32_DEBUGCTLMSR:
@@ -1055,6 +1062,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1055 case MSR_K7_EVNTSEL0: 1062 case MSR_K7_EVNTSEL0:
1056 case MSR_K8_INT_PENDING_MSG: 1063 case MSR_K8_INT_PENDING_MSG:
1057 case MSR_AMD64_NB_CFG: 1064 case MSR_AMD64_NB_CFG:
1065 case MSR_FAM10H_MMIO_CONF_BASE:
1058 data = 0; 1066 data = 0;
1059 break; 1067 break;
1060 case MSR_MTRRcap: 1068 case MSR_MTRRcap: