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authorNadav Amit <namit@cs.technion.ac.il>2015-04-01 20:10:36 -0400
committerPaolo Bonzini <pbonzini@redhat.com>2015-04-08 04:47:02 -0400
commit58d269d8cccc53643f1a0900cfc0940e85ec9691 (patch)
treed8154df29de173aa1efa6192077854b4084fccb5 /arch/x86/kvm/vmx.c
parent3b5a5ffa928a3f875b0d5dd284eeb7c322e1688a (diff)
KVM: x86: BSP in MSR_IA32_APICBASE is writable
After reset, the CPU can change the BSP, which will be used upon INIT. Reset should return the BSP which QEMU asked for, and therefore handled accordingly. To quote: "If the MP protocol has completed and a BSP is chosen, subsequent INITs (either to a specific processor or system wide) do not cause the MP protocol to be repeated." [Intel SDM 8.4.2: MP Initialization Protocol Requirements and Restrictions] Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Message-Id: <1427933438-12782-3-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/vmx.c')
-rw-r--r--arch/x86/kvm/vmx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ddce07e8bef8..8c14d6a455b0 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -4706,7 +4706,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4706 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4706 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4707 kvm_set_cr8(&vmx->vcpu, 0); 4707 kvm_set_cr8(&vmx->vcpu, 0);
4708 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; 4708 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4709 if (kvm_vcpu_is_bsp(&vmx->vcpu)) 4709 if (kvm_vcpu_is_reset_bsp(&vmx->vcpu))
4710 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4710 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4711 apic_base_msr.host_initiated = true; 4711 apic_base_msr.host_initiated = true;
4712 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr); 4712 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);