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authorGleb Natapov <gleb@redhat.com>2013-01-21 08:36:41 -0500
committerMarcelo Tosatti <mtosatti@redhat.com>2013-01-23 21:40:25 -0500
commit1f3141e80b149e7215313dff29e9a0c47811b1d1 (patch)
tree1bad6cb5c463b08b3bc31f40505f873c83342613 /arch/x86/kvm/vmx.c
parent158de57f905ed97ea0f993feac1c40a40f5c7a04 (diff)
KVM: VMX: remove special CPL cache access during transition to real mode.
Since vmx_get_cpl() always returns 0 when VCPU is in real mode it is no longer needed. Also reset CPL cache to zero during transaction to protected mode since transaction may happen while CS.selectors & 3 != 0, but in reality CPL is 0. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'arch/x86/kvm/vmx.c')
-rw-r--r--arch/x86/kvm/vmx.c12
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index dd2a85c1c6f0..9d2ec88eeed2 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2817,6 +2817,10 @@ static void enter_pmode(struct kvm_vcpu *vcpu)
2817 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2817 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2818 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2818 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2819 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2819 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2820
2821 /* CPL is always 0 when CPU enters protected mode */
2822 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2823 vmx->cpl = 0;
2820} 2824}
2821 2825
2822static gva_t rmode_tss_base(struct kvm *kvm) 2826static gva_t rmode_tss_base(struct kvm *kvm)
@@ -3229,14 +3233,6 @@ static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3229 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */ 3233 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3230 return 3; 3234 return 3;
3231 3235
3232 /*
3233 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3234 * fail; use the cache instead.
3235 */
3236 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3237 return vmx->cpl;
3238 }
3239
3240 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) { 3236 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3241 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); 3237 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3242 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3; 3238 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;