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authorYan, Zheng <zheng.z.yan@intel.com>2012-07-05 02:32:17 -0400
committerIngo Molnar <mingo@kernel.org>2012-07-26 06:23:11 -0400
commit254298c726b93bb8ed92774b4a209b479851fa6d (patch)
tree59aa1bfc68223b774856bff9b46d2f64aaca0c86 /arch/x86/kernel
parent4f3f713fc78d966d81ad87d2f3587369f9b34ae6 (diff)
perf/x86: Add Intel Nehalem-EX uncore support
The uncore subsystem in Nehalem-EX consists of 7 components (U-Box, C-Box, B-Box, S-Box, R-Box, M-Box and W-Box). This patch is large because the way to program these boxes is diverse. Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/4FF534F1.3030307@intel.com [ Improved the code. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.c1278
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.h203
2 files changed, 1352 insertions, 129 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index a5de59f1a3ff..d9981701bdcf 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -38,6 +38,77 @@ DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
38DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23"); 38DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
39DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31"); 39DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31");
40 40
41static u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
42{
43 u64 count;
44
45 rdmsrl(event->hw.event_base, count);
46
47 return count;
48}
49
50/*
51 * generic get constraint function for shared match/mask registers.
52 */
53static struct event_constraint *
54uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
55{
56 struct intel_uncore_extra_reg *er;
57 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
58 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
59 unsigned long flags;
60 bool ok = false;
61
62 /*
63 * reg->alloc can be set due to existing state, so for fake box we
64 * need to ignore this, otherwise we might fail to allocate proper
65 * fake state for this extra reg constraint.
66 */
67 if (reg1->idx == EXTRA_REG_NONE ||
68 (!uncore_box_is_fake(box) && reg1->alloc))
69 return NULL;
70
71 er = &box->shared_regs[reg1->idx];
72 raw_spin_lock_irqsave(&er->lock, flags);
73 if (!atomic_read(&er->ref) ||
74 (er->config1 == reg1->config && er->config2 == reg2->config)) {
75 atomic_inc(&er->ref);
76 er->config1 = reg1->config;
77 er->config2 = reg2->config;
78 ok = true;
79 }
80 raw_spin_unlock_irqrestore(&er->lock, flags);
81
82 if (ok) {
83 if (!uncore_box_is_fake(box))
84 reg1->alloc = 1;
85 return NULL;
86 }
87
88 return &constraint_empty;
89}
90
91static void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
92{
93 struct intel_uncore_extra_reg *er;
94 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
95
96 /*
97 * Only put constraint if extra reg was actually allocated. Also
98 * takes care of event which do not use an extra shared reg.
99 *
100 * Also, if this is a fake box we shouldn't touch any event state
101 * (reg->alloc) and we don't care about leaving inconsistent box
102 * state either since it will be thrown out.
103 */
104 if (uncore_box_is_fake(box) || !reg1->alloc)
105 return;
106
107 er = &box->shared_regs[reg1->idx];
108 atomic_dec(&er->ref);
109 reg1->alloc = 0;
110}
111
41/* Sandy Bridge-EP uncore support */ 112/* Sandy Bridge-EP uncore support */
42static struct intel_uncore_type snbep_uncore_cbox; 113static struct intel_uncore_type snbep_uncore_cbox;
43static struct intel_uncore_type snbep_uncore_pcu; 114static struct intel_uncore_type snbep_uncore_pcu;
@@ -64,18 +135,15 @@ static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
64 pci_write_config_dword(pdev, box_ctl, config); 135 pci_write_config_dword(pdev, box_ctl, config);
65} 136}
66 137
67static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, 138static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
68 struct perf_event *event)
69{ 139{
70 struct pci_dev *pdev = box->pci_dev; 140 struct pci_dev *pdev = box->pci_dev;
71 struct hw_perf_event *hwc = &event->hw; 141 struct hw_perf_event *hwc = &event->hw;
72 142
73 pci_write_config_dword(pdev, hwc->config_base, hwc->config | 143 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
74 SNBEP_PMON_CTL_EN);
75} 144}
76 145
77static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, 146static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event)
78 struct perf_event *event)
79{ 147{
80 struct pci_dev *pdev = box->pci_dev; 148 struct pci_dev *pdev = box->pci_dev;
81 struct hw_perf_event *hwc = &event->hw; 149 struct hw_perf_event *hwc = &event->hw;
@@ -83,8 +151,7 @@ static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box,
83 pci_write_config_dword(pdev, hwc->config_base, hwc->config); 151 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
84} 152}
85 153
86static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, 154static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event)
87 struct perf_event *event)
88{ 155{
89 struct pci_dev *pdev = box->pci_dev; 156 struct pci_dev *pdev = box->pci_dev;
90 struct hw_perf_event *hwc = &event->hw; 157 struct hw_perf_event *hwc = &event->hw;
@@ -92,14 +159,15 @@ static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box,
92 159
93 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); 160 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
94 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); 161 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
162
95 return count; 163 return count;
96} 164}
97 165
98static void snbep_uncore_pci_init_box(struct intel_uncore_box *box) 166static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
99{ 167{
100 struct pci_dev *pdev = box->pci_dev; 168 struct pci_dev *pdev = box->pci_dev;
101 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, 169
102 SNBEP_PMON_BOX_CTL_INT); 170 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, SNBEP_PMON_BOX_CTL_INT);
103} 171}
104 172
105static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box) 173static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
@@ -112,7 +180,6 @@ static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
112 rdmsrl(msr, config); 180 rdmsrl(msr, config);
113 config |= SNBEP_PMON_BOX_CTL_FRZ; 181 config |= SNBEP_PMON_BOX_CTL_FRZ;
114 wrmsrl(msr, config); 182 wrmsrl(msr, config);
115 return;
116 } 183 }
117} 184}
118 185
@@ -126,12 +193,10 @@ static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
126 rdmsrl(msr, config); 193 rdmsrl(msr, config);
127 config &= ~SNBEP_PMON_BOX_CTL_FRZ; 194 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
128 wrmsrl(msr, config); 195 wrmsrl(msr, config);
129 return;
130 } 196 }
131} 197}
132 198
133static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, 199static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
134 struct perf_event *event)
135{ 200{
136 struct hw_perf_event *hwc = &event->hw; 201 struct hw_perf_event *hwc = &event->hw;
137 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 202 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
@@ -150,68 +215,15 @@ static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
150 wrmsrl(hwc->config_base, hwc->config); 215 wrmsrl(hwc->config_base, hwc->config);
151} 216}
152 217
153static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box,
154 struct perf_event *event)
155{
156 struct hw_perf_event *hwc = &event->hw;
157 u64 count;
158
159 rdmsrl(hwc->event_base, count);
160 return count;
161}
162
163static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) 218static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
164{ 219{
165 unsigned msr = uncore_msr_box_ctl(box); 220 unsigned msr = uncore_msr_box_ctl(box);
221
166 if (msr) 222 if (msr)
167 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); 223 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
168} 224}
169 225
170static struct event_constraint * 226static int snbep_uncore_hw_config(struct intel_uncore_box *box, struct perf_event *event)
171snbep_uncore_get_constraint(struct intel_uncore_box *box,
172 struct perf_event *event)
173{
174 struct intel_uncore_extra_reg *er;
175 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
176 unsigned long flags;
177 bool ok = false;
178
179 if (reg1->idx == EXTRA_REG_NONE || (box->phys_id >= 0 && reg1->alloc))
180 return NULL;
181
182 er = &box->shared_regs[reg1->idx];
183 raw_spin_lock_irqsave(&er->lock, flags);
184 if (!atomic_read(&er->ref) || er->config1 == reg1->config) {
185 atomic_inc(&er->ref);
186 er->config1 = reg1->config;
187 ok = true;
188 }
189 raw_spin_unlock_irqrestore(&er->lock, flags);
190
191 if (ok) {
192 if (box->phys_id >= 0)
193 reg1->alloc = 1;
194 return NULL;
195 }
196 return &constraint_empty;
197}
198
199static void snbep_uncore_put_constraint(struct intel_uncore_box *box,
200 struct perf_event *event)
201{
202 struct intel_uncore_extra_reg *er;
203 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
204
205 if (box->phys_id < 0 || !reg1->alloc)
206 return;
207
208 er = &box->shared_regs[reg1->idx];
209 atomic_dec(&er->ref);
210 reg1->alloc = 0;
211}
212
213static int snbep_uncore_hw_config(struct intel_uncore_box *box,
214 struct perf_event *event)
215{ 227{
216 struct hw_perf_event *hwc = &event->hw; 228 struct hw_perf_event *hwc = &event->hw;
217 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 229 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
@@ -221,14 +233,16 @@ static int snbep_uncore_hw_config(struct intel_uncore_box *box,
221 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 233 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
222 reg1->config = event->attr.config1 & 234 reg1->config = event->attr.config1 &
223 SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK; 235 SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK;
224 } else if (box->pmu->type == &snbep_uncore_pcu) {
225 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
226 reg1->config = event->attr.config1 &
227 SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK;
228 } else { 236 } else {
229 return 0; 237 if (box->pmu->type == &snbep_uncore_pcu) {
238 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
239 reg1->config = event->attr.config1 & SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK;
240 } else {
241 return 0;
242 }
230 } 243 }
231 reg1->idx = 0; 244 reg1->idx = 0;
245
232 return 0; 246 return 0;
233} 247}
234 248
@@ -320,9 +334,9 @@ static struct intel_uncore_ops snbep_uncore_msr_ops = {
320 .enable_box = snbep_uncore_msr_enable_box, 334 .enable_box = snbep_uncore_msr_enable_box,
321 .disable_event = snbep_uncore_msr_disable_event, 335 .disable_event = snbep_uncore_msr_disable_event,
322 .enable_event = snbep_uncore_msr_enable_event, 336 .enable_event = snbep_uncore_msr_enable_event,
323 .read_counter = snbep_uncore_msr_read_counter, 337 .read_counter = uncore_msr_read_counter,
324 .get_constraint = snbep_uncore_get_constraint, 338 .get_constraint = uncore_get_constraint,
325 .put_constraint = snbep_uncore_put_constraint, 339 .put_constraint = uncore_put_constraint,
326 .hw_config = snbep_uncore_hw_config, 340 .hw_config = snbep_uncore_hw_config,
327}; 341};
328 342
@@ -603,10 +617,8 @@ static void snbep_pci2phy_map_init(void)
603} 617}
604/* end of Sandy Bridge-EP uncore support */ 618/* end of Sandy Bridge-EP uncore support */
605 619
606
607/* Sandy Bridge uncore support */ 620/* Sandy Bridge uncore support */
608static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, 621static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
609 struct perf_event *event)
610{ 622{
611 struct hw_perf_event *hwc = &event->hw; 623 struct hw_perf_event *hwc = &event->hw;
612 624
@@ -616,20 +628,11 @@ static void snb_uncore_msr_enable_event(struct intel_uncore_box *box,
616 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); 628 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
617} 629}
618 630
619static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, 631static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
620 struct perf_event *event)
621{ 632{
622 wrmsrl(event->hw.config_base, 0); 633 wrmsrl(event->hw.config_base, 0);
623} 634}
624 635
625static u64 snb_uncore_msr_read_counter(struct intel_uncore_box *box,
626 struct perf_event *event)
627{
628 u64 count;
629 rdmsrl(event->hw.event_base, count);
630 return count;
631}
632
633static void snb_uncore_msr_init_box(struct intel_uncore_box *box) 636static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
634{ 637{
635 if (box->pmu->pmu_idx == 0) { 638 if (box->pmu->pmu_idx == 0) {
@@ -648,15 +651,15 @@ static struct attribute *snb_uncore_formats_attr[] = {
648}; 651};
649 652
650static struct attribute_group snb_uncore_format_group = { 653static struct attribute_group snb_uncore_format_group = {
651 .name = "format", 654 .name = "format",
652 .attrs = snb_uncore_formats_attr, 655 .attrs = snb_uncore_formats_attr,
653}; 656};
654 657
655static struct intel_uncore_ops snb_uncore_msr_ops = { 658static struct intel_uncore_ops snb_uncore_msr_ops = {
656 .init_box = snb_uncore_msr_init_box, 659 .init_box = snb_uncore_msr_init_box,
657 .disable_event = snb_uncore_msr_disable_event, 660 .disable_event = snb_uncore_msr_disable_event,
658 .enable_event = snb_uncore_msr_enable_event, 661 .enable_event = snb_uncore_msr_enable_event,
659 .read_counter = snb_uncore_msr_read_counter, 662 .read_counter = uncore_msr_read_counter,
660}; 663};
661 664
662static struct event_constraint snb_uncore_cbox_constraints[] = { 665static struct event_constraint snb_uncore_cbox_constraints[] = {
@@ -697,12 +700,10 @@ static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
697 700
698static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box) 701static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
699{ 702{
700 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 703 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
701 NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
702} 704}
703 705
704static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, 706static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
705 struct perf_event *event)
706{ 707{
707 struct hw_perf_event *hwc = &event->hw; 708 struct hw_perf_event *hwc = &event->hw;
708 709
@@ -744,7 +745,7 @@ static struct intel_uncore_ops nhm_uncore_msr_ops = {
744 .enable_box = nhm_uncore_msr_enable_box, 745 .enable_box = nhm_uncore_msr_enable_box,
745 .disable_event = snb_uncore_msr_disable_event, 746 .disable_event = snb_uncore_msr_disable_event,
746 .enable_event = nhm_uncore_msr_enable_event, 747 .enable_event = nhm_uncore_msr_enable_event,
747 .read_counter = snb_uncore_msr_read_counter, 748 .read_counter = uncore_msr_read_counter,
748}; 749};
749 750
750static struct intel_uncore_type nhm_uncore = { 751static struct intel_uncore_type nhm_uncore = {
@@ -769,8 +770,1041 @@ static struct intel_uncore_type *nhm_msr_uncores[] = {
769}; 770};
770/* end of Nehalem uncore support */ 771/* end of Nehalem uncore support */
771 772
772static void uncore_assign_hw_event(struct intel_uncore_box *box, 773/* Nehalem-EX uncore support */
773 struct perf_event *event, int idx) 774#define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
775 ((1ULL << (n)) - 1)))
776
777DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
778DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
779DEFINE_UNCORE_FORMAT_ATTR(mm_cfg, mm_cfg, "config:63");
780DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
781DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
782
783static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box)
784{
785 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL);
786}
787
788static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
789{
790 unsigned msr = uncore_msr_box_ctl(box);
791 u64 config;
792
793 if (msr) {
794 rdmsrl(msr, config);
795 config &= ~((1ULL << uncore_num_counters(box)) - 1);
796 /* WBox has a fixed counter */
797 if (uncore_msr_fixed_ctl(box))
798 config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN;
799 wrmsrl(msr, config);
800 }
801}
802
803static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
804{
805 unsigned msr = uncore_msr_box_ctl(box);
806 u64 config;
807
808 if (msr) {
809 rdmsrl(msr, config);
810 config |= (1ULL << uncore_num_counters(box)) - 1;
811 /* WBox has a fixed counter */
812 if (uncore_msr_fixed_ctl(box))
813 config |= NHMEX_W_PMON_GLOBAL_FIXED_EN;
814 wrmsrl(msr, config);
815 }
816}
817
818static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
819{
820 wrmsrl(event->hw.config_base, 0);
821}
822
823static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
824{
825 struct hw_perf_event *hwc = &event->hw;
826
827 if (hwc->idx >= UNCORE_PMC_IDX_FIXED)
828 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);
829 else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0)
830 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
831 else
832 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
833}
834
835#define NHMEX_UNCORE_OPS_COMMON_INIT() \
836 .init_box = nhmex_uncore_msr_init_box, \
837 .disable_box = nhmex_uncore_msr_disable_box, \
838 .enable_box = nhmex_uncore_msr_enable_box, \
839 .disable_event = nhmex_uncore_msr_disable_event, \
840 .read_counter = uncore_msr_read_counter
841
842static struct intel_uncore_ops nhmex_uncore_ops = {
843 NHMEX_UNCORE_OPS_COMMON_INIT(),
844 .enable_event = nhmex_uncore_msr_enable_event,
845};
846
847static struct attribute *nhmex_uncore_ubox_formats_attr[] = {
848 &format_attr_event.attr,
849 &format_attr_edge.attr,
850 NULL,
851};
852
853static struct attribute_group nhmex_uncore_ubox_format_group = {
854 .name = "format",
855 .attrs = nhmex_uncore_ubox_formats_attr,
856};
857
858static struct intel_uncore_type nhmex_uncore_ubox = {
859 .name = "ubox",
860 .num_counters = 1,
861 .num_boxes = 1,
862 .perf_ctr_bits = 48,
863 .event_ctl = NHMEX_U_MSR_PMON_EV_SEL,
864 .perf_ctr = NHMEX_U_MSR_PMON_CTR,
865 .event_mask = NHMEX_U_PMON_RAW_EVENT_MASK,
866 .box_ctl = NHMEX_U_MSR_PMON_GLOBAL_CTL,
867 .ops = &nhmex_uncore_ops,
868 .format_group = &nhmex_uncore_ubox_format_group
869};
870
871static struct attribute *nhmex_uncore_cbox_formats_attr[] = {
872 &format_attr_event.attr,
873 &format_attr_umask.attr,
874 &format_attr_edge.attr,
875 &format_attr_inv.attr,
876 &format_attr_thresh8.attr,
877 NULL,
878};
879
880static struct attribute_group nhmex_uncore_cbox_format_group = {
881 .name = "format",
882 .attrs = nhmex_uncore_cbox_formats_attr,
883};
884
885static struct intel_uncore_type nhmex_uncore_cbox = {
886 .name = "cbox",
887 .num_counters = 6,
888 .num_boxes = 8,
889 .perf_ctr_bits = 48,
890 .event_ctl = NHMEX_C0_MSR_PMON_EV_SEL0,
891 .perf_ctr = NHMEX_C0_MSR_PMON_CTR0,
892 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
893 .box_ctl = NHMEX_C0_MSR_PMON_GLOBAL_CTL,
894 .msr_offset = NHMEX_C_MSR_OFFSET,
895 .pair_ctr_ctl = 1,
896 .ops = &nhmex_uncore_ops,
897 .format_group = &nhmex_uncore_cbox_format_group
898};
899
900static struct uncore_event_desc nhmex_uncore_wbox_events[] = {
901 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0"),
902 { /* end: all zeroes */ },
903};
904
905static struct intel_uncore_type nhmex_uncore_wbox = {
906 .name = "wbox",
907 .num_counters = 4,
908 .num_boxes = 1,
909 .perf_ctr_bits = 48,
910 .event_ctl = NHMEX_W_MSR_PMON_CNT0,
911 .perf_ctr = NHMEX_W_MSR_PMON_EVT_SEL0,
912 .fixed_ctr = NHMEX_W_MSR_PMON_FIXED_CTR,
913 .fixed_ctl = NHMEX_W_MSR_PMON_FIXED_CTL,
914 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
915 .box_ctl = NHMEX_W_MSR_GLOBAL_CTL,
916 .pair_ctr_ctl = 1,
917 .event_descs = nhmex_uncore_wbox_events,
918 .ops = &nhmex_uncore_ops,
919 .format_group = &nhmex_uncore_cbox_format_group
920};
921
922static int nhmex_bbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
923{
924 struct hw_perf_event *hwc = &event->hw;
925 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
926 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
927 int ctr, ev_sel;
928
929 ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >>
930 NHMEX_B_PMON_CTR_SHIFT;
931 ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >>
932 NHMEX_B_PMON_CTL_EV_SEL_SHIFT;
933
934 /* events that do not use the match/mask registers */
935 if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) ||
936 (ctr == 2 && ev_sel != 0x4) || ctr == 3)
937 return 0;
938
939 if (box->pmu->pmu_idx == 0)
940 reg1->reg = NHMEX_B0_MSR_MATCH;
941 else
942 reg1->reg = NHMEX_B1_MSR_MATCH;
943 reg1->idx = 0;
944 reg1->config = event->attr.config1;
945 reg2->config = event->attr.config2;
946 return 0;
947}
948
949static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
950{
951 struct hw_perf_event *hwc = &event->hw;
952 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
953 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
954
955 if (reg1->idx != EXTRA_REG_NONE) {
956 wrmsrl(reg1->reg, reg1->config);
957 wrmsrl(reg1->reg + 1, reg2->config);
958 }
959 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
960 (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK));
961}
962
963/*
964 * The Bbox has 4 counters, but each counter monitors different events.
965 * Use bits 6-7 in the event config to select counter.
966 */
967static struct event_constraint nhmex_uncore_bbox_constraints[] = {
968 EVENT_CONSTRAINT(0 , 1, 0xc0),
969 EVENT_CONSTRAINT(0x40, 2, 0xc0),
970 EVENT_CONSTRAINT(0x80, 4, 0xc0),
971 EVENT_CONSTRAINT(0xc0, 8, 0xc0),
972 EVENT_CONSTRAINT_END,
973};
974
975static struct attribute *nhmex_uncore_bbox_formats_attr[] = {
976 &format_attr_event5.attr,
977 &format_attr_counter.attr,
978 &format_attr_match.attr,
979 &format_attr_mask.attr,
980 NULL,
981};
982
983static struct attribute_group nhmex_uncore_bbox_format_group = {
984 .name = "format",
985 .attrs = nhmex_uncore_bbox_formats_attr,
986};
987
988static struct intel_uncore_ops nhmex_uncore_bbox_ops = {
989 NHMEX_UNCORE_OPS_COMMON_INIT(),
990 .enable_event = nhmex_bbox_msr_enable_event,
991 .hw_config = nhmex_bbox_hw_config,
992 .get_constraint = uncore_get_constraint,
993 .put_constraint = uncore_put_constraint,
994};
995
996static struct intel_uncore_type nhmex_uncore_bbox = {
997 .name = "bbox",
998 .num_counters = 4,
999 .num_boxes = 2,
1000 .perf_ctr_bits = 48,
1001 .event_ctl = NHMEX_B0_MSR_PMON_CTL0,
1002 .perf_ctr = NHMEX_B0_MSR_PMON_CTR0,
1003 .event_mask = NHMEX_B_PMON_RAW_EVENT_MASK,
1004 .box_ctl = NHMEX_B0_MSR_PMON_GLOBAL_CTL,
1005 .msr_offset = NHMEX_B_MSR_OFFSET,
1006 .pair_ctr_ctl = 1,
1007 .num_shared_regs = 1,
1008 .constraints = nhmex_uncore_bbox_constraints,
1009 .ops = &nhmex_uncore_bbox_ops,
1010 .format_group = &nhmex_uncore_bbox_format_group
1011};
1012
1013static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1014{
1015 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1016 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1017
1018 if (event->attr.config & NHMEX_S_PMON_MM_CFG_EN) {
1019 reg1->config = event->attr.config1;
1020 reg2->config = event->attr.config2;
1021 } else {
1022 reg1->config = ~0ULL;
1023 reg2->config = ~0ULL;
1024 }
1025
1026 if (box->pmu->pmu_idx == 0)
1027 reg1->reg = NHMEX_S0_MSR_MM_CFG;
1028 else
1029 reg1->reg = NHMEX_S1_MSR_MM_CFG;
1030
1031 reg1->idx = 0;
1032
1033 return 0;
1034}
1035
1036static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1037{
1038 struct hw_perf_event *hwc = &event->hw;
1039 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1040 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1041
1042 wrmsrl(reg1->reg, 0);
1043 if (reg1->config != ~0ULL || reg2->config != ~0ULL) {
1044 wrmsrl(reg1->reg + 1, reg1->config);
1045 wrmsrl(reg1->reg + 2, reg2->config);
1046 wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
1047 }
1048 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
1049}
1050
1051static struct attribute *nhmex_uncore_sbox_formats_attr[] = {
1052 &format_attr_event.attr,
1053 &format_attr_umask.attr,
1054 &format_attr_edge.attr,
1055 &format_attr_inv.attr,
1056 &format_attr_thresh8.attr,
1057 &format_attr_mm_cfg.attr,
1058 &format_attr_match.attr,
1059 &format_attr_mask.attr,
1060 NULL,
1061};
1062
1063static struct attribute_group nhmex_uncore_sbox_format_group = {
1064 .name = "format",
1065 .attrs = nhmex_uncore_sbox_formats_attr,
1066};
1067
1068static struct intel_uncore_ops nhmex_uncore_sbox_ops = {
1069 NHMEX_UNCORE_OPS_COMMON_INIT(),
1070 .enable_event = nhmex_sbox_msr_enable_event,
1071 .hw_config = nhmex_sbox_hw_config,
1072 .get_constraint = uncore_get_constraint,
1073 .put_constraint = uncore_put_constraint,
1074};
1075
1076static struct intel_uncore_type nhmex_uncore_sbox = {
1077 .name = "sbox",
1078 .num_counters = 4,
1079 .num_boxes = 2,
1080 .perf_ctr_bits = 48,
1081 .event_ctl = NHMEX_S0_MSR_PMON_CTL0,
1082 .perf_ctr = NHMEX_S0_MSR_PMON_CTR0,
1083 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
1084 .box_ctl = NHMEX_S0_MSR_PMON_GLOBAL_CTL,
1085 .msr_offset = NHMEX_S_MSR_OFFSET,
1086 .pair_ctr_ctl = 1,
1087 .num_shared_regs = 1,
1088 .ops = &nhmex_uncore_sbox_ops,
1089 .format_group = &nhmex_uncore_sbox_format_group
1090};
1091
1092enum {
1093 EXTRA_REG_NHMEX_M_FILTER,
1094 EXTRA_REG_NHMEX_M_DSP,
1095 EXTRA_REG_NHMEX_M_ISS,
1096 EXTRA_REG_NHMEX_M_MAP,
1097 EXTRA_REG_NHMEX_M_MSC_THR,
1098 EXTRA_REG_NHMEX_M_PGT,
1099 EXTRA_REG_NHMEX_M_PLD,
1100 EXTRA_REG_NHMEX_M_ZDP_CTL_FVC,
1101};
1102
1103static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
1104 MBOX_INC_SEL_EXTAR_REG(0x0, DSP),
1105 MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),
1106 MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),
1107 MBOX_INC_SEL_EXTAR_REG(0x9, ISS),
1108 /* event 0xa uses two extra registers */
1109 MBOX_INC_SEL_EXTAR_REG(0xa, ISS),
1110 MBOX_INC_SEL_EXTAR_REG(0xa, PLD),
1111 MBOX_INC_SEL_EXTAR_REG(0xb, PLD),
1112 /* events 0xd ~ 0x10 use the same extra register */
1113 MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),
1114 MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),
1115 MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),
1116 MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),
1117 MBOX_INC_SEL_EXTAR_REG(0x16, PGT),
1118 MBOX_SET_FLAG_SEL_EXTRA_REG(0x0, DSP),
1119 MBOX_SET_FLAG_SEL_EXTRA_REG(0x1, ISS),
1120 MBOX_SET_FLAG_SEL_EXTRA_REG(0x5, PGT),
1121 MBOX_SET_FLAG_SEL_EXTRA_REG(0x6, MAP),
1122 EVENT_EXTRA_END
1123};
1124
1125static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
1126{
1127 struct intel_uncore_extra_reg *er;
1128 unsigned long flags;
1129 bool ret = false;
1130 u64 mask;
1131
1132 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
1133 er = &box->shared_regs[idx];
1134 raw_spin_lock_irqsave(&er->lock, flags);
1135 if (!atomic_read(&er->ref) || er->config == config) {
1136 atomic_inc(&er->ref);
1137 er->config = config;
1138 ret = true;
1139 }
1140 raw_spin_unlock_irqrestore(&er->lock, flags);
1141
1142 return ret;
1143 }
1144 /*
1145 * The ZDP_CTL_FVC MSR has 4 fields which are used to control
1146 * events 0xd ~ 0x10. Besides these 4 fields, there are additional
1147 * fields which are shared.
1148 */
1149 idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1150 if (WARN_ON_ONCE(idx >= 4))
1151 return false;
1152
1153 /* mask of the shared fields */
1154 mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
1155 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
1156
1157 raw_spin_lock_irqsave(&er->lock, flags);
1158 /* add mask of the non-shared field if it's in use */
1159 if (__BITS_VALUE(atomic_read(&er->ref), idx, 8))
1160 mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1161
1162 if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) {
1163 atomic_add(1 << (idx * 8), &er->ref);
1164 mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
1165 NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1166 er->config &= ~mask;
1167 er->config |= (config & mask);
1168 ret = true;
1169 }
1170 raw_spin_unlock_irqrestore(&er->lock, flags);
1171
1172 return ret;
1173}
1174
1175static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
1176{
1177 struct intel_uncore_extra_reg *er;
1178
1179 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
1180 er = &box->shared_regs[idx];
1181 atomic_dec(&er->ref);
1182 return;
1183 }
1184
1185 idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1186 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
1187 atomic_sub(1 << (idx * 8), &er->ref);
1188}
1189
1190u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
1191{
1192 struct hw_perf_event *hwc = &event->hw;
1193 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1194 int idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
1195 u64 config = reg1->config;
1196
1197 /* get the non-shared control bits and shift them */
1198 idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1199 config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
1200 if (new_idx > orig_idx) {
1201 idx = new_idx - orig_idx;
1202 config <<= 3 * idx;
1203 } else {
1204 idx = orig_idx - new_idx;
1205 config >>= 3 * idx;
1206 }
1207
1208 /* add the shared control bits back */
1209 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
1210 if (modify) {
1211 /* adjust the main event selector */
1212 if (new_idx > orig_idx)
1213 hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
1214 else
1215 hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
1216 reg1->config = config;
1217 reg1->idx = ~0xff | new_idx;
1218 }
1219 return config;
1220}
1221
1222static struct event_constraint *
1223nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1224{
1225 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1226 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1227 int i, idx[2], alloc = 0;
1228 u64 config1 = reg1->config;
1229
1230 idx[0] = __BITS_VALUE(reg1->idx, 0, 8);
1231 idx[1] = __BITS_VALUE(reg1->idx, 1, 8);
1232again:
1233 for (i = 0; i < 2; i++) {
1234 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
1235 idx[i] = 0xff;
1236
1237 if (idx[i] == 0xff)
1238 continue;
1239
1240 if (!nhmex_mbox_get_shared_reg(box, idx[i],
1241 __BITS_VALUE(config1, i, 32)))
1242 goto fail;
1243 alloc |= (0x1 << i);
1244 }
1245
1246 /* for the match/mask registers */
1247 if ((uncore_box_is_fake(box) || !reg2->alloc) &&
1248 !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))
1249 goto fail;
1250
1251 /*
1252 * If it's a fake box -- as per validate_{group,event}() we
1253 * shouldn't touch event state and we can avoid doing so
1254 * since both will only call get_event_constraints() once
1255 * on each event, this avoids the need for reg->alloc.
1256 */
1257 if (!uncore_box_is_fake(box)) {
1258 if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
1259 nhmex_mbox_alter_er(event, idx[0], true);
1260 reg1->alloc |= alloc;
1261 reg2->alloc = 1;
1262 }
1263 return NULL;
1264fail:
1265 if (idx[0] != 0xff && !(alloc & 0x1) &&
1266 idx[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
1267 /*
1268 * events 0xd ~ 0x10 are functional identical, but are
1269 * controlled by different fields in the ZDP_CTL_FVC
1270 * register. If we failed to take one field, try the
1271 * rest 3 choices.
1272 */
1273 BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);
1274 idx[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1275 idx[0] = (idx[0] + 1) % 4;
1276 idx[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
1277 if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {
1278 config1 = nhmex_mbox_alter_er(event, idx[0], false);
1279 goto again;
1280 }
1281 }
1282
1283 if (alloc & 0x1)
1284 nhmex_mbox_put_shared_reg(box, idx[0]);
1285 if (alloc & 0x2)
1286 nhmex_mbox_put_shared_reg(box, idx[1]);
1287 return &constraint_empty;
1288}
1289
1290static void nhmex_mbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
1291{
1292 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1293 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1294
1295 if (uncore_box_is_fake(box))
1296 return;
1297
1298 if (reg1->alloc & 0x1)
1299 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));
1300 if (reg1->alloc & 0x2)
1301 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));
1302 reg1->alloc = 0;
1303
1304 if (reg2->alloc) {
1305 nhmex_mbox_put_shared_reg(box, reg2->idx);
1306 reg2->alloc = 0;
1307 }
1308}
1309
1310static int nhmex_mbox_extra_reg_idx(struct extra_reg *er)
1311{
1312 if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
1313 return er->idx;
1314 return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;
1315}
1316
1317static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1318{
1319 struct intel_uncore_type *type = box->pmu->type;
1320 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1321 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1322 struct extra_reg *er;
1323 unsigned msr;
1324 int reg_idx = 0;
1325
1326 if (WARN_ON_ONCE(reg1->idx != -1))
1327 return -EINVAL;
1328 /*
1329 * The mbox events may require 2 extra MSRs at the most. But only
1330 * the lower 32 bits in these MSRs are significant, so we can use
1331 * config1 to pass two MSRs' config.
1332 */
1333 for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) {
1334 if (er->event != (event->hw.config & er->config_mask))
1335 continue;
1336 if (event->attr.config1 & ~er->valid_mask)
1337 return -EINVAL;
1338 if (er->idx == __BITS_VALUE(reg1->idx, 0, 8) ||
1339 er->idx == __BITS_VALUE(reg1->idx, 1, 8))
1340 continue;
1341 if (WARN_ON_ONCE(reg_idx >= 2))
1342 return -EINVAL;
1343
1344 msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
1345 if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
1346 return -EINVAL;
1347
1348 /* always use the 32~63 bits to pass the PLD config */
1349 if (er->idx == EXTRA_REG_NHMEX_M_PLD)
1350 reg_idx = 1;
1351
1352 reg1->idx &= ~(0xff << (reg_idx * 8));
1353 reg1->reg &= ~(0xffff << (reg_idx * 16));
1354 reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
1355 reg1->reg |= msr << (reg_idx * 16);
1356 reg1->config = event->attr.config1;
1357 reg_idx++;
1358 }
1359 /* use config2 to pass the filter config */
1360 reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
1361 if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
1362 reg2->config = event->attr.config2;
1363 else
1364 reg2->config = ~0ULL;
1365 if (box->pmu->pmu_idx == 0)
1366 reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
1367 else
1368 reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
1369
1370 return 0;
1371}
1372
1373static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)
1374{
1375 struct intel_uncore_extra_reg *er;
1376 unsigned long flags;
1377 u64 config;
1378
1379 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
1380 return box->shared_regs[idx].config;
1381
1382 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
1383 raw_spin_lock_irqsave(&er->lock, flags);
1384 config = er->config;
1385 raw_spin_unlock_irqrestore(&er->lock, flags);
1386 return config;
1387}
1388
1389static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1390{
1391 struct hw_perf_event *hwc = &event->hw;
1392 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1393 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1394 int idx;
1395
1396 idx = __BITS_VALUE(reg1->idx, 0, 8);
1397 if (idx != 0xff)
1398 wrmsrl(__BITS_VALUE(reg1->reg, 0, 16),
1399 nhmex_mbox_shared_reg_config(box, idx));
1400 idx = __BITS_VALUE(reg1->idx, 1, 8);
1401 if (idx != 0xff)
1402 wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
1403 nhmex_mbox_shared_reg_config(box, idx));
1404
1405 wrmsrl(reg2->reg, 0);
1406 if (reg2->config != ~0ULL) {
1407 wrmsrl(reg2->reg + 1,
1408 reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
1409 wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
1410 (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
1411 wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
1412 }
1413
1414 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
1415}
1416
1417DEFINE_UNCORE_FORMAT_ATTR(count_mode, count_mode, "config:2-3");
1418DEFINE_UNCORE_FORMAT_ATTR(storage_mode, storage_mode, "config:4-5");
1419DEFINE_UNCORE_FORMAT_ATTR(wrap_mode, wrap_mode, "config:6");
1420DEFINE_UNCORE_FORMAT_ATTR(flag_mode, flag_mode, "config:7");
1421DEFINE_UNCORE_FORMAT_ATTR(inc_sel, inc_sel, "config:9-13");
1422DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel, set_flag_sel, "config:19-21");
1423DEFINE_UNCORE_FORMAT_ATTR(filter_cfg, filter_cfg, "config2:63");
1424DEFINE_UNCORE_FORMAT_ATTR(filter_match, filter_match, "config2:0-33");
1425DEFINE_UNCORE_FORMAT_ATTR(filter_mask, filter_mask, "config2:34-61");
1426DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1:0-31");
1427DEFINE_UNCORE_FORMAT_ATTR(thr, thr, "config1:0-31");
1428DEFINE_UNCORE_FORMAT_ATTR(fvc, fvc, "config1:0-31");
1429DEFINE_UNCORE_FORMAT_ATTR(pgt, pgt, "config1:0-31");
1430DEFINE_UNCORE_FORMAT_ATTR(map, map, "config1:0-31");
1431DEFINE_UNCORE_FORMAT_ATTR(iss, iss, "config1:0-31");
1432DEFINE_UNCORE_FORMAT_ATTR(pld, pld, "config1:32-63");
1433
1434static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
1435 &format_attr_count_mode.attr,
1436 &format_attr_storage_mode.attr,
1437 &format_attr_wrap_mode.attr,
1438 &format_attr_flag_mode.attr,
1439 &format_attr_inc_sel.attr,
1440 &format_attr_set_flag_sel.attr,
1441 &format_attr_filter_cfg.attr,
1442 &format_attr_filter_match.attr,
1443 &format_attr_filter_mask.attr,
1444 &format_attr_dsp.attr,
1445 &format_attr_thr.attr,
1446 &format_attr_fvc.attr,
1447 &format_attr_pgt.attr,
1448 &format_attr_map.attr,
1449 &format_attr_iss.attr,
1450 &format_attr_pld.attr,
1451 NULL,
1452};
1453
1454static struct attribute_group nhmex_uncore_mbox_format_group = {
1455 .name = "format",
1456 .attrs = nhmex_uncore_mbox_formats_attr,
1457};
1458
1459static struct uncore_event_desc nhmex_uncore_mbox_events[] = {
1460 INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x2800"),
1461 INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x2820"),
1462 { /* end: all zeroes */ },
1463};
1464
1465static struct intel_uncore_ops nhmex_uncore_mbox_ops = {
1466 NHMEX_UNCORE_OPS_COMMON_INIT(),
1467 .enable_event = nhmex_mbox_msr_enable_event,
1468 .hw_config = nhmex_mbox_hw_config,
1469 .get_constraint = nhmex_mbox_get_constraint,
1470 .put_constraint = nhmex_mbox_put_constraint,
1471};
1472
1473static struct intel_uncore_type nhmex_uncore_mbox = {
1474 .name = "mbox",
1475 .num_counters = 6,
1476 .num_boxes = 2,
1477 .perf_ctr_bits = 48,
1478 .event_ctl = NHMEX_M0_MSR_PMU_CTL0,
1479 .perf_ctr = NHMEX_M0_MSR_PMU_CNT0,
1480 .event_mask = NHMEX_M_PMON_RAW_EVENT_MASK,
1481 .box_ctl = NHMEX_M0_MSR_GLOBAL_CTL,
1482 .msr_offset = NHMEX_M_MSR_OFFSET,
1483 .pair_ctr_ctl = 1,
1484 .num_shared_regs = 8,
1485 .event_descs = nhmex_uncore_mbox_events,
1486 .ops = &nhmex_uncore_mbox_ops,
1487 .format_group = &nhmex_uncore_mbox_format_group,
1488};
1489
1490void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
1491{
1492 struct hw_perf_event *hwc = &event->hw;
1493 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1494 int port;
1495
1496 /* adjust the main event selector */
1497 if (reg1->idx % 2) {
1498 reg1->idx--;
1499 hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
1500 } else {
1501 reg1->idx++;
1502 hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
1503 }
1504
1505 /* adjust address or config of extra register */
1506 port = reg1->idx / 6 + box->pmu->pmu_idx * 4;
1507 switch (reg1->idx % 6) {
1508 case 0:
1509 reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG0(port);
1510 break;
1511 case 1:
1512 reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG1(port);
1513 break;
1514 case 2:
1515 /* the 8~15 bits to the 0~7 bits */
1516 reg1->config >>= 8;
1517 break;
1518 case 3:
1519 /* the 0~7 bits to the 8~15 bits */
1520 reg1->config <<= 8;
1521 break;
1522 case 4:
1523 reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port);
1524 break;
1525 case 5:
1526 reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port);
1527 break;
1528 };
1529}
1530
1531/*
1532 * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7.
1533 * An event set consists of 6 events, the 3rd and 4th events in
1534 * an event set use the same extra register. So an event set uses
1535 * 5 extra registers.
1536 */
1537static struct event_constraint *
1538nhmex_rbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1539{
1540 struct hw_perf_event *hwc = &event->hw;
1541 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1542 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1543 struct intel_uncore_extra_reg *er;
1544 unsigned long flags;
1545 int idx, er_idx;
1546 u64 config1;
1547 bool ok = false;
1548
1549 if (!uncore_box_is_fake(box) && reg1->alloc)
1550 return NULL;
1551
1552 idx = reg1->idx % 6;
1553 config1 = reg1->config;
1554again:
1555 er_idx = idx;
1556 /* the 3rd and 4th events use the same extra register */
1557 if (er_idx > 2)
1558 er_idx--;
1559 er_idx += (reg1->idx / 6) * 5;
1560
1561 er = &box->shared_regs[er_idx];
1562 raw_spin_lock_irqsave(&er->lock, flags);
1563 if (idx < 2) {
1564 if (!atomic_read(&er->ref) || er->config == reg1->config) {
1565 atomic_inc(&er->ref);
1566 er->config = reg1->config;
1567 ok = true;
1568 }
1569 } else if (idx == 2 || idx == 3) {
1570 /*
1571 * these two events use different fields in a extra register,
1572 * the 0~7 bits and the 8~15 bits respectively.
1573 */
1574 u64 mask = 0xff << ((idx - 2) * 8);
1575 if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||
1576 !((er->config ^ config1) & mask)) {
1577 atomic_add(1 << ((idx - 2) * 8), &er->ref);
1578 er->config &= ~mask;
1579 er->config |= config1 & mask;
1580 ok = true;
1581 }
1582 } else {
1583 if (!atomic_read(&er->ref) ||
1584 (er->config == (hwc->config >> 32) &&
1585 er->config1 == reg1->config &&
1586 er->config2 == reg2->config)) {
1587 atomic_inc(&er->ref);
1588 er->config = (hwc->config >> 32);
1589 er->config1 = reg1->config;
1590 er->config2 = reg2->config;
1591 ok = true;
1592 }
1593 }
1594 raw_spin_unlock_irqrestore(&er->lock, flags);
1595
1596 if (!ok) {
1597 /*
1598 * The Rbox events are always in pairs. The paired
1599 * events are functional identical, but use different
1600 * extra registers. If we failed to take an extra
1601 * register, try the alternative.
1602 */
1603 if (idx % 2)
1604 idx--;
1605 else
1606 idx++;
1607 if (idx != reg1->idx % 6) {
1608 if (idx == 2)
1609 config1 >>= 8;
1610 else if (idx == 3)
1611 config1 <<= 8;
1612 goto again;
1613 }
1614 } else {
1615 if (!uncore_box_is_fake(box)) {
1616 if (idx != reg1->idx % 6)
1617 nhmex_rbox_alter_er(box, event);
1618 reg1->alloc = 1;
1619 }
1620 return NULL;
1621 }
1622 return &constraint_empty;
1623}
1624
1625static void nhmex_rbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
1626{
1627 struct intel_uncore_extra_reg *er;
1628 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1629 int idx, er_idx;
1630
1631 if (uncore_box_is_fake(box) || !reg1->alloc)
1632 return;
1633
1634 idx = reg1->idx % 6;
1635 er_idx = idx;
1636 if (er_idx > 2)
1637 er_idx--;
1638 er_idx += (reg1->idx / 6) * 5;
1639
1640 er = &box->shared_regs[er_idx];
1641 if (idx == 2 || idx == 3)
1642 atomic_sub(1 << ((idx - 2) * 8), &er->ref);
1643 else
1644 atomic_dec(&er->ref);
1645
1646 reg1->alloc = 0;
1647}
1648
1649static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1650{
1651 struct hw_perf_event *hwc = &event->hw;
1652 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1653 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
1654 int port, idx;
1655
1656 idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>
1657 NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
1658 if (idx >= 0x18)
1659 return -EINVAL;
1660
1661 reg1->idx = idx;
1662 reg1->config = event->attr.config1;
1663
1664 port = idx / 6 + box->pmu->pmu_idx * 4;
1665 idx %= 6;
1666 switch (idx) {
1667 case 0:
1668 reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG0(port);
1669 break;
1670 case 1:
1671 reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG1(port);
1672 break;
1673 case 2:
1674 case 3:
1675 reg1->reg = NHMEX_R_MSR_PORTN_QLX_CFG(port);
1676 break;
1677 case 4:
1678 case 5:
1679 if (idx == 4)
1680 reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port);
1681 else
1682 reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port);
1683 reg2->config = event->attr.config2;
1684 hwc->config |= event->attr.config & (~0ULL << 32);
1685 break;
1686 };
1687 return 0;
1688}
1689
1690static u64 nhmex_rbox_shared_reg_config(struct intel_uncore_box *box, int idx)
1691{
1692 struct intel_uncore_extra_reg *er;
1693 unsigned long flags;
1694 u64 config;
1695
1696 er = &box->shared_regs[idx];
1697
1698 raw_spin_lock_irqsave(&er->lock, flags);
1699 config = er->config;
1700 raw_spin_unlock_irqrestore(&er->lock, flags);
1701
1702 return config;
1703}
1704
1705static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1706{
1707 struct hw_perf_event *hwc = &event->hw;
1708 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1709 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
1710 int idx, er_idx;
1711
1712 idx = reg1->idx % 6;
1713 er_idx = idx;
1714 if (er_idx > 2)
1715 er_idx--;
1716 er_idx += (reg1->idx / 6) * 5;
1717
1718 switch (idx) {
1719 case 0:
1720 case 1:
1721 wrmsrl(reg1->reg, reg1->config);
1722 break;
1723 case 2:
1724 case 3:
1725 wrmsrl(reg1->reg, nhmex_rbox_shared_reg_config(box, er_idx));
1726 break;
1727 case 4:
1728 case 5:
1729 wrmsrl(reg1->reg, reg1->config);
1730 wrmsrl(reg1->reg + 1, hwc->config >> 32);
1731 wrmsrl(reg1->reg + 2, reg2->config);
1732 break;
1733 };
1734
1735 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
1736 (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
1737}
1738
1739DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config:32-63");
1740DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config1:0-63");
1741DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");
1742DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");
1743DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
1744
1745static struct attribute *nhmex_uncore_rbox_formats_attr[] = {
1746 &format_attr_event5.attr,
1747 &format_attr_xbr_mm_cfg.attr,
1748 &format_attr_xbr_match.attr,
1749 &format_attr_xbr_mask.attr,
1750 &format_attr_qlx_cfg.attr,
1751 &format_attr_iperf_cfg.attr,
1752 NULL,
1753};
1754
1755static struct attribute_group nhmex_uncore_rbox_format_group = {
1756 .name = "format",
1757 .attrs = nhmex_uncore_rbox_formats_attr,
1758};
1759
1760static struct uncore_event_desc nhmex_uncore_rbox_events[] = {
1761 INTEL_UNCORE_EVENT_DESC(qpi0_flit_send, "event=0x0,iperf_cfg=0x80000000"),
1762 INTEL_UNCORE_EVENT_DESC(qpi1_filt_send, "event=0x6,iperf_cfg=0x80000000"),
1763 INTEL_UNCORE_EVENT_DESC(qpi0_idle_filt, "event=0x0,iperf_cfg=0x40000000"),
1764 INTEL_UNCORE_EVENT_DESC(qpi1_idle_filt, "event=0x6,iperf_cfg=0x40000000"),
1765 INTEL_UNCORE_EVENT_DESC(qpi0_date_response, "event=0x0,iperf_cfg=0xc4"),
1766 INTEL_UNCORE_EVENT_DESC(qpi1_date_response, "event=0x6,iperf_cfg=0xc4"),
1767 { /* end: all zeroes */ },
1768};
1769
1770static struct intel_uncore_ops nhmex_uncore_rbox_ops = {
1771 NHMEX_UNCORE_OPS_COMMON_INIT(),
1772 .enable_event = nhmex_rbox_msr_enable_event,
1773 .hw_config = nhmex_rbox_hw_config,
1774 .get_constraint = nhmex_rbox_get_constraint,
1775 .put_constraint = nhmex_rbox_put_constraint,
1776};
1777
1778static struct intel_uncore_type nhmex_uncore_rbox = {
1779 .name = "rbox",
1780 .num_counters = 8,
1781 .num_boxes = 2,
1782 .perf_ctr_bits = 48,
1783 .event_ctl = NHMEX_R_MSR_PMON_CTL0,
1784 .perf_ctr = NHMEX_R_MSR_PMON_CNT0,
1785 .event_mask = NHMEX_R_PMON_RAW_EVENT_MASK,
1786 .box_ctl = NHMEX_R_MSR_GLOBAL_CTL,
1787 .msr_offset = NHMEX_R_MSR_OFFSET,
1788 .pair_ctr_ctl = 1,
1789 .num_shared_regs = 20,
1790 .event_descs = nhmex_uncore_rbox_events,
1791 .ops = &nhmex_uncore_rbox_ops,
1792 .format_group = &nhmex_uncore_rbox_format_group
1793};
1794
1795static struct intel_uncore_type *nhmex_msr_uncores[] = {
1796 &nhmex_uncore_ubox,
1797 &nhmex_uncore_cbox,
1798 &nhmex_uncore_bbox,
1799 &nhmex_uncore_sbox,
1800 &nhmex_uncore_mbox,
1801 &nhmex_uncore_rbox,
1802 &nhmex_uncore_wbox,
1803 NULL,
1804};
1805/* end of Nehalem-EX uncore support */
1806
1807static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
774{ 1808{
775 struct hw_perf_event *hwc = &event->hw; 1809 struct hw_perf_event *hwc = &event->hw;
776 1810
@@ -787,8 +1821,7 @@ static void uncore_assign_hw_event(struct intel_uncore_box *box,
787 hwc->event_base = uncore_perf_ctr(box, hwc->idx); 1821 hwc->event_base = uncore_perf_ctr(box, hwc->idx);
788} 1822}
789 1823
790static void uncore_perf_event_update(struct intel_uncore_box *box, 1824static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
791 struct perf_event *event)
792{ 1825{
793 u64 prev_count, new_count, delta; 1826 u64 prev_count, new_count, delta;
794 int shift; 1827 int shift;
@@ -858,14 +1891,12 @@ static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
858 box->hrtimer.function = uncore_pmu_hrtimer; 1891 box->hrtimer.function = uncore_pmu_hrtimer;
859} 1892}
860 1893
861struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, 1894struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int cpu)
862 int cpu)
863{ 1895{
864 struct intel_uncore_box *box; 1896 struct intel_uncore_box *box;
865 int i, size; 1897 int i, size;
866 1898
867 size = sizeof(*box) + type->num_shared_regs * 1899 size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
868 sizeof(struct intel_uncore_extra_reg);
869 1900
870 box = kmalloc_node(size, GFP_KERNEL | __GFP_ZERO, cpu_to_node(cpu)); 1901 box = kmalloc_node(size, GFP_KERNEL | __GFP_ZERO, cpu_to_node(cpu));
871 if (!box) 1902 if (!box)
@@ -915,12 +1946,11 @@ static struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
915 * perf core schedules event on the basis of cpu, uncore events are 1946 * perf core schedules event on the basis of cpu, uncore events are
916 * collected by one of the cpus inside a physical package. 1947 * collected by one of the cpus inside a physical package.
917 */ 1948 */
918 return uncore_pmu_to_box(uncore_event_to_pmu(event), 1949 return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
919 smp_processor_id());
920} 1950}
921 1951
922static int uncore_collect_events(struct intel_uncore_box *box, 1952static int
923 struct perf_event *leader, bool dogrp) 1953uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
924{ 1954{
925 struct perf_event *event; 1955 struct perf_event *event;
926 int n, max_count; 1956 int n, max_count;
@@ -952,8 +1982,7 @@ static int uncore_collect_events(struct intel_uncore_box *box,
952} 1982}
953 1983
954static struct event_constraint * 1984static struct event_constraint *
955uncore_get_event_constraint(struct intel_uncore_box *box, 1985uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
956 struct perf_event *event)
957{ 1986{
958 struct intel_uncore_type *type = box->pmu->type; 1987 struct intel_uncore_type *type = box->pmu->type;
959 struct event_constraint *c; 1988 struct event_constraint *c;
@@ -977,15 +2006,13 @@ uncore_get_event_constraint(struct intel_uncore_box *box,
977 return &type->unconstrainted; 2006 return &type->unconstrainted;
978} 2007}
979 2008
980static void uncore_put_event_constraint(struct intel_uncore_box *box, 2009static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
981 struct perf_event *event)
982{ 2010{
983 if (box->pmu->type->ops->put_constraint) 2011 if (box->pmu->type->ops->put_constraint)
984 box->pmu->type->ops->put_constraint(box, event); 2012 box->pmu->type->ops->put_constraint(box, event);
985} 2013}
986 2014
987static int uncore_assign_events(struct intel_uncore_box *box, 2015static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
988 int assign[], int n)
989{ 2016{
990 unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)]; 2017 unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
991 struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX]; 2018 struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX];
@@ -1407,8 +2434,7 @@ static bool pcidrv_registered;
1407/* 2434/*
1408 * add a pci uncore device 2435 * add a pci uncore device
1409 */ 2436 */
1410static int __devinit uncore_pci_add(struct intel_uncore_type *type, 2437static int __devinit uncore_pci_add(struct intel_uncore_type *type, struct pci_dev *pdev)
1411 struct pci_dev *pdev)
1412{ 2438{
1413 struct intel_uncore_pmu *pmu; 2439 struct intel_uncore_pmu *pmu;
1414 struct intel_uncore_box *box; 2440 struct intel_uncore_box *box;
@@ -1485,6 +2511,7 @@ static int __devinit uncore_pci_probe(struct pci_dev *pdev,
1485 struct intel_uncore_type *type; 2511 struct intel_uncore_type *type;
1486 2512
1487 type = (struct intel_uncore_type *)id->driver_data; 2513 type = (struct intel_uncore_type *)id->driver_data;
2514
1488 return uncore_pci_add(type, pdev); 2515 return uncore_pci_add(type, pdev);
1489} 2516}
1490 2517
@@ -1612,8 +2639,8 @@ static int __cpuinit uncore_cpu_prepare(int cpu, int phys_id)
1612 return 0; 2639 return 0;
1613} 2640}
1614 2641
1615static void __cpuinit uncore_change_context(struct intel_uncore_type **uncores, 2642static void __cpuinit
1616 int old_cpu, int new_cpu) 2643uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
1617{ 2644{
1618 struct intel_uncore_type *type; 2645 struct intel_uncore_type *type;
1619 struct intel_uncore_pmu *pmu; 2646 struct intel_uncore_pmu *pmu;
@@ -1694,8 +2721,8 @@ static void __cpuinit uncore_event_init_cpu(int cpu)
1694 uncore_change_context(pci_uncores, -1, cpu); 2721 uncore_change_context(pci_uncores, -1, cpu);
1695} 2722}
1696 2723
1697static int __cpuinit uncore_cpu_notifier(struct notifier_block *self, 2724static int
1698 unsigned long action, void *hcpu) 2725 __cpuinit uncore_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1699{ 2726{
1700 unsigned int cpu = (long)hcpu; 2727 unsigned int cpu = (long)hcpu;
1701 2728
@@ -1732,12 +2759,12 @@ static int __cpuinit uncore_cpu_notifier(struct notifier_block *self,
1732} 2759}
1733 2760
1734static struct notifier_block uncore_cpu_nb __cpuinitdata = { 2761static struct notifier_block uncore_cpu_nb __cpuinitdata = {
1735 .notifier_call = uncore_cpu_notifier, 2762 .notifier_call = uncore_cpu_notifier,
1736 /* 2763 /*
1737 * to migrate uncore events, our notifier should be executed 2764 * to migrate uncore events, our notifier should be executed
1738 * before perf core's notifier. 2765 * before perf core's notifier.
1739 */ 2766 */
1740 .priority = CPU_PRI_PERF + 1, 2767 .priority = CPU_PRI_PERF + 1,
1741}; 2768};
1742 2769
1743static void __init uncore_cpu_setup(void *dummy) 2770static void __init uncore_cpu_setup(void *dummy)
@@ -1767,6 +2794,9 @@ static int __init uncore_cpu_init(void)
1767 snbep_uncore_cbox.num_boxes = max_cores; 2794 snbep_uncore_cbox.num_boxes = max_cores;
1768 msr_uncores = snbep_msr_uncores; 2795 msr_uncores = snbep_msr_uncores;
1769 break; 2796 break;
2797 case 46:
2798 msr_uncores = nhmex_msr_uncores;
2799 break;
1770 default: 2800 default:
1771 return 0; 2801 return 0;
1772 } 2802 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index b13e9ea81def..47b1776a858b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -5,8 +5,6 @@
5#include "perf_event.h" 5#include "perf_event.h"
6 6
7#define UNCORE_PMU_NAME_LEN 32 7#define UNCORE_PMU_NAME_LEN 32
8#define UNCORE_BOX_HASH_SIZE 8
9
10#define UNCORE_PMU_HRTIMER_INTERVAL (60 * NSEC_PER_SEC) 8#define UNCORE_PMU_HRTIMER_INTERVAL (60 * NSEC_PER_SEC)
11 9
12#define UNCORE_FIXED_EVENT 0xff 10#define UNCORE_FIXED_EVENT 0xff
@@ -158,6 +156,193 @@
158#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc 156#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
159#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd 157#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
160 158
159/* NHM-EX event control */
160#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
161#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00
162#define NHMEX_PMON_CTL_EN_BIT0 (1 << 0)
163#define NHMEX_PMON_CTL_EDGE_DET (1 << 18)
164#define NHMEX_PMON_CTL_PMI_EN (1 << 20)
165#define NHMEX_PMON_CTL_EN_BIT22 (1 << 22)
166#define NHMEX_PMON_CTL_INVERT (1 << 23)
167#define NHMEX_PMON_CTL_TRESH_MASK 0xff000000
168#define NHMEX_PMON_RAW_EVENT_MASK (NHMEX_PMON_CTL_EV_SEL_MASK | \
169 NHMEX_PMON_CTL_UMASK_MASK | \
170 NHMEX_PMON_CTL_EDGE_DET | \
171 NHMEX_PMON_CTL_INVERT | \
172 NHMEX_PMON_CTL_TRESH_MASK)
173
174/* NHM-EX Ubox */
175#define NHMEX_U_MSR_PMON_GLOBAL_CTL 0xc00
176#define NHMEX_U_MSR_PMON_CTR 0xc11
177#define NHMEX_U_MSR_PMON_EV_SEL 0xc10
178
179#define NHMEX_U_PMON_GLOBAL_EN (1 << 0)
180#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL 0x0000001e
181#define NHMEX_U_PMON_GLOBAL_EN_ALL (1 << 28)
182#define NHMEX_U_PMON_GLOBAL_RST_ALL (1 << 29)
183#define NHMEX_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
184
185#define NHMEX_U_PMON_RAW_EVENT_MASK \
186 (NHMEX_PMON_CTL_EV_SEL_MASK | \
187 NHMEX_PMON_CTL_EDGE_DET)
188
189/* NHM-EX Cbox */
190#define NHMEX_C0_MSR_PMON_GLOBAL_CTL 0xd00
191#define NHMEX_C0_MSR_PMON_CTR0 0xd11
192#define NHMEX_C0_MSR_PMON_EV_SEL0 0xd10
193#define NHMEX_C_MSR_OFFSET 0x20
194
195/* NHM-EX Bbox */
196#define NHMEX_B0_MSR_PMON_GLOBAL_CTL 0xc20
197#define NHMEX_B0_MSR_PMON_CTR0 0xc31
198#define NHMEX_B0_MSR_PMON_CTL0 0xc30
199#define NHMEX_B_MSR_OFFSET 0x40
200#define NHMEX_B0_MSR_MATCH 0xe45
201#define NHMEX_B0_MSR_MASK 0xe46
202#define NHMEX_B1_MSR_MATCH 0xe4d
203#define NHMEX_B1_MSR_MASK 0xe4e
204
205#define NHMEX_B_PMON_CTL_EN (1 << 0)
206#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT 1
207#define NHMEX_B_PMON_CTL_EV_SEL_MASK \
208 (0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)
209#define NHMEX_B_PMON_CTR_SHIFT 6
210#define NHMEX_B_PMON_CTR_MASK \
211 (0x3 << NHMEX_B_PMON_CTR_SHIFT)
212#define NHMEX_B_PMON_RAW_EVENT_MASK \
213 (NHMEX_B_PMON_CTL_EV_SEL_MASK | \
214 NHMEX_B_PMON_CTR_MASK)
215
216/* NHM-EX Sbox */
217#define NHMEX_S0_MSR_PMON_GLOBAL_CTL 0xc40
218#define NHMEX_S0_MSR_PMON_CTR0 0xc51
219#define NHMEX_S0_MSR_PMON_CTL0 0xc50
220#define NHMEX_S_MSR_OFFSET 0x80
221#define NHMEX_S0_MSR_MM_CFG 0xe48
222#define NHMEX_S0_MSR_MATCH 0xe49
223#define NHMEX_S0_MSR_MASK 0xe4a
224#define NHMEX_S1_MSR_MM_CFG 0xe58
225#define NHMEX_S1_MSR_MATCH 0xe59
226#define NHMEX_S1_MSR_MASK 0xe5a
227
228#define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63)
229
230/* NHM-EX Mbox */
231#define NHMEX_M0_MSR_GLOBAL_CTL 0xca0
232#define NHMEX_M0_MSR_PMU_DSP 0xca5
233#define NHMEX_M0_MSR_PMU_ISS 0xca6
234#define NHMEX_M0_MSR_PMU_MAP 0xca7
235#define NHMEX_M0_MSR_PMU_MSC_THR 0xca8
236#define NHMEX_M0_MSR_PMU_PGT 0xca9
237#define NHMEX_M0_MSR_PMU_PLD 0xcaa
238#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC 0xcab
239#define NHMEX_M0_MSR_PMU_CTL0 0xcb0
240#define NHMEX_M0_MSR_PMU_CNT0 0xcb1
241#define NHMEX_M_MSR_OFFSET 0x40
242#define NHMEX_M0_MSR_PMU_MM_CFG 0xe54
243#define NHMEX_M1_MSR_PMU_MM_CFG 0xe5c
244
245#define NHMEX_M_PMON_MM_CFG_EN (1ULL << 63)
246#define NHMEX_M_PMON_ADDR_MATCH_MASK 0x3ffffffffULL
247#define NHMEX_M_PMON_ADDR_MASK_MASK 0x7ffffffULL
248#define NHMEX_M_PMON_ADDR_MASK_SHIFT 34
249
250#define NHMEX_M_PMON_CTL_EN (1 << 0)
251#define NHMEX_M_PMON_CTL_PMI_EN (1 << 1)
252#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT 2
253#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK \
254 (0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)
255#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT 4
256#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK \
257 (0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)
258#define NHMEX_M_PMON_CTL_WRAP_MODE (1 << 6)
259#define NHMEX_M_PMON_CTL_FLAG_MODE (1 << 7)
260#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT 9
261#define NHMEX_M_PMON_CTL_INC_SEL_MASK \
262 (0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
263#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT 19
264#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK \
265 (0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)
266#define NHMEX_M_PMON_RAW_EVENT_MASK \
267 (NHMEX_M_PMON_CTL_COUNT_MODE_MASK | \
268 NHMEX_M_PMON_CTL_STORAGE_MODE_MASK | \
269 NHMEX_M_PMON_CTL_WRAP_MODE | \
270 NHMEX_M_PMON_CTL_FLAG_MODE | \
271 NHMEX_M_PMON_CTL_INC_SEL_MASK | \
272 NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
273
274
275#define NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK 0x1f
276#define NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK (0x7 << 5)
277#define NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK (0x7 << 8)
278#define NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR (1 << 23)
279#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK \
280 (NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK | \
281 NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK | \
282 NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK | \
283 NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR)
284#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (11 + 3 * (n)))
285
286/*
287 * use the 9~13 bits to select event If the 7th bit is not set,
288 * otherwise use the 19~21 bits to select event.
289 */
290#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
291#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \
292 NHMEX_M_PMON_CTL_FLAG_MODE)
293#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \
294 NHMEX_M_PMON_CTL_FLAG_MODE)
295#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \
296 NHMEX_M_PMON_CTL_FLAG_MODE)
297#define MBOX_INC_SEL_EXTAR_REG(c, r) \
298 EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \
299 MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)
300#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \
301 EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \
302 MBOX_SET_FLAG_SEL_MASK, \
303 (u64)-1, NHMEX_M_##r)
304
305/* NHM-EX Rbox */
306#define NHMEX_R_MSR_GLOBAL_CTL 0xe00
307#define NHMEX_R_MSR_PMON_CTL0 0xe10
308#define NHMEX_R_MSR_PMON_CNT0 0xe11
309#define NHMEX_R_MSR_OFFSET 0x20
310
311#define NHMEX_R_MSR_PORTN_QLX_CFG(n) \
312 ((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))
313#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n) (0xe04 + (n))
314#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n) (0xe24 + (n))
315#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n) \
316 (((n) < 4 ? 0 : 0x10) + (n) * 4)
317#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) \
318 (0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
319#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n) \
320 (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)
321#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n) \
322 (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)
323#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) \
324 (0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
325#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n) \
326 (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)
327#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n) \
328 (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)
329
330#define NHMEX_R_PMON_CTL_EN (1 << 0)
331#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT 1
332#define NHMEX_R_PMON_CTL_EV_SEL_MASK \
333 (0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)
334#define NHMEX_R_PMON_CTL_PMI_EN (1 << 6)
335#define NHMEX_R_PMON_RAW_EVENT_MASK NHMEX_R_PMON_CTL_EV_SEL_MASK
336
337/* NHM-EX Wbox */
338#define NHMEX_W_MSR_GLOBAL_CTL 0xc80
339#define NHMEX_W_MSR_PMON_CNT0 0xc90
340#define NHMEX_W_MSR_PMON_EVT_SEL0 0xc91
341#define NHMEX_W_MSR_PMON_FIXED_CTR 0x394
342#define NHMEX_W_MSR_PMON_FIXED_CTL 0x395
343
344#define NHMEX_W_PMON_GLOBAL_FIXED_EN (1ULL << 31)
345
161struct intel_uncore_ops; 346struct intel_uncore_ops;
162struct intel_uncore_pmu; 347struct intel_uncore_pmu;
163struct intel_uncore_box; 348struct intel_uncore_box;
@@ -178,6 +363,7 @@ struct intel_uncore_type {
178 unsigned msr_offset; 363 unsigned msr_offset;
179 unsigned num_shared_regs:8; 364 unsigned num_shared_regs:8;
180 unsigned single_fixed:1; 365 unsigned single_fixed:1;
366 unsigned pair_ctr_ctl:1;
181 struct event_constraint unconstrainted; 367 struct event_constraint unconstrainted;
182 struct event_constraint *constraints; 368 struct event_constraint *constraints;
183 struct intel_uncore_pmu *pmus; 369 struct intel_uncore_pmu *pmus;
@@ -213,7 +399,7 @@ struct intel_uncore_pmu {
213 399
214struct intel_uncore_extra_reg { 400struct intel_uncore_extra_reg {
215 raw_spinlock_t lock; 401 raw_spinlock_t lock;
216 u64 config1; 402 u64 config, config1, config2;
217 atomic_t ref; 403 atomic_t ref;
218}; 404};
219 405
@@ -323,14 +509,16 @@ unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
323static inline 509static inline
324unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx) 510unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
325{ 511{
326 return idx + box->pmu->type->event_ctl + 512 return box->pmu->type->event_ctl +
513 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
327 box->pmu->type->msr_offset * box->pmu->pmu_idx; 514 box->pmu->type->msr_offset * box->pmu->pmu_idx;
328} 515}
329 516
330static inline 517static inline
331unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx) 518unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
332{ 519{
333 return idx + box->pmu->type->perf_ctr + 520 return box->pmu->type->perf_ctr +
521 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
334 box->pmu->type->msr_offset * box->pmu->pmu_idx; 522 box->pmu->type->msr_offset * box->pmu->pmu_idx;
335} 523}
336 524
@@ -422,3 +610,8 @@ static inline void uncore_box_init(struct intel_uncore_box *box)
422 box->pmu->type->ops->init_box(box); 610 box->pmu->type->ops->init_box(box);
423 } 611 }
424} 612}
613
614static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
615{
616 return (box->phys_id < 0);
617}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 00:20:19 -0500