diff options
author | venkatesh.pallipadi@intel.com <venkatesh.pallipadi@intel.com> | 2008-09-05 21:02:16 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-10-16 10:53:07 -0400 |
commit | b40d575bf0679c45aaf9e1161fc51a6b041b7210 (patch) | |
tree | 03cbbbe4b6144268150447b25ad573ae3abaca50 /arch/x86/kernel | |
parent | 932775a4ab622e3c99bd59f14cc7d96722f79501 (diff) |
x86: HPET_MSI Refactor code in preparation for HPET_MSI
Preparatory patch before the actual HPET MSI changes. Sets up hpet_set_mode
and hpet_next_event for the MSI related changes. Just the code
refactoring and should be zero functional change.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r-- | arch/x86/kernel/hpet.c | 42 |
1 files changed, 27 insertions, 15 deletions
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index acf62fc233da..f7cb5e9e261e 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c | |||
@@ -227,44 +227,44 @@ static void hpet_legacy_clockevent_register(void) | |||
227 | printk(KERN_DEBUG "hpet clockevent registered\n"); | 227 | printk(KERN_DEBUG "hpet clockevent registered\n"); |
228 | } | 228 | } |
229 | 229 | ||
230 | static void hpet_legacy_set_mode(enum clock_event_mode mode, | 230 | static void hpet_set_mode(enum clock_event_mode mode, |
231 | struct clock_event_device *evt) | 231 | struct clock_event_device *evt, int timer) |
232 | { | 232 | { |
233 | unsigned long cfg, cmp, now; | 233 | unsigned long cfg, cmp, now; |
234 | uint64_t delta; | 234 | uint64_t delta; |
235 | 235 | ||
236 | switch(mode) { | 236 | switch(mode) { |
237 | case CLOCK_EVT_MODE_PERIODIC: | 237 | case CLOCK_EVT_MODE_PERIODIC: |
238 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult; | 238 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
239 | delta >>= hpet_clockevent.shift; | 239 | delta >>= evt->shift; |
240 | now = hpet_readl(HPET_COUNTER); | 240 | now = hpet_readl(HPET_COUNTER); |
241 | cmp = now + (unsigned long) delta; | 241 | cmp = now + (unsigned long) delta; |
242 | cfg = hpet_readl(HPET_T0_CFG); | 242 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
243 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | | 243 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
244 | HPET_TN_SETVAL | HPET_TN_32BIT; | 244 | HPET_TN_SETVAL | HPET_TN_32BIT; |
245 | hpet_writel(cfg, HPET_T0_CFG); | 245 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
246 | /* | 246 | /* |
247 | * The first write after writing TN_SETVAL to the | 247 | * The first write after writing TN_SETVAL to the |
248 | * config register sets the counter value, the second | 248 | * config register sets the counter value, the second |
249 | * write sets the period. | 249 | * write sets the period. |
250 | */ | 250 | */ |
251 | hpet_writel(cmp, HPET_T0_CMP); | 251 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
252 | udelay(1); | 252 | udelay(1); |
253 | hpet_writel((unsigned long) delta, HPET_T0_CMP); | 253 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
254 | break; | 254 | break; |
255 | 255 | ||
256 | case CLOCK_EVT_MODE_ONESHOT: | 256 | case CLOCK_EVT_MODE_ONESHOT: |
257 | cfg = hpet_readl(HPET_T0_CFG); | 257 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
258 | cfg &= ~HPET_TN_PERIODIC; | 258 | cfg &= ~HPET_TN_PERIODIC; |
259 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | 259 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; |
260 | hpet_writel(cfg, HPET_T0_CFG); | 260 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
261 | break; | 261 | break; |
262 | 262 | ||
263 | case CLOCK_EVT_MODE_UNUSED: | 263 | case CLOCK_EVT_MODE_UNUSED: |
264 | case CLOCK_EVT_MODE_SHUTDOWN: | 264 | case CLOCK_EVT_MODE_SHUTDOWN: |
265 | cfg = hpet_readl(HPET_T0_CFG); | 265 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
266 | cfg &= ~HPET_TN_ENABLE; | 266 | cfg &= ~HPET_TN_ENABLE; |
267 | hpet_writel(cfg, HPET_T0_CFG); | 267 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
268 | break; | 268 | break; |
269 | 269 | ||
270 | case CLOCK_EVT_MODE_RESUME: | 270 | case CLOCK_EVT_MODE_RESUME: |
@@ -273,14 +273,14 @@ static void hpet_legacy_set_mode(enum clock_event_mode mode, | |||
273 | } | 273 | } |
274 | } | 274 | } |
275 | 275 | ||
276 | static int hpet_legacy_next_event(unsigned long delta, | 276 | static int hpet_next_event(unsigned long delta, |
277 | struct clock_event_device *evt) | 277 | struct clock_event_device *evt, int timer) |
278 | { | 278 | { |
279 | u32 cnt; | 279 | u32 cnt; |
280 | 280 | ||
281 | cnt = hpet_readl(HPET_COUNTER); | 281 | cnt = hpet_readl(HPET_COUNTER); |
282 | cnt += (u32) delta; | 282 | cnt += (u32) delta; |
283 | hpet_writel(cnt, HPET_T0_CMP); | 283 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
284 | 284 | ||
285 | /* | 285 | /* |
286 | * We need to read back the CMP register to make sure that | 286 | * We need to read back the CMP register to make sure that |
@@ -292,6 +292,18 @@ static int hpet_legacy_next_event(unsigned long delta, | |||
292 | return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; | 292 | return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; |
293 | } | 293 | } |
294 | 294 | ||
295 | static void hpet_legacy_set_mode(enum clock_event_mode mode, | ||
296 | struct clock_event_device *evt) | ||
297 | { | ||
298 | hpet_set_mode(mode, evt, 0); | ||
299 | } | ||
300 | |||
301 | static int hpet_legacy_next_event(unsigned long delta, | ||
302 | struct clock_event_device *evt) | ||
303 | { | ||
304 | return hpet_next_event(delta, evt, 0); | ||
305 | } | ||
306 | |||
295 | /* | 307 | /* |
296 | * Clock source related code | 308 | * Clock source related code |
297 | */ | 309 | */ |