Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cpu handling changes from Ingo Molnar:
 "Bigger changes:

   - Intel CPU hardware-enablement: new vector instructions support
     (AVX-512), by Fenghua Yu.

   - Support the clflushopt instruction and use it in appropriate
     places.  clflushopt is similar to clflush but with more relaxed
     ordering, by Ross Zwisler.

   - MSR accessor cleanups, by Borislav Petkov.

   - 'forcepae' boot flag for those who have way too much time to spend
     on way too old Pentium-M systems and want to live way too
     dangerously, by Chris Bainbridge"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, cpu: Add forcepae parameter for booting PAE kernels on PAE-disabled Pentium M
  Rename TAINT_UNSAFE_SMP to TAINT_CPU_OUT_OF_SPEC
  x86, intel: Make MSR_IA32_MISC_ENABLE bit constants systematic
  x86, Intel: Convert to the new bit access MSR accessors
  x86, AMD: Convert to the new bit access MSR accessors
  x86: Add another set of MSR accessor functions
  x86: Use clflushopt in drm_clflush_virt_range
  x86: Use clflushopt in drm_clflush_page
  x86: Use clflushopt in clflush_cache_range
  x86: Add support for the clflushopt instruction
  x86, AVX-512: Enable AVX-512 States Context Switch
  x86, AVX-512: AVX-512 Feature Detection

2 files changed, 43 insertions, 60 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index c67ffa686064..ce8b8ff0e0ef 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -218,7 +218,7 @@ static void amd_k7_smp_check(struct cpuinfo_x86 *c)
          */
         WARN_ONCE(1, "WARNING: This combination of AMD"
                 " processors is not suitable for SMP.\n");
-        add_taint(TAINT_UNSAFE_SMP, LOCKDEP_NOW_UNRELIABLE);
+        add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
 }
 
 static void init_amd_k7(struct cpuinfo_x86 *c)
@@ -233,9 +233,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
         if (c->x86_model >= 6 && c->x86_model <= 10) {
                 if (!cpu_has(c, X86_FEATURE_XMM)) {
                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
-                        rdmsr(MSR_K7_HWCR, l, h);
-                        l &= ~0x00008000;
-                        wrmsr(MSR_K7_HWCR, l, h);
+                        msr_clear_bit(MSR_K7_HWCR, 15);
                         set_cpu_cap(c, X86_FEATURE_XMM);
                 }
         }
@@ -509,14 +507,8 @@ static void early_init_amd(struct cpuinfo_x86 *c)
 #endif
 
         /* F16h erratum 793, CVE-2013-6885 */
-        if (c->x86 == 0x16 && c->x86_model <= 0xf) {
-                u64 val;
-
-                rdmsrl(MSR_AMD64_LS_CFG, val);
-                if (!(val & BIT(15)))
-                        wrmsrl(MSR_AMD64_LS_CFG, val | BIT(15));
-        }
-
+        if (c->x86 == 0x16 && c->x86_model <= 0xf)
+                msr_set_bit(MSR_AMD64_LS_CFG, 15);
 }
 
 static const int amd_erratum_383[];
@@ -536,11 +528,8 @@ static void init_amd(struct cpuinfo_x86 *c)
          * Errata 63 for SH-B3 steppings
          * Errata 122 for all steppings (F+ have it disabled by default)
          */
-        if (c->x86 == 0xf) {
-                rdmsrl(MSR_K7_HWCR, value);
-                value |= 1 << 6;
-                wrmsrl(MSR_K7_HWCR, value);
-        }
+        if (c->x86 == 0xf)
+                msr_set_bit(MSR_K7_HWCR, 6);
 #endif
 
         early_init_amd(c);
@@ -623,14 +612,11 @@ static void init_amd(struct cpuinfo_x86 *c)
             (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
             !cpu_has(c, X86_FEATURE_TOPOEXT)) {
 
-                if (!rdmsrl_safe(0xc0011005, &value)) {
-                        value |= 1ULL << 54;
-                        wrmsrl_safe(0xc0011005, value);
+                if (msr_set_bit(0xc0011005, 54) > 0) {
                         rdmsrl(0xc0011005, value);
-                        if (value & (1ULL << 54)) {
+                        if (value & BIT_64(54)) {
                                 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
-                                printk(KERN_INFO FW_INFO "CPU: Re-enabling "
-                                  "disabled Topology Extensions Support\n");
+                                pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
                         }
                 }
         }
@@ -709,19 +695,12 @@ static void init_amd(struct cpuinfo_x86 *c)
                  * Disable GART TLB Walk Errors on Fam10h. We do this here
                  * because this is always needed when GART is enabled, even in a
                  * kernel which has no MCE support built in.
-                 * BIOS should disable GartTlbWlk Errors themself. If
-                 * it doesn't do it here as suggested by the BKDG.
+                 * BIOS should disable GartTlbWlk Errors already. If
+                 * it doesn't, do it here as suggested by the BKDG.
                  *
                  * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
                  */
-                u64 mask;
-                int err;
-
-                err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
-                if (err == 0) {
-                        mask |= (1 << 10);
-                        wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
-                }
+                msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
 
                 /*
                  * On family 10h BIOS may not have properly enabled WC+ support,
@@ -733,10 +712,7 @@ static void init_amd(struct cpuinfo_x86 *c)
                  * NOTE: we want to use the _safe accessors so as not to #GP kvm
                  * guests on older kvm hosts.
                  */
-
-                rdmsrl_safe(MSR_AMD64_BU_CFG2, &value);
-                value &= ~(1ULL << 24);
-                wrmsrl_safe(MSR_AMD64_BU_CFG2, value);
+                msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
 
                 if (cpu_has_amd_erratum(c, amd_erratum_383))
                         set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5cd9bfabd645..897d6201ef10 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -31,11 +31,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 
         /* Unmask CPUID levels if masked: */
         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
-                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-
-                if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
-                        misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
-                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
+                                  MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
                         c->cpuid_level = cpuid_eax(0);
                         get_cpu_cap(c);
                 }
@@ -129,16 +126,10 @@ static void early_init_intel(struct cpuinfo_x86 *c)
          * Ingo Molnar reported a Pentium D (model 6) and a Xeon
          * (model 2) with the same problem.
          */
-        if (c->x86 == 15) {
-                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-
-                if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
-                        printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
-
-                        misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
-                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-                }
-        }
+        if (c->x86 == 15)
+                if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
+                                  MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
+                        pr_info("kmemcheck: Disabling fast string operations\n");
 #endif
 
         /*
@@ -195,10 +186,16 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
         }
 }
 
-static void intel_workarounds(struct cpuinfo_x86 *c)
+static int forcepae;
+static int __init forcepae_setup(char *__unused)
 {
-        unsigned long lo, hi;
+        forcepae = 1;
+        return 1;
+}
+__setup("forcepae", forcepae_setup);
 
+static void intel_workarounds(struct cpuinfo_x86 *c)
+{
 #ifdef CONFIG_X86_F00F_BUG
         /*
          * All current models of Pentium and Pentium with MMX technology CPUs
@@ -225,16 +222,26 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
                 clear_cpu_cap(c, X86_FEATURE_SEP);
 
         /*
+         * PAE CPUID issue: many Pentium M report no PAE but may have a
+         * functionally usable PAE implementation.
+         * Forcefully enable PAE if kernel parameter "forcepae" is present.
+         */
+        if (forcepae) {
+                printk(KERN_WARNING "PAE forced!\n");
+                set_cpu_cap(c, X86_FEATURE_PAE);
+                add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
+        }
+
+        /*
          * P4 Xeon errata 037 workaround.
          * Hardware prefetcher may cause stale data to be loaded into the cache.
          */
         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
-                rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
-                if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
-                        printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
-                        printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
-                        lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
-                        wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
+                if (msr_set_bit(MSR_IA32_MISC_ENABLE,
+                                MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
+                    > 0) {
+                        pr_info("CPU: C0 stepping P4 Xeon detected.\n");
+                        pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
                 }
         }