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authorYinghai Lu <yhlu.kernel@gmail.com>2008-08-19 23:50:42 -0400
committerIngo Molnar <mingo@elte.hu>2008-10-16 10:52:55 -0400
commit26d347c2c035b1f4c5b3c5094f3046db9ec920f5 (patch)
treebbb6dc5b6473c3d1c00255e844a21ed40809a700 /arch/x86/kernel
parent54168ed7f2a4f3fc2780e645124ae952598da601 (diff)
rename io_apic_64.c and io_apic_32.c to io_apic.c
The two files are now line by line equal. (sans a printk) Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r--arch/x86/kernel/Makefile2
-rw-r--r--arch/x86/kernel/io_apic.c (renamed from arch/x86/kernel/io_apic_32.c)0
-rw-r--r--arch/x86/kernel/io_apic_64.c3913
3 files changed, 1 insertions, 3914 deletions
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 0d41f0343dc0..7264f9c3af8f 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -61,7 +61,7 @@ obj-$(CONFIG_X86_64_SMP) += tsc_sync.o smpcommon.o
61obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o 61obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o
62obj-$(CONFIG_X86_MPPARSE) += mpparse.o 62obj-$(CONFIG_X86_MPPARSE) += mpparse.o
63obj-$(CONFIG_X86_LOCAL_APIC) += apic_$(BITS).o nmi.o 63obj-$(CONFIG_X86_LOCAL_APIC) += apic_$(BITS).o nmi.o
64obj-$(CONFIG_X86_IO_APIC) += io_apic_$(BITS).o 64obj-$(CONFIG_X86_IO_APIC) += io_apic.o
65obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o 65obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o
66obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 66obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
67obj-$(CONFIG_KEXEC) += machine_kexec_$(BITS).o 67obj-$(CONFIG_KEXEC) += machine_kexec_$(BITS).o
diff --git a/arch/x86/kernel/io_apic_32.c b/arch/x86/kernel/io_apic.c
index fba6d6ee3480..fba6d6ee3480 100644
--- a/arch/x86/kernel/io_apic_32.c
+++ b/arch/x86/kernel/io_apic.c
diff --git a/arch/x86/kernel/io_apic_64.c b/arch/x86/kernel/io_apic_64.c
deleted file mode 100644
index 940c4167b325..000000000000
--- a/arch/x86/kernel/io_apic_64.c
+++ /dev/null
@@ -1,3913 +0,0 @@
1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/pci.h>
29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
32#include <linux/module.h>
33#include <linux/sysdev.h>
34#include <linux/msi.h>
35#include <linux/htirq.h>
36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
44
45#include <asm/idle.h>
46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/desc.h>
49#include <asm/proto.h>
50#include <asm/acpi.h>
51#include <asm/dma.h>
52#include <asm/timer.h>
53#include <asm/i8259.h>
54#include <asm/nmi.h>
55#include <asm/msidef.h>
56#include <asm/hypertransport.h>
57#include <asm/setup.h>
58#include <asm/irq_remapping.h>
59
60#include <mach_ipi.h>
61#include <mach_apic.h>
62#include <mach_apicdef.h>
63
64#define __apicdebuginit(type) static type __init
65
66/*
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
69 */
70int sis_apic_bug = -1;
71
72static DEFINE_SPINLOCK(ioapic_lock);
73static DEFINE_SPINLOCK(vector_lock);
74
75int first_free_entry;
76/*
77 * Rough estimation of how many shared IRQs there are, can
78 * be changed anytime.
79 */
80int pin_map_size;
81
82/*
83 * # of IRQ routing registers
84 */
85int nr_ioapic_registers[MAX_IO_APICS];
86
87/* I/O APIC entries */
88struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
89int nr_ioapics;
90
91/* MP IRQ source entries */
92struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
93
94/* # of MP IRQ source entries */
95int mp_irq_entries;
96
97#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
98int mp_bus_id_to_type[MAX_MP_BUSSES];
99#endif
100
101DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
102
103int skip_ioapic_setup;
104
105static int __init parse_noapic(char *str)
106{
107 /* disable IO-APIC */
108 disable_ioapic_setup();
109 return 0;
110}
111early_param("noapic", parse_noapic);
112
113struct irq_cfg;
114struct irq_pin_list;
115struct irq_cfg {
116 unsigned int irq;
117 struct irq_cfg *next;
118 struct irq_pin_list *irq_2_pin;
119 cpumask_t domain;
120 cpumask_t old_domain;
121 unsigned move_cleanup_count;
122 u8 vector;
123 u8 move_in_progress : 1;
124};
125
126/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
127static struct irq_cfg irq_cfg_legacy[] __initdata = {
128 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
129 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
130 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
131 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
132 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
133 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
134 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
135 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
136 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
137 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
138 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
139 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
140 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
141 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
142 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
143 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
144};
145
146static struct irq_cfg irq_cfg_init = { .irq = -1U, };
147/* need to be biger than size of irq_cfg_legacy */
148static int nr_irq_cfg = 32;
149
150static int __init parse_nr_irq_cfg(char *arg)
151{
152 if (arg) {
153 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
154 if (nr_irq_cfg < 32)
155 nr_irq_cfg = 32;
156 }
157 return 0;
158}
159
160early_param("nr_irq_cfg", parse_nr_irq_cfg);
161
162static void init_one_irq_cfg(struct irq_cfg *cfg)
163{
164 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
165}
166
167static struct irq_cfg *irq_cfgx;
168static struct irq_cfg *irq_cfgx_free;
169static void __init init_work(void *data)
170{
171 struct dyn_array *da = data;
172 struct irq_cfg *cfg;
173 int legacy_count;
174 int i;
175
176 cfg = *da->name;
177
178 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
179
180 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
181 for (i = legacy_count; i < *da->nr; i++)
182 init_one_irq_cfg(&cfg[i]);
183
184 for (i = 1; i < *da->nr; i++)
185 cfg[i-1].next = &cfg[i];
186
187 irq_cfgx_free = &irq_cfgx[legacy_count];
188 irq_cfgx[legacy_count - 1].next = NULL;
189}
190
191#define for_each_irq_cfg(cfg) \
192 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
193
194DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
195
196static struct irq_cfg *irq_cfg(unsigned int irq)
197{
198 struct irq_cfg *cfg;
199
200 cfg = irq_cfgx;
201 while (cfg) {
202 if (cfg->irq == irq)
203 return cfg;
204
205 cfg = cfg->next;
206 }
207
208 return NULL;
209}
210
211static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
212{
213 struct irq_cfg *cfg, *cfg_pri;
214 int i;
215 int count = 0;
216
217 cfg_pri = cfg = irq_cfgx;
218 while (cfg) {
219 if (cfg->irq == irq)
220 return cfg;
221
222 cfg_pri = cfg;
223 cfg = cfg->next;
224 count++;
225 }
226
227 if (!irq_cfgx_free) {
228 unsigned long phys;
229 unsigned long total_bytes;
230 /*
231 * we run out of pre-allocate ones, allocate more
232 */
233 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
234
235 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
236 if (after_bootmem)
237 cfg = kzalloc(total_bytes, GFP_ATOMIC);
238 else
239 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
240
241 if (!cfg)
242 panic("please boot with nr_irq_cfg= %d\n", count * 2);
243
244 phys = __pa(cfg);
245 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
246
247 for (i = 0; i < nr_irq_cfg; i++)
248 init_one_irq_cfg(&cfg[i]);
249
250 for (i = 1; i < nr_irq_cfg; i++)
251 cfg[i-1].next = &cfg[i];
252
253 irq_cfgx_free = cfg;
254 }
255
256 cfg = irq_cfgx_free;
257 irq_cfgx_free = irq_cfgx_free->next;
258 cfg->next = NULL;
259 if (cfg_pri)
260 cfg_pri->next = cfg;
261 else
262 irq_cfgx = cfg;
263 cfg->irq = irq;
264 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
265#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
266 {
267 /* dump the results */
268 struct irq_cfg *cfg;
269 unsigned long phys;
270 unsigned long bytes = sizeof(struct irq_cfg);
271
272 printk(KERN_DEBUG "=========================== %d\n", irq);
273 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
274 for_each_irq_cfg(cfg) {
275 phys = __pa(cfg);
276 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
277 }
278 printk(KERN_DEBUG "===========================\n");
279 }
280#endif
281 return cfg;
282}
283
284/*
285 * This is performance-critical, we want to do it O(1)
286 *
287 * the indexing order of this array favors 1:1 mappings
288 * between pins and IRQs.
289 */
290
291struct irq_pin_list {
292 int apic, pin;
293 struct irq_pin_list *next;
294};
295
296static struct irq_pin_list *irq_2_pin_head;
297/* fill one page ? */
298static int nr_irq_2_pin = 0x100;
299static struct irq_pin_list *irq_2_pin_ptr;
300static void __init irq_2_pin_init_work(void *data)
301{
302 struct dyn_array *da = data;
303 struct irq_pin_list *pin;
304 int i;
305
306 pin = *da->name;
307
308 for (i = 1; i < *da->nr; i++)
309 pin[i-1].next = &pin[i];
310
311 irq_2_pin_ptr = &pin[0];
312}
313DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
314
315static struct irq_pin_list *get_one_free_irq_2_pin(void)
316{
317 struct irq_pin_list *pin;
318 int i;
319
320 pin = irq_2_pin_ptr;
321
322 if (pin) {
323 irq_2_pin_ptr = pin->next;
324 pin->next = NULL;
325 return pin;
326 }
327
328 /*
329 * we run out of pre-allocate ones, allocate more
330 */
331 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
332
333 if (after_bootmem)
334 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
335 GFP_ATOMIC);
336 else
337 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
338 nr_irq_2_pin, PAGE_SIZE, 0);
339
340 if (!pin)
341 panic("can not get more irq_2_pin\n");
342
343 for (i = 1; i < nr_irq_2_pin; i++)
344 pin[i-1].next = &pin[i];
345
346 irq_2_pin_ptr = pin->next;
347 pin->next = NULL;
348
349 return pin;
350}
351
352struct io_apic {
353 unsigned int index;
354 unsigned int unused[3];
355 unsigned int data;
356};
357
358static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
359{
360 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
361 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
362}
363
364static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
365{
366 struct io_apic __iomem *io_apic = io_apic_base(apic);
367 writel(reg, &io_apic->index);
368 return readl(&io_apic->data);
369}
370
371static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
372{
373 struct io_apic __iomem *io_apic = io_apic_base(apic);
374 writel(reg, &io_apic->index);
375 writel(value, &io_apic->data);
376}
377
378/*
379 * Re-write a value: to be used for read-modify-write
380 * cycles where the read already set up the index register.
381 *
382 * Older SiS APIC requires we rewrite the index register
383 */
384static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
385{
386 struct io_apic __iomem *io_apic = io_apic_base(apic);
387 if (sis_apic_bug)
388 writel(reg, &io_apic->index);
389 writel(value, &io_apic->data);
390}
391
392#ifdef CONFIG_X86_64
393static bool io_apic_level_ack_pending(unsigned int irq)
394{
395 struct irq_pin_list *entry;
396 unsigned long flags;
397 struct irq_cfg *cfg = irq_cfg(irq);
398
399 spin_lock_irqsave(&ioapic_lock, flags);
400 entry = cfg->irq_2_pin;
401 for (;;) {
402 unsigned int reg;
403 int pin;
404
405 if (!entry)
406 break;
407 pin = entry->pin;
408 reg = io_apic_read(entry->apic, 0x10 + pin*2);
409 /* Is the remote IRR bit set? */
410 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
411 spin_unlock_irqrestore(&ioapic_lock, flags);
412 return true;
413 }
414 if (!entry->next)
415 break;
416 entry = entry->next;
417 }
418 spin_unlock_irqrestore(&ioapic_lock, flags);
419
420 return false;
421}
422#endif
423
424union entry_union {
425 struct { u32 w1, w2; };
426 struct IO_APIC_route_entry entry;
427};
428
429static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
430{
431 union entry_union eu;
432 unsigned long flags;
433 spin_lock_irqsave(&ioapic_lock, flags);
434 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
435 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
436 spin_unlock_irqrestore(&ioapic_lock, flags);
437 return eu.entry;
438}
439
440/*
441 * When we write a new IO APIC routing entry, we need to write the high
442 * word first! If the mask bit in the low word is clear, we will enable
443 * the interrupt, and we need to make sure the entry is fully populated
444 * before that happens.
445 */
446static void
447__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
448{
449 union entry_union eu;
450 eu.entry = e;
451 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
452 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
453}
454
455static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
456{
457 unsigned long flags;
458 spin_lock_irqsave(&ioapic_lock, flags);
459 __ioapic_write_entry(apic, pin, e);
460 spin_unlock_irqrestore(&ioapic_lock, flags);
461}
462
463/*
464 * When we mask an IO APIC routing entry, we need to write the low
465 * word first, in order to set the mask bit before we change the
466 * high bits!
467 */
468static void ioapic_mask_entry(int apic, int pin)
469{
470 unsigned long flags;
471 union entry_union eu = { .entry.mask = 1 };
472
473 spin_lock_irqsave(&ioapic_lock, flags);
474 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
475 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
476 spin_unlock_irqrestore(&ioapic_lock, flags);
477}
478
479#ifdef CONFIG_SMP
480static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
481{
482 int apic, pin;
483 struct irq_cfg *cfg;
484 struct irq_pin_list *entry;
485
486 cfg = irq_cfg(irq);
487 entry = cfg->irq_2_pin;
488 for (;;) {
489 unsigned int reg;
490
491 if (!entry)
492 break;
493
494 apic = entry->apic;
495 pin = entry->pin;
496#ifdef CONFIG_INTR_REMAP
497 /*
498 * With interrupt-remapping, destination information comes
499 * from interrupt-remapping table entry.
500 */
501 if (!irq_remapped(irq))
502 io_apic_write(apic, 0x11 + pin*2, dest);
503#else
504 io_apic_write(apic, 0x11 + pin*2, dest);
505#endif
506 reg = io_apic_read(apic, 0x10 + pin*2);
507 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
508 reg |= vector;
509 io_apic_modify(apic, 0x10 + pin*2, reg);
510 if (!entry->next)
511 break;
512 entry = entry->next;
513 }
514}
515
516static int assign_irq_vector(int irq, cpumask_t mask);
517
518static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
519{
520 struct irq_cfg *cfg;
521 unsigned long flags;
522 unsigned int dest;
523 cpumask_t tmp;
524 struct irq_desc *desc;
525
526 cpus_and(tmp, mask, cpu_online_map);
527 if (cpus_empty(tmp))
528 return;
529
530 cfg = irq_cfg(irq);
531 if (assign_irq_vector(irq, mask))
532 return;
533
534 cpus_and(tmp, cfg->domain, mask);
535 dest = cpu_mask_to_apicid(tmp);
536 /*
537 * Only the high 8 bits are valid.
538 */
539 dest = SET_APIC_LOGICAL_ID(dest);
540
541 desc = irq_to_desc(irq);
542 spin_lock_irqsave(&ioapic_lock, flags);
543 __target_IO_APIC_irq(irq, dest, cfg->vector);
544 desc->affinity = mask;
545 spin_unlock_irqrestore(&ioapic_lock, flags);
546}
547#endif /* CONFIG_SMP */
548
549/*
550 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
551 * shared ISA-space IRQs, so we have to support them. We are super
552 * fast in the common case, and fast for shared ISA-space IRQs.
553 */
554static void add_pin_to_irq(unsigned int irq, int apic, int pin)
555{
556 struct irq_cfg *cfg;
557 struct irq_pin_list *entry;
558
559 /* first time to refer irq_cfg, so with new */
560 cfg = irq_cfg_alloc(irq);
561 entry = cfg->irq_2_pin;
562 if (!entry) {
563 entry = get_one_free_irq_2_pin();
564 cfg->irq_2_pin = entry;
565 entry->apic = apic;
566 entry->pin = pin;
567 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
568 return;
569 }
570
571 while (entry->next) {
572 /* not again, please */
573 if (entry->apic == apic && entry->pin == pin)
574 return;
575
576 entry = entry->next;
577 }
578
579 entry->next = get_one_free_irq_2_pin();
580 entry = entry->next;
581 entry->apic = apic;
582 entry->pin = pin;
583 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
584}
585
586/*
587 * Reroute an IRQ to a different pin.
588 */
589static void __init replace_pin_at_irq(unsigned int irq,
590 int oldapic, int oldpin,
591 int newapic, int newpin)
592{
593 struct irq_cfg *cfg = irq_cfg(irq);
594 struct irq_pin_list *entry = cfg->irq_2_pin;
595 int replaced = 0;
596
597 while (entry) {
598 if (entry->apic == oldapic && entry->pin == oldpin) {
599 entry->apic = newapic;
600 entry->pin = newpin;
601 replaced = 1;
602 /* every one is different, right? */
603 break;
604 }
605 entry = entry->next;
606 }
607
608 /* why? call replace before add? */
609 if (!replaced)
610 add_pin_to_irq(irq, newapic, newpin);
611}
612
613#ifdef CONFIG_X86_64
614/*
615 * Synchronize the IO-APIC and the CPU by doing
616 * a dummy read from the IO-APIC
617 */
618static inline void io_apic_sync(unsigned int apic)
619{
620 struct io_apic __iomem *io_apic = io_apic_base(apic);
621 readl(&io_apic->data);
622}
623
624#define __DO_ACTION(R, ACTION, FINAL) \
625 \
626{ \
627 int pin; \
628 struct irq_cfg *cfg; \
629 struct irq_pin_list *entry; \
630 \
631 cfg = irq_cfg(irq); \
632 entry = cfg->irq_2_pin; \
633 for (;;) { \
634 unsigned int reg; \
635 if (!entry) \
636 break; \
637 pin = entry->pin; \
638 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
639 reg ACTION; \
640 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
641 FINAL; \
642 if (!entry->next) \
643 break; \
644 entry = entry->next; \
645 } \
646}
647
648#define DO_ACTION(name,R,ACTION, FINAL) \
649 \
650 static void name##_IO_APIC_irq (unsigned int irq) \
651 __DO_ACTION(R, ACTION, FINAL)
652
653/* mask = 1 */
654DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
655
656/* mask = 0 */
657DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
658
659#else
660
661static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
662{
663 struct irq_cfg *cfg;
664 struct irq_pin_list *entry;
665 unsigned int pin, reg;
666
667 cfg = irq_cfg(irq);
668 entry = cfg->irq_2_pin;
669 for (;;) {
670 if (!entry)
671 break;
672 pin = entry->pin;
673 reg = io_apic_read(entry->apic, 0x10 + pin*2);
674 reg &= ~disable;
675 reg |= enable;
676 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
677 if (!entry->next)
678 break;
679 entry = entry->next;
680 }
681}
682
683/* mask = 1 */
684static void __mask_IO_APIC_irq(unsigned int irq)
685{
686 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
687}
688
689/* mask = 0 */
690static void __unmask_IO_APIC_irq(unsigned int irq)
691{
692 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
693}
694
695/* mask = 1, trigger = 0 */
696static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
697{
698 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
699 IO_APIC_REDIR_LEVEL_TRIGGER);
700}
701
702/* mask = 0, trigger = 1 */
703static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
704{
705 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
706 IO_APIC_REDIR_MASKED);
707}
708
709#endif
710
711static void mask_IO_APIC_irq (unsigned int irq)
712{
713 unsigned long flags;
714
715 spin_lock_irqsave(&ioapic_lock, flags);
716 __mask_IO_APIC_irq(irq);
717 spin_unlock_irqrestore(&ioapic_lock, flags);
718}
719
720static void unmask_IO_APIC_irq (unsigned int irq)
721{
722 unsigned long flags;
723
724 spin_lock_irqsave(&ioapic_lock, flags);
725 __unmask_IO_APIC_irq(irq);
726 spin_unlock_irqrestore(&ioapic_lock, flags);
727}
728
729static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
730{
731 struct IO_APIC_route_entry entry;
732
733 /* Check delivery_mode to be sure we're not clearing an SMI pin */
734 entry = ioapic_read_entry(apic, pin);
735 if (entry.delivery_mode == dest_SMI)
736 return;
737 /*
738 * Disable it in the IO-APIC irq-routing table:
739 */
740 ioapic_mask_entry(apic, pin);
741}
742
743static void clear_IO_APIC (void)
744{
745 int apic, pin;
746
747 for (apic = 0; apic < nr_ioapics; apic++)
748 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
749 clear_IO_APIC_pin(apic, pin);
750}
751
752#if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
753void send_IPI_self(int vector)
754{
755 unsigned int cfg;
756
757 /*
758 * Wait for idle.
759 */
760 apic_wait_icr_idle();
761 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
762 /*
763 * Send the IPI. The write to APIC_ICR fires this off.
764 */
765 apic_write(APIC_ICR, cfg);
766}
767#endif /* !CONFIG_SMP && CONFIG_X86_32*/
768
769#ifdef CONFIG_X86_32
770/*
771 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
772 * specific CPU-side IRQs.
773 */
774
775#define MAX_PIRQS 8
776static int pirq_entries [MAX_PIRQS];
777static int pirqs_enabled;
778
779static int __init ioapic_pirq_setup(char *str)
780{
781 int i, max;
782 int ints[MAX_PIRQS+1];
783
784 get_options(str, ARRAY_SIZE(ints), ints);
785
786 for (i = 0; i < MAX_PIRQS; i++)
787 pirq_entries[i] = -1;
788
789 pirqs_enabled = 1;
790 apic_printk(APIC_VERBOSE, KERN_INFO
791 "PIRQ redirection, working around broken MP-BIOS.\n");
792 max = MAX_PIRQS;
793 if (ints[0] < MAX_PIRQS)
794 max = ints[0];
795
796 for (i = 0; i < max; i++) {
797 apic_printk(APIC_VERBOSE, KERN_DEBUG
798 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
799 /*
800 * PIRQs are mapped upside down, usually.
801 */
802 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
803 }
804 return 1;
805}
806
807__setup("pirq=", ioapic_pirq_setup);
808#endif /* CONFIG_X86_32 */
809
810#ifdef CONFIG_INTR_REMAP
811/* I/O APIC RTE contents at the OS boot up */
812static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
813
814/*
815 * Saves and masks all the unmasked IO-APIC RTE's
816 */
817int save_mask_IO_APIC_setup(void)
818{
819 union IO_APIC_reg_01 reg_01;
820 unsigned long flags;
821 int apic, pin;
822
823 /*
824 * The number of IO-APIC IRQ registers (== #pins):
825 */
826 for (apic = 0; apic < nr_ioapics; apic++) {
827 spin_lock_irqsave(&ioapic_lock, flags);
828 reg_01.raw = io_apic_read(apic, 1);
829 spin_unlock_irqrestore(&ioapic_lock, flags);
830 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
831 }
832
833 for (apic = 0; apic < nr_ioapics; apic++) {
834 early_ioapic_entries[apic] =
835 kzalloc(sizeof(struct IO_APIC_route_entry) *
836 nr_ioapic_registers[apic], GFP_KERNEL);
837 if (!early_ioapic_entries[apic])
838 return -ENOMEM;
839 }
840
841 for (apic = 0; apic < nr_ioapics; apic++)
842 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
843 struct IO_APIC_route_entry entry;
844
845 entry = early_ioapic_entries[apic][pin] =
846 ioapic_read_entry(apic, pin);
847 if (!entry.mask) {
848 entry.mask = 1;
849 ioapic_write_entry(apic, pin, entry);
850 }
851 }
852 return 0;
853}
854
855void restore_IO_APIC_setup(void)
856{
857 int apic, pin;
858
859 for (apic = 0; apic < nr_ioapics; apic++)
860 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
861 ioapic_write_entry(apic, pin,
862 early_ioapic_entries[apic][pin]);
863}
864
865void reinit_intr_remapped_IO_APIC(int intr_remapping)
866{
867 /*
868 * for now plain restore of previous settings.
869 * TBD: In the case of OS enabling interrupt-remapping,
870 * IO-APIC RTE's need to be setup to point to interrupt-remapping
871 * table entries. for now, do a plain restore, and wait for
872 * the setup_IO_APIC_irqs() to do proper initialization.
873 */
874 restore_IO_APIC_setup();
875}
876#endif
877
878/*
879 * Find the IRQ entry number of a certain pin.
880 */
881static int find_irq_entry(int apic, int pin, int type)
882{
883 int i;
884
885 for (i = 0; i < mp_irq_entries; i++)
886 if (mp_irqs[i].mp_irqtype == type &&
887 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
888 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
889 mp_irqs[i].mp_dstirq == pin)
890 return i;
891
892 return -1;
893}
894
895/*
896 * Find the pin to which IRQ[irq] (ISA) is connected
897 */
898static int __init find_isa_irq_pin(int irq, int type)
899{
900 int i;
901
902 for (i = 0; i < mp_irq_entries; i++) {
903 int lbus = mp_irqs[i].mp_srcbus;
904
905 if (test_bit(lbus, mp_bus_not_pci) &&
906 (mp_irqs[i].mp_irqtype == type) &&
907 (mp_irqs[i].mp_srcbusirq == irq))
908
909 return mp_irqs[i].mp_dstirq;
910 }
911 return -1;
912}
913
914static int __init find_isa_irq_apic(int irq, int type)
915{
916 int i;
917
918 for (i = 0; i < mp_irq_entries; i++) {
919 int lbus = mp_irqs[i].mp_srcbus;
920
921 if (test_bit(lbus, mp_bus_not_pci) &&
922 (mp_irqs[i].mp_irqtype == type) &&
923 (mp_irqs[i].mp_srcbusirq == irq))
924 break;
925 }
926 if (i < mp_irq_entries) {
927 int apic;
928 for(apic = 0; apic < nr_ioapics; apic++) {
929 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
930 return apic;
931 }
932 }
933
934 return -1;
935}
936
937/*
938 * Find a specific PCI IRQ entry.
939 * Not an __init, possibly needed by modules
940 */
941static int pin_2_irq(int idx, int apic, int pin);
942
943int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
944{
945 int apic, i, best_guess = -1;
946
947 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
948 bus, slot, pin);
949 if (test_bit(bus, mp_bus_not_pci)) {
950 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
951 return -1;
952 }
953 for (i = 0; i < mp_irq_entries; i++) {
954 int lbus = mp_irqs[i].mp_srcbus;
955
956 for (apic = 0; apic < nr_ioapics; apic++)
957 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
958 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
959 break;
960
961 if (!test_bit(lbus, mp_bus_not_pci) &&
962 !mp_irqs[i].mp_irqtype &&
963 (bus == lbus) &&
964 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
965 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
966
967 if (!(apic || IO_APIC_IRQ(irq)))
968 continue;
969
970 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
971 return irq;
972 /*
973 * Use the first all-but-pin matching entry as a
974 * best-guess fuzzy result for broken mptables.
975 */
976 if (best_guess < 0)
977 best_guess = irq;
978 }
979 }
980 return best_guess;
981}
982
983EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
984
985#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
986/*
987 * EISA Edge/Level control register, ELCR
988 */
989static int EISA_ELCR(unsigned int irq)
990{
991 if (irq < 16) {
992 unsigned int port = 0x4d0 + (irq >> 3);
993 return (inb(port) >> (irq & 7)) & 1;
994 }
995 apic_printk(APIC_VERBOSE, KERN_INFO
996 "Broken MPtable reports ISA irq %d\n", irq);
997 return 0;
998}
999
1000#endif
1001
1002/* ISA interrupts are always polarity zero edge triggered,
1003 * when listed as conforming in the MP table. */
1004
1005#define default_ISA_trigger(idx) (0)
1006#define default_ISA_polarity(idx) (0)
1007
1008/* EISA interrupts are always polarity zero and can be edge or level
1009 * trigger depending on the ELCR value. If an interrupt is listed as
1010 * EISA conforming in the MP table, that means its trigger type must
1011 * be read in from the ELCR */
1012
1013#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1014#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1015
1016/* PCI interrupts are always polarity one level triggered,
1017 * when listed as conforming in the MP table. */
1018
1019#define default_PCI_trigger(idx) (1)
1020#define default_PCI_polarity(idx) (1)
1021
1022/* MCA interrupts are always polarity zero level triggered,
1023 * when listed as conforming in the MP table. */
1024
1025#define default_MCA_trigger(idx) (1)
1026#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1027
1028static int MPBIOS_polarity(int idx)
1029{
1030 int bus = mp_irqs[idx].mp_srcbus;
1031 int polarity;
1032
1033 /*
1034 * Determine IRQ line polarity (high active or low active):
1035 */
1036 switch (mp_irqs[idx].mp_irqflag & 3)
1037 {
1038 case 0: /* conforms, ie. bus-type dependent polarity */
1039 if (test_bit(bus, mp_bus_not_pci))
1040 polarity = default_ISA_polarity(idx);
1041 else
1042 polarity = default_PCI_polarity(idx);
1043 break;
1044 case 1: /* high active */
1045 {
1046 polarity = 0;
1047 break;
1048 }
1049 case 2: /* reserved */
1050 {
1051 printk(KERN_WARNING "broken BIOS!!\n");
1052 polarity = 1;
1053 break;
1054 }
1055 case 3: /* low active */
1056 {
1057 polarity = 1;
1058 break;
1059 }
1060 default: /* invalid */
1061 {
1062 printk(KERN_WARNING "broken BIOS!!\n");
1063 polarity = 1;
1064 break;
1065 }
1066 }
1067 return polarity;
1068}
1069
1070static int MPBIOS_trigger(int idx)
1071{
1072 int bus = mp_irqs[idx].mp_srcbus;
1073 int trigger;
1074
1075 /*
1076 * Determine IRQ trigger mode (edge or level sensitive):
1077 */
1078 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1079 {
1080 case 0: /* conforms, ie. bus-type dependent */
1081 if (test_bit(bus, mp_bus_not_pci))
1082 trigger = default_ISA_trigger(idx);
1083 else
1084 trigger = default_PCI_trigger(idx);
1085#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1086 switch (mp_bus_id_to_type[bus]) {
1087 case MP_BUS_ISA: /* ISA pin */
1088 {
1089 /* set before the switch */
1090 break;
1091 }
1092 case MP_BUS_EISA: /* EISA pin */
1093 {
1094 trigger = default_EISA_trigger(idx);
1095 break;
1096 }
1097 case MP_BUS_PCI: /* PCI pin */
1098 {
1099 /* set before the switch */
1100 break;
1101 }
1102 case MP_BUS_MCA: /* MCA pin */
1103 {
1104 trigger = default_MCA_trigger(idx);
1105 break;
1106 }
1107 default:
1108 {
1109 printk(KERN_WARNING "broken BIOS!!\n");
1110 trigger = 1;
1111 break;
1112 }
1113 }
1114#endif
1115 break;
1116 case 1: /* edge */
1117 {
1118 trigger = 0;
1119 break;
1120 }
1121 case 2: /* reserved */
1122 {
1123 printk(KERN_WARNING "broken BIOS!!\n");
1124 trigger = 1;
1125 break;
1126 }
1127 case 3: /* level */
1128 {
1129 trigger = 1;
1130 break;
1131 }
1132 default: /* invalid */
1133 {
1134 printk(KERN_WARNING "broken BIOS!!\n");
1135 trigger = 0;
1136 break;
1137 }
1138 }
1139 return trigger;
1140}
1141
1142static inline int irq_polarity(int idx)
1143{
1144 return MPBIOS_polarity(idx);
1145}
1146
1147static inline int irq_trigger(int idx)
1148{
1149 return MPBIOS_trigger(idx);
1150}
1151
1152int (*ioapic_renumber_irq)(int ioapic, int irq);
1153static int pin_2_irq(int idx, int apic, int pin)
1154{
1155 int irq, i;
1156 int bus = mp_irqs[idx].mp_srcbus;
1157
1158 /*
1159 * Debugging check, we are in big trouble if this message pops up!
1160 */
1161 if (mp_irqs[idx].mp_dstirq != pin)
1162 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1163
1164 if (test_bit(bus, mp_bus_not_pci)) {
1165 irq = mp_irqs[idx].mp_srcbusirq;
1166 } else {
1167 /*
1168 * PCI IRQs are mapped in order
1169 */
1170 i = irq = 0;
1171 while (i < apic)
1172 irq += nr_ioapic_registers[i++];
1173 irq += pin;
1174 /*
1175 * For MPS mode, so far only needed by ES7000 platform
1176 */
1177 if (ioapic_renumber_irq)
1178 irq = ioapic_renumber_irq(apic, irq);
1179 }
1180
1181#ifdef CONFIG_X86_32
1182 /*
1183 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1184 */
1185 if ((pin >= 16) && (pin <= 23)) {
1186 if (pirq_entries[pin-16] != -1) {
1187 if (!pirq_entries[pin-16]) {
1188 apic_printk(APIC_VERBOSE, KERN_DEBUG
1189 "disabling PIRQ%d\n", pin-16);
1190 } else {
1191 irq = pirq_entries[pin-16];
1192 apic_printk(APIC_VERBOSE, KERN_DEBUG
1193 "using PIRQ%d -> IRQ %d\n",
1194 pin-16, irq);
1195 }
1196 }
1197 }
1198#endif
1199
1200 return irq;
1201}
1202
1203void lock_vector_lock(void)
1204{
1205 /* Used to the online set of cpus does not change
1206 * during assign_irq_vector.
1207 */
1208 spin_lock(&vector_lock);
1209}
1210
1211void unlock_vector_lock(void)
1212{
1213 spin_unlock(&vector_lock);
1214}
1215
1216static int __assign_irq_vector(int irq, cpumask_t mask)
1217{
1218 /*
1219 * NOTE! The local APIC isn't very good at handling
1220 * multiple interrupts at the same interrupt level.
1221 * As the interrupt level is determined by taking the
1222 * vector number and shifting that right by 4, we
1223 * want to spread these out a bit so that they don't
1224 * all fall in the same interrupt level.
1225 *
1226 * Also, we've got to be careful not to trash gate
1227 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1228 */
1229 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1230 unsigned int old_vector;
1231 int cpu;
1232 struct irq_cfg *cfg;
1233
1234 cfg = irq_cfg(irq);
1235
1236 /* Only try and allocate irqs on cpus that are present */
1237 cpus_and(mask, mask, cpu_online_map);
1238
1239 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1240 return -EBUSY;
1241
1242 old_vector = cfg->vector;
1243 if (old_vector) {
1244 cpumask_t tmp;
1245 cpus_and(tmp, cfg->domain, mask);
1246 if (!cpus_empty(tmp))
1247 return 0;
1248 }
1249
1250 for_each_cpu_mask_nr(cpu, mask) {
1251 cpumask_t domain, new_mask;
1252 int new_cpu;
1253 int vector, offset;
1254
1255 domain = vector_allocation_domain(cpu);
1256 cpus_and(new_mask, domain, cpu_online_map);
1257
1258 vector = current_vector;
1259 offset = current_offset;
1260next:
1261 vector += 8;
1262 if (vector >= first_system_vector) {
1263 /* If we run out of vectors on large boxen, must share them. */
1264 offset = (offset + 1) % 8;
1265 vector = FIRST_DEVICE_VECTOR + offset;
1266 }
1267 if (unlikely(current_vector == vector))
1268 continue;
1269#ifdef CONFIG_X86_64
1270 if (vector == IA32_SYSCALL_VECTOR)
1271 goto next;
1272#else
1273 if (vector == SYSCALL_VECTOR)
1274 goto next;
1275#endif
1276 for_each_cpu_mask_nr(new_cpu, new_mask)
1277 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1278 goto next;
1279 /* Found one! */
1280 current_vector = vector;
1281 current_offset = offset;
1282 if (old_vector) {
1283 cfg->move_in_progress = 1;
1284 cfg->old_domain = cfg->domain;
1285 }
1286 for_each_cpu_mask_nr(new_cpu, new_mask)
1287 per_cpu(vector_irq, new_cpu)[vector] = irq;
1288 cfg->vector = vector;
1289 cfg->domain = domain;
1290 return 0;
1291 }
1292 return -ENOSPC;
1293}
1294
1295static int assign_irq_vector(int irq, cpumask_t mask)
1296{
1297 int err;
1298 unsigned long flags;
1299
1300 spin_lock_irqsave(&vector_lock, flags);
1301 err = __assign_irq_vector(irq, mask);
1302 spin_unlock_irqrestore(&vector_lock, flags);
1303 return err;
1304}
1305
1306static void __clear_irq_vector(int irq)
1307{
1308 struct irq_cfg *cfg;
1309 cpumask_t mask;
1310 int cpu, vector;
1311
1312 cfg = irq_cfg(irq);
1313 BUG_ON(!cfg->vector);
1314
1315 vector = cfg->vector;
1316 cpus_and(mask, cfg->domain, cpu_online_map);
1317 for_each_cpu_mask_nr(cpu, mask)
1318 per_cpu(vector_irq, cpu)[vector] = -1;
1319
1320 cfg->vector = 0;
1321 cpus_clear(cfg->domain);
1322}
1323
1324void __setup_vector_irq(int cpu)
1325{
1326 /* Initialize vector_irq on a new cpu */
1327 /* This function must be called with vector_lock held */
1328 int irq, vector;
1329 struct irq_cfg *cfg;
1330
1331 /* Mark the inuse vectors */
1332 for_each_irq_cfg(cfg) {
1333 if (!cpu_isset(cpu, cfg->domain))
1334 continue;
1335 vector = cfg->vector;
1336 irq = cfg->irq;
1337 per_cpu(vector_irq, cpu)[vector] = irq;
1338 }
1339 /* Mark the free vectors */
1340 for (vector = 0; vector < NR_VECTORS; ++vector) {
1341 irq = per_cpu(vector_irq, cpu)[vector];
1342 if (irq < 0)
1343 continue;
1344
1345 cfg = irq_cfg(irq);
1346 if (!cpu_isset(cpu, cfg->domain))
1347 per_cpu(vector_irq, cpu)[vector] = -1;
1348 }
1349}
1350
1351static struct irq_chip ioapic_chip;
1352#ifdef CONFIG_INTR_REMAP
1353static struct irq_chip ir_ioapic_chip;
1354#endif
1355
1356#define IOAPIC_AUTO -1
1357#define IOAPIC_EDGE 0
1358#define IOAPIC_LEVEL 1
1359
1360#ifdef CONFIG_X86_32
1361static inline int IO_APIC_irq_trigger(int irq)
1362{
1363 int apic, idx, pin;
1364
1365 for (apic = 0; apic < nr_ioapics; apic++) {
1366 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1367 idx = find_irq_entry(apic, pin, mp_INT);
1368 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1369 return irq_trigger(idx);
1370 }
1371 }
1372 /*
1373 * nonexistent IRQs are edge default
1374 */
1375 return 0;
1376}
1377#else
1378static inline int IO_APIC_irq_trigger(int irq)
1379{
1380 return 1;
1381}
1382#endif
1383
1384static void ioapic_register_intr(int irq, unsigned long trigger)
1385{
1386 struct irq_desc *desc;
1387
1388 /* first time to use this irq_desc */
1389 if (irq < 16)
1390 desc = irq_to_desc(irq);
1391 else
1392 desc = irq_to_desc_alloc(irq);
1393
1394 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1395 trigger == IOAPIC_LEVEL)
1396 desc->status |= IRQ_LEVEL;
1397 else
1398 desc->status &= ~IRQ_LEVEL;
1399
1400#ifdef CONFIG_INTR_REMAP
1401 if (irq_remapped(irq)) {
1402 desc->status |= IRQ_MOVE_PCNTXT;
1403 if (trigger)
1404 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1405 handle_fasteoi_irq,
1406 "fasteoi");
1407 else
1408 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1409 handle_edge_irq, "edge");
1410 return;
1411 }
1412#endif
1413 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1414 trigger == IOAPIC_LEVEL)
1415 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1416 handle_fasteoi_irq,
1417 "fasteoi");
1418 else
1419 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1420 handle_edge_irq, "edge");
1421}
1422
1423static int setup_ioapic_entry(int apic, int irq,
1424 struct IO_APIC_route_entry *entry,
1425 unsigned int destination, int trigger,
1426 int polarity, int vector)
1427{
1428 /*
1429 * add it to the IO-APIC irq-routing table:
1430 */
1431 memset(entry,0,sizeof(*entry));
1432
1433#ifdef CONFIG_INTR_REMAP
1434 if (intr_remapping_enabled) {
1435 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1436 struct irte irte;
1437 struct IR_IO_APIC_route_entry *ir_entry =
1438 (struct IR_IO_APIC_route_entry *) entry;
1439 int index;
1440
1441 if (!iommu)
1442 panic("No mapping iommu for ioapic %d\n", apic);
1443
1444 index = alloc_irte(iommu, irq, 1);
1445 if (index < 0)
1446 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1447
1448 memset(&irte, 0, sizeof(irte));
1449
1450 irte.present = 1;
1451 irte.dst_mode = INT_DEST_MODE;
1452 irte.trigger_mode = trigger;
1453 irte.dlvry_mode = INT_DELIVERY_MODE;
1454 irte.vector = vector;
1455 irte.dest_id = IRTE_DEST(destination);
1456
1457 modify_irte(irq, &irte);
1458
1459 ir_entry->index2 = (index >> 15) & 0x1;
1460 ir_entry->zero = 0;
1461 ir_entry->format = 1;
1462 ir_entry->index = (index & 0x7fff);
1463 } else
1464#endif
1465 {
1466 entry->delivery_mode = INT_DELIVERY_MODE;
1467 entry->dest_mode = INT_DEST_MODE;
1468 entry->dest = destination;
1469 }
1470
1471 entry->mask = 0; /* enable IRQ */
1472 entry->trigger = trigger;
1473 entry->polarity = polarity;
1474 entry->vector = vector;
1475
1476 /* Mask level triggered irqs.
1477 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1478 */
1479 if (trigger)
1480 entry->mask = 1;
1481 return 0;
1482}
1483
1484static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1485 int trigger, int polarity)
1486{
1487 struct irq_cfg *cfg;
1488 struct IO_APIC_route_entry entry;
1489 cpumask_t mask;
1490
1491 if (!IO_APIC_IRQ(irq))
1492 return;
1493
1494 cfg = irq_cfg(irq);
1495
1496 mask = TARGET_CPUS;
1497 if (assign_irq_vector(irq, mask))
1498 return;
1499
1500 cpus_and(mask, cfg->domain, mask);
1501
1502 apic_printk(APIC_VERBOSE,KERN_DEBUG
1503 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1504 "IRQ %d Mode:%i Active:%i)\n",
1505 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1506 irq, trigger, polarity);
1507
1508
1509 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1510 cpu_mask_to_apicid(mask), trigger, polarity,
1511 cfg->vector)) {
1512 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1513 mp_ioapics[apic].mp_apicid, pin);
1514 __clear_irq_vector(irq);
1515 return;
1516 }
1517
1518 ioapic_register_intr(irq, trigger);
1519 if (irq < 16)
1520 disable_8259A_irq(irq);
1521
1522 ioapic_write_entry(apic, pin, entry);
1523}
1524
1525static void __init setup_IO_APIC_irqs(void)
1526{
1527 int apic, pin, idx, irq, first_notcon = 1;
1528
1529 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1530
1531 for (apic = 0; apic < nr_ioapics; apic++) {
1532 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1533
1534 idx = find_irq_entry(apic,pin,mp_INT);
1535 if (idx == -1) {
1536 if (first_notcon) {
1537 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1538 first_notcon = 0;
1539 } else
1540 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1541 continue;
1542 }
1543 if (!first_notcon) {
1544 apic_printk(APIC_VERBOSE, " not connected.\n");
1545 first_notcon = 1;
1546 }
1547
1548 irq = pin_2_irq(idx, apic, pin);
1549#ifdef CONFIG_X86_32
1550 if (multi_timer_check(apic, irq))
1551 continue;
1552#endif
1553 add_pin_to_irq(irq, apic, pin);
1554
1555 setup_IO_APIC_irq(apic, pin, irq,
1556 irq_trigger(idx), irq_polarity(idx));
1557 }
1558 }
1559
1560 if (!first_notcon)
1561 apic_printk(APIC_VERBOSE, " not connected.\n");
1562}
1563
1564/*
1565 * Set up the timer pin, possibly with the 8259A-master behind.
1566 */
1567static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1568 int vector)
1569{
1570 struct IO_APIC_route_entry entry;
1571
1572#ifdef CONFIG_INTR_REMAP
1573 if (intr_remapping_enabled)
1574 return;
1575#endif
1576
1577 memset(&entry, 0, sizeof(entry));
1578
1579 /*
1580 * We use logical delivery to get the timer IRQ
1581 * to the first CPU.
1582 */
1583 entry.dest_mode = INT_DEST_MODE;
1584 entry.mask = 1; /* mask IRQ now */
1585 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1586 entry.delivery_mode = INT_DELIVERY_MODE;
1587 entry.polarity = 0;
1588 entry.trigger = 0;
1589 entry.vector = vector;
1590
1591 /*
1592 * The timer IRQ doesn't have to know that behind the
1593 * scene we may have a 8259A-master in AEOI mode ...
1594 */
1595 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1596
1597 /*
1598 * Add it to the IO-APIC irq-routing table:
1599 */
1600 ioapic_write_entry(apic, pin, entry);
1601}
1602
1603
1604__apicdebuginit(void) print_IO_APIC(void)
1605{
1606 int apic, i;
1607 union IO_APIC_reg_00 reg_00;
1608 union IO_APIC_reg_01 reg_01;
1609 union IO_APIC_reg_02 reg_02;
1610 union IO_APIC_reg_03 reg_03;
1611 unsigned long flags;
1612 struct irq_cfg *cfg;
1613
1614 if (apic_verbosity == APIC_QUIET)
1615 return;
1616
1617 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1618 for (i = 0; i < nr_ioapics; i++)
1619 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1620 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1621
1622 /*
1623 * We are a bit conservative about what we expect. We have to
1624 * know about every hardware change ASAP.
1625 */
1626 printk(KERN_INFO "testing the IO APIC.......................\n");
1627
1628 for (apic = 0; apic < nr_ioapics; apic++) {
1629
1630 spin_lock_irqsave(&ioapic_lock, flags);
1631 reg_00.raw = io_apic_read(apic, 0);
1632 reg_01.raw = io_apic_read(apic, 1);
1633 if (reg_01.bits.version >= 0x10)
1634 reg_02.raw = io_apic_read(apic, 2);
1635 if (reg_01.bits.version >= 0x20)
1636 reg_03.raw = io_apic_read(apic, 3);
1637 spin_unlock_irqrestore(&ioapic_lock, flags);
1638
1639 printk("\n");
1640 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1641 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1642 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1643 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1644 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1645
1646 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1647 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1648
1649 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1650 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1651
1652 /*
1653 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1654 * but the value of reg_02 is read as the previous read register
1655 * value, so ignore it if reg_02 == reg_01.
1656 */
1657 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1658 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1659 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1660 }
1661
1662 /*
1663 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1664 * or reg_03, but the value of reg_0[23] is read as the previous read
1665 * register value, so ignore it if reg_03 == reg_0[12].
1666 */
1667 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1668 reg_03.raw != reg_01.raw) {
1669 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1670 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1671 }
1672
1673 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1674
1675 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1676 " Stat Dmod Deli Vect: \n");
1677
1678 for (i = 0; i <= reg_01.bits.entries; i++) {
1679 struct IO_APIC_route_entry entry;
1680
1681 entry = ioapic_read_entry(apic, i);
1682
1683 printk(KERN_DEBUG " %02x %03X ",
1684 i,
1685 entry.dest
1686 );
1687
1688 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1689 entry.mask,
1690 entry.trigger,
1691 entry.irr,
1692 entry.polarity,
1693 entry.delivery_status,
1694 entry.dest_mode,
1695 entry.delivery_mode,
1696 entry.vector
1697 );
1698 }
1699 }
1700 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1701 for_each_irq_cfg(cfg) {
1702 struct irq_pin_list *entry = cfg->irq_2_pin;
1703 if (!entry)
1704 continue;
1705 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1706 for (;;) {
1707 printk("-> %d:%d", entry->apic, entry->pin);
1708 if (!entry->next)
1709 break;
1710 entry = entry->next;
1711 }
1712 printk("\n");
1713 }
1714
1715 printk(KERN_INFO ".................................... done.\n");
1716
1717 return;
1718}
1719
1720__apicdebuginit(void) print_APIC_bitfield(int base)
1721{
1722 unsigned int v;
1723 int i, j;
1724
1725 if (apic_verbosity == APIC_QUIET)
1726 return;
1727
1728 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1729 for (i = 0; i < 8; i++) {
1730 v = apic_read(base + i*0x10);
1731 for (j = 0; j < 32; j++) {
1732 if (v & (1<<j))
1733 printk("1");
1734 else
1735 printk("0");
1736 }
1737 printk("\n");
1738 }
1739}
1740
1741__apicdebuginit(void) print_local_APIC(void *dummy)
1742{
1743 unsigned int v, ver, maxlvt;
1744 u64 icr;
1745
1746 if (apic_verbosity == APIC_QUIET)
1747 return;
1748
1749 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1750 smp_processor_id(), hard_smp_processor_id());
1751 v = apic_read(APIC_ID);
1752 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1753 v = apic_read(APIC_LVR);
1754 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1755 ver = GET_APIC_VERSION(v);
1756 maxlvt = lapic_get_maxlvt();
1757
1758 v = apic_read(APIC_TASKPRI);
1759 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1760
1761 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1762 v = apic_read(APIC_ARBPRI);
1763 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1764 v & APIC_ARBPRI_MASK);
1765 v = apic_read(APIC_PROCPRI);
1766 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1767 }
1768
1769 v = apic_read(APIC_EOI);
1770 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1771 v = apic_read(APIC_RRR);
1772 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1773 v = apic_read(APIC_LDR);
1774 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1775 v = apic_read(APIC_DFR);
1776 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1777 v = apic_read(APIC_SPIV);
1778 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1779
1780 printk(KERN_DEBUG "... APIC ISR field:\n");
1781 print_APIC_bitfield(APIC_ISR);
1782 printk(KERN_DEBUG "... APIC TMR field:\n");
1783 print_APIC_bitfield(APIC_TMR);
1784 printk(KERN_DEBUG "... APIC IRR field:\n");
1785 print_APIC_bitfield(APIC_IRR);
1786
1787 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1788 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1789 apic_write(APIC_ESR, 0);
1790
1791 v = apic_read(APIC_ESR);
1792 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1793 }
1794
1795 icr = apic_icr_read();
1796 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1797 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1798
1799 v = apic_read(APIC_LVTT);
1800 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1801
1802 if (maxlvt > 3) { /* PC is LVT#4. */
1803 v = apic_read(APIC_LVTPC);
1804 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1805 }
1806 v = apic_read(APIC_LVT0);
1807 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1808 v = apic_read(APIC_LVT1);
1809 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1810
1811 if (maxlvt > 2) { /* ERR is LVT#3. */
1812 v = apic_read(APIC_LVTERR);
1813 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1814 }
1815
1816 v = apic_read(APIC_TMICT);
1817 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1818 v = apic_read(APIC_TMCCT);
1819 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1820 v = apic_read(APIC_TDCR);
1821 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1822 printk("\n");
1823}
1824
1825__apicdebuginit(void) print_all_local_APICs(void)
1826{
1827 on_each_cpu(print_local_APIC, NULL, 1);
1828}
1829
1830__apicdebuginit(void) print_PIC(void)
1831{
1832 unsigned int v;
1833 unsigned long flags;
1834
1835 if (apic_verbosity == APIC_QUIET)
1836 return;
1837
1838 printk(KERN_DEBUG "\nprinting PIC contents\n");
1839
1840 spin_lock_irqsave(&i8259A_lock, flags);
1841
1842 v = inb(0xa1) << 8 | inb(0x21);
1843 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1844
1845 v = inb(0xa0) << 8 | inb(0x20);
1846 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1847
1848 outb(0x0b,0xa0);
1849 outb(0x0b,0x20);
1850 v = inb(0xa0) << 8 | inb(0x20);
1851 outb(0x0a,0xa0);
1852 outb(0x0a,0x20);
1853
1854 spin_unlock_irqrestore(&i8259A_lock, flags);
1855
1856 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1857
1858 v = inb(0x4d1) << 8 | inb(0x4d0);
1859 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1860}
1861
1862__apicdebuginit(int) print_all_ICs(void)
1863{
1864 print_PIC();
1865 print_all_local_APICs();
1866 print_IO_APIC();
1867
1868 return 0;
1869}
1870
1871fs_initcall(print_all_ICs);
1872
1873
1874/* Where if anywhere is the i8259 connect in external int mode */
1875static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1876
1877void __init enable_IO_APIC(void)
1878{
1879 union IO_APIC_reg_01 reg_01;
1880 int i8259_apic, i8259_pin;
1881 int apic;
1882 unsigned long flags;
1883
1884#ifdef CONFIG_X86_32
1885 int i;
1886 if (!pirqs_enabled)
1887 for (i = 0; i < MAX_PIRQS; i++)
1888 pirq_entries[i] = -1;
1889#endif
1890
1891 /*
1892 * The number of IO-APIC IRQ registers (== #pins):
1893 */
1894 for (apic = 0; apic < nr_ioapics; apic++) {
1895 spin_lock_irqsave(&ioapic_lock, flags);
1896 reg_01.raw = io_apic_read(apic, 1);
1897 spin_unlock_irqrestore(&ioapic_lock, flags);
1898 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1899 }
1900 for(apic = 0; apic < nr_ioapics; apic++) {
1901 int pin;
1902 /* See if any of the pins is in ExtINT mode */
1903 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1904 struct IO_APIC_route_entry entry;
1905 entry = ioapic_read_entry(apic, pin);
1906
1907 /* If the interrupt line is enabled and in ExtInt mode
1908 * I have found the pin where the i8259 is connected.
1909 */
1910 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1911 ioapic_i8259.apic = apic;
1912 ioapic_i8259.pin = pin;
1913 goto found_i8259;
1914 }
1915 }
1916 }
1917 found_i8259:
1918 /* Look to see what if the MP table has reported the ExtINT */
1919 /* If we could not find the appropriate pin by looking at the ioapic
1920 * the i8259 probably is not connected the ioapic but give the
1921 * mptable a chance anyway.
1922 */
1923 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1924 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1925 /* Trust the MP table if nothing is setup in the hardware */
1926 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1927 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1928 ioapic_i8259.pin = i8259_pin;
1929 ioapic_i8259.apic = i8259_apic;
1930 }
1931 /* Complain if the MP table and the hardware disagree */
1932 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1933 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1934 {
1935 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1936 }
1937
1938 /*
1939 * Do not trust the IO-APIC being empty at bootup
1940 */
1941 clear_IO_APIC();
1942}
1943
1944/*
1945 * Not an __init, needed by the reboot code
1946 */
1947void disable_IO_APIC(void)
1948{
1949 /*
1950 * Clear the IO-APIC before rebooting:
1951 */
1952 clear_IO_APIC();
1953
1954 /*
1955 * If the i8259 is routed through an IOAPIC
1956 * Put that IOAPIC in virtual wire mode
1957 * so legacy interrupts can be delivered.
1958 */
1959 if (ioapic_i8259.pin != -1) {
1960 struct IO_APIC_route_entry entry;
1961
1962 memset(&entry, 0, sizeof(entry));
1963 entry.mask = 0; /* Enabled */
1964 entry.trigger = 0; /* Edge */
1965 entry.irr = 0;
1966 entry.polarity = 0; /* High */
1967 entry.delivery_status = 0;
1968 entry.dest_mode = 0; /* Physical */
1969 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1970 entry.vector = 0;
1971 entry.dest = read_apic_id();
1972
1973 /*
1974 * Add it to the IO-APIC irq-routing table:
1975 */
1976 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1977 }
1978
1979 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1980}
1981
1982#ifdef CONFIG_X86_32
1983/*
1984 * function to set the IO-APIC physical IDs based on the
1985 * values stored in the MPC table.
1986 *
1987 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1988 */
1989
1990static void __init setup_ioapic_ids_from_mpc(void)
1991{
1992 union IO_APIC_reg_00 reg_00;
1993 physid_mask_t phys_id_present_map;
1994 int apic;
1995 int i;
1996 unsigned char old_id;
1997 unsigned long flags;
1998
1999 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2000 return;
2001
2002 /*
2003 * Don't check I/O APIC IDs for xAPIC systems. They have
2004 * no meaning without the serial APIC bus.
2005 */
2006 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2007 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2008 return;
2009 /*
2010 * This is broken; anything with a real cpu count has to
2011 * circumvent this idiocy regardless.
2012 */
2013 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2014
2015 /*
2016 * Set the IOAPIC ID to the value stored in the MPC table.
2017 */
2018 for (apic = 0; apic < nr_ioapics; apic++) {
2019
2020 /* Read the register 0 value */
2021 spin_lock_irqsave(&ioapic_lock, flags);
2022 reg_00.raw = io_apic_read(apic, 0);
2023 spin_unlock_irqrestore(&ioapic_lock, flags);
2024
2025 old_id = mp_ioapics[apic].mp_apicid;
2026
2027 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
2028 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2029 apic, mp_ioapics[apic].mp_apicid);
2030 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2031 reg_00.bits.ID);
2032 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
2033 }
2034
2035 /*
2036 * Sanity check, is the ID really free? Every APIC in a
2037 * system must have a unique ID or we get lots of nice
2038 * 'stuck on smp_invalidate_needed IPI wait' messages.
2039 */
2040 if (check_apicid_used(phys_id_present_map,
2041 mp_ioapics[apic].mp_apicid)) {
2042 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2043 apic, mp_ioapics[apic].mp_apicid);
2044 for (i = 0; i < get_physical_broadcast(); i++)
2045 if (!physid_isset(i, phys_id_present_map))
2046 break;
2047 if (i >= get_physical_broadcast())
2048 panic("Max APIC ID exceeded!\n");
2049 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2050 i);
2051 physid_set(i, phys_id_present_map);
2052 mp_ioapics[apic].mp_apicid = i;
2053 } else {
2054 physid_mask_t tmp;
2055 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2056 apic_printk(APIC_VERBOSE, "Setting %d in the "
2057 "phys_id_present_map\n",
2058 mp_ioapics[apic].mp_apicid);
2059 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2060 }
2061
2062
2063 /*
2064 * We need to adjust the IRQ routing table
2065 * if the ID changed.
2066 */
2067 if (old_id != mp_ioapics[apic].mp_apicid)
2068 for (i = 0; i < mp_irq_entries; i++)
2069 if (mp_irqs[i].mp_dstapic == old_id)
2070 mp_irqs[i].mp_dstapic
2071 = mp_ioapics[apic].mp_apicid;
2072
2073 /*
2074 * Read the right value from the MPC table and
2075 * write it into the ID register.
2076 */
2077 apic_printk(APIC_VERBOSE, KERN_INFO
2078 "...changing IO-APIC physical APIC ID to %d ...",
2079 mp_ioapics[apic].mp_apicid);
2080
2081 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2082 spin_lock_irqsave(&ioapic_lock, flags);
2083
2084 /*
2085 * Sanity check
2086 */
2087 spin_lock_irqsave(&ioapic_lock, flags);
2088 reg_00.raw = io_apic_read(apic, 0);
2089 spin_unlock_irqrestore(&ioapic_lock, flags);
2090 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2091 printk("could not set ID!\n");
2092 else
2093 apic_printk(APIC_VERBOSE, " ok.\n");
2094 }
2095}
2096#endif
2097
2098int no_timer_check __initdata;
2099
2100static int __init notimercheck(char *s)
2101{
2102 no_timer_check = 1;
2103 return 1;
2104}
2105__setup("no_timer_check", notimercheck);
2106
2107/*
2108 * There is a nasty bug in some older SMP boards, their mptable lies
2109 * about the timer IRQ. We do the following to work around the situation:
2110 *
2111 * - timer IRQ defaults to IO-APIC IRQ
2112 * - if this function detects that timer IRQs are defunct, then we fall
2113 * back to ISA timer IRQs
2114 */
2115static int __init timer_irq_works(void)
2116{
2117 unsigned long t1 = jiffies;
2118 unsigned long flags;
2119
2120 if (no_timer_check)
2121 return 1;
2122
2123 local_save_flags(flags);
2124 local_irq_enable();
2125 /* Let ten ticks pass... */
2126 mdelay((10 * 1000) / HZ);
2127 local_irq_restore(flags);
2128
2129 /*
2130 * Expect a few ticks at least, to be sure some possible
2131 * glue logic does not lock up after one or two first
2132 * ticks in a non-ExtINT mode. Also the local APIC
2133 * might have cached one ExtINT interrupt. Finally, at
2134 * least one tick may be lost due to delays.
2135 */
2136
2137 /* jiffies wrap? */
2138 if (time_after(jiffies, t1 + 4))
2139 return 1;
2140 return 0;
2141}
2142
2143/*
2144 * In the SMP+IOAPIC case it might happen that there are an unspecified
2145 * number of pending IRQ events unhandled. These cases are very rare,
2146 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2147 * better to do it this way as thus we do not have to be aware of
2148 * 'pending' interrupts in the IRQ path, except at this point.
2149 */
2150/*
2151 * Edge triggered needs to resend any interrupt
2152 * that was delayed but this is now handled in the device
2153 * independent code.
2154 */
2155
2156/*
2157 * Starting up a edge-triggered IO-APIC interrupt is
2158 * nasty - we need to make sure that we get the edge.
2159 * If it is already asserted for some reason, we need
2160 * return 1 to indicate that is was pending.
2161 *
2162 * This is not complete - we should be able to fake
2163 * an edge even if it isn't on the 8259A...
2164 */
2165
2166static unsigned int startup_ioapic_irq(unsigned int irq)
2167{
2168 int was_pending = 0;
2169 unsigned long flags;
2170
2171 spin_lock_irqsave(&ioapic_lock, flags);
2172 if (irq < 16) {
2173 disable_8259A_irq(irq);
2174 if (i8259A_irq_pending(irq))
2175 was_pending = 1;
2176 }
2177 __unmask_IO_APIC_irq(irq);
2178 spin_unlock_irqrestore(&ioapic_lock, flags);
2179
2180 return was_pending;
2181}
2182
2183#ifdef CONFIG_X86_64
2184static int ioapic_retrigger_irq(unsigned int irq)
2185{
2186
2187 struct irq_cfg *cfg = irq_cfg(irq);
2188 unsigned long flags;
2189
2190 spin_lock_irqsave(&vector_lock, flags);
2191 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2192 spin_unlock_irqrestore(&vector_lock, flags);
2193
2194 return 1;
2195}
2196#else
2197static int ioapic_retrigger_irq(unsigned int irq)
2198{
2199 send_IPI_self(irq_cfg(irq)->vector);
2200
2201 return 1;
2202}
2203#endif
2204
2205/*
2206 * Level and edge triggered IO-APIC interrupts need different handling,
2207 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2208 * handled with the level-triggered descriptor, but that one has slightly
2209 * more overhead. Level-triggered interrupts cannot be handled with the
2210 * edge-triggered handler, without risking IRQ storms and other ugly
2211 * races.
2212 */
2213
2214#ifdef CONFIG_SMP
2215
2216#ifdef CONFIG_INTR_REMAP
2217static void ir_irq_migration(struct work_struct *work);
2218
2219static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2220
2221/*
2222 * Migrate the IO-APIC irq in the presence of intr-remapping.
2223 *
2224 * For edge triggered, irq migration is a simple atomic update(of vector
2225 * and cpu destination) of IRTE and flush the hardware cache.
2226 *
2227 * For level triggered, we need to modify the io-apic RTE aswell with the update
2228 * vector information, along with modifying IRTE with vector and destination.
2229 * So irq migration for level triggered is little bit more complex compared to
2230 * edge triggered migration. But the good news is, we use the same algorithm
2231 * for level triggered migration as we have today, only difference being,
2232 * we now initiate the irq migration from process context instead of the
2233 * interrupt context.
2234 *
2235 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2236 * suppression) to the IO-APIC, level triggered irq migration will also be
2237 * as simple as edge triggered migration and we can do the irq migration
2238 * with a simple atomic update to IO-APIC RTE.
2239 */
2240static void migrate_ioapic_irq(int irq, cpumask_t mask)
2241{
2242 struct irq_cfg *cfg;
2243 struct irq_desc *desc;
2244 cpumask_t tmp, cleanup_mask;
2245 struct irte irte;
2246 int modify_ioapic_rte;
2247 unsigned int dest;
2248 unsigned long flags;
2249
2250 cpus_and(tmp, mask, cpu_online_map);
2251 if (cpus_empty(tmp))
2252 return;
2253
2254 if (get_irte(irq, &irte))
2255 return;
2256
2257 if (assign_irq_vector(irq, mask))
2258 return;
2259
2260 cfg = irq_cfg(irq);
2261 cpus_and(tmp, cfg->domain, mask);
2262 dest = cpu_mask_to_apicid(tmp);
2263
2264 desc = irq_to_desc(irq);
2265 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2266 if (modify_ioapic_rte) {
2267 spin_lock_irqsave(&ioapic_lock, flags);
2268 __target_IO_APIC_irq(irq, dest, cfg->vector);
2269 spin_unlock_irqrestore(&ioapic_lock, flags);
2270 }
2271
2272 irte.vector = cfg->vector;
2273 irte.dest_id = IRTE_DEST(dest);
2274
2275 /*
2276 * Modified the IRTE and flushes the Interrupt entry cache.
2277 */
2278 modify_irte(irq, &irte);
2279
2280 if (cfg->move_in_progress) {
2281 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2282 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2283 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2284 cfg->move_in_progress = 0;
2285 }
2286
2287 desc->affinity = mask;
2288}
2289
2290static int migrate_irq_remapped_level(int irq)
2291{
2292 int ret = -1;
2293 struct irq_desc *desc = irq_to_desc(irq);
2294
2295 mask_IO_APIC_irq(irq);
2296
2297 if (io_apic_level_ack_pending(irq)) {
2298 /*
2299 * Interrupt in progress. Migrating irq now will change the
2300 * vector information in the IO-APIC RTE and that will confuse
2301 * the EOI broadcast performed by cpu.
2302 * So, delay the irq migration to the next instance.
2303 */
2304 schedule_delayed_work(&ir_migration_work, 1);
2305 goto unmask;
2306 }
2307
2308 /* everthing is clear. we have right of way */
2309 migrate_ioapic_irq(irq, desc->pending_mask);
2310
2311 ret = 0;
2312 desc->status &= ~IRQ_MOVE_PENDING;
2313 cpus_clear(desc->pending_mask);
2314
2315unmask:
2316 unmask_IO_APIC_irq(irq);
2317 return ret;
2318}
2319
2320static void ir_irq_migration(struct work_struct *work)
2321{
2322 unsigned int irq;
2323 struct irq_desc *desc;
2324
2325 for_each_irq_desc(irq, desc) {
2326 if (desc->status & IRQ_MOVE_PENDING) {
2327 unsigned long flags;
2328
2329 spin_lock_irqsave(&desc->lock, flags);
2330 if (!desc->chip->set_affinity ||
2331 !(desc->status & IRQ_MOVE_PENDING)) {
2332 desc->status &= ~IRQ_MOVE_PENDING;
2333 spin_unlock_irqrestore(&desc->lock, flags);
2334 continue;
2335 }
2336
2337 desc->chip->set_affinity(irq, desc->pending_mask);
2338 spin_unlock_irqrestore(&desc->lock, flags);
2339 }
2340 }
2341}
2342
2343/*
2344 * Migrates the IRQ destination in the process context.
2345 */
2346static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2347{
2348 struct irq_desc *desc = irq_to_desc(irq);
2349
2350 if (desc->status & IRQ_LEVEL) {
2351 desc->status |= IRQ_MOVE_PENDING;
2352 desc->pending_mask = mask;
2353 migrate_irq_remapped_level(irq);
2354 return;
2355 }
2356
2357 migrate_ioapic_irq(irq, mask);
2358}
2359#endif
2360
2361asmlinkage void smp_irq_move_cleanup_interrupt(void)
2362{
2363 unsigned vector, me;
2364 ack_APIC_irq();
2365#ifdef CONFIG_X86_64
2366 exit_idle();
2367#endif
2368 irq_enter();
2369
2370 me = smp_processor_id();
2371 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2372 unsigned int irq;
2373 struct irq_desc *desc;
2374 struct irq_cfg *cfg;
2375 irq = __get_cpu_var(vector_irq)[vector];
2376
2377 desc = irq_to_desc(irq);
2378 if (!desc)
2379 continue;
2380
2381 cfg = irq_cfg(irq);
2382 spin_lock(&desc->lock);
2383 if (!cfg->move_cleanup_count)
2384 goto unlock;
2385
2386 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2387 goto unlock;
2388
2389 __get_cpu_var(vector_irq)[vector] = -1;
2390 cfg->move_cleanup_count--;
2391unlock:
2392 spin_unlock(&desc->lock);
2393 }
2394
2395 irq_exit();
2396}
2397
2398static void irq_complete_move(unsigned int irq)
2399{
2400 struct irq_cfg *cfg = irq_cfg(irq);
2401 unsigned vector, me;
2402
2403 if (likely(!cfg->move_in_progress))
2404 return;
2405
2406 vector = ~get_irq_regs()->orig_ax;
2407 me = smp_processor_id();
2408 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2409 cpumask_t cleanup_mask;
2410
2411 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2412 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2413 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2414 cfg->move_in_progress = 0;
2415 }
2416}
2417#else
2418static inline void irq_complete_move(unsigned int irq) {}
2419#endif
2420#ifdef CONFIG_INTR_REMAP
2421static void ack_x2apic_level(unsigned int irq)
2422{
2423 ack_x2APIC_irq();
2424}
2425
2426static void ack_x2apic_edge(unsigned int irq)
2427{
2428 ack_x2APIC_irq();
2429}
2430#endif
2431
2432static void ack_apic_edge(unsigned int irq)
2433{
2434 irq_complete_move(irq);
2435 move_native_irq(irq);
2436 ack_APIC_irq();
2437}
2438
2439#ifdef CONFIG_X86_64
2440static void ack_apic_level(unsigned int irq)
2441{
2442 int do_unmask_irq = 0;
2443
2444 irq_complete_move(irq);
2445#ifdef CONFIG_GENERIC_PENDING_IRQ
2446 /* If we are moving the irq we need to mask it */
2447 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2448 do_unmask_irq = 1;
2449 mask_IO_APIC_irq(irq);
2450 }
2451#endif
2452
2453 /*
2454 * We must acknowledge the irq before we move it or the acknowledge will
2455 * not propagate properly.
2456 */
2457 ack_APIC_irq();
2458
2459 /* Now we can move and renable the irq */
2460 if (unlikely(do_unmask_irq)) {
2461 /* Only migrate the irq if the ack has been received.
2462 *
2463 * On rare occasions the broadcast level triggered ack gets
2464 * delayed going to ioapics, and if we reprogram the
2465 * vector while Remote IRR is still set the irq will never
2466 * fire again.
2467 *
2468 * To prevent this scenario we read the Remote IRR bit
2469 * of the ioapic. This has two effects.
2470 * - On any sane system the read of the ioapic will
2471 * flush writes (and acks) going to the ioapic from
2472 * this cpu.
2473 * - We get to see if the ACK has actually been delivered.
2474 *
2475 * Based on failed experiments of reprogramming the
2476 * ioapic entry from outside of irq context starting
2477 * with masking the ioapic entry and then polling until
2478 * Remote IRR was clear before reprogramming the
2479 * ioapic I don't trust the Remote IRR bit to be
2480 * completey accurate.
2481 *
2482 * However there appears to be no other way to plug
2483 * this race, so if the Remote IRR bit is not
2484 * accurate and is causing problems then it is a hardware bug
2485 * and you can go talk to the chipset vendor about it.
2486 */
2487 if (!io_apic_level_ack_pending(irq))
2488 move_masked_irq(irq);
2489 unmask_IO_APIC_irq(irq);
2490 }
2491}
2492#else
2493atomic_t irq_mis_count;
2494static void ack_apic_level(unsigned int irq)
2495{
2496 unsigned long v;
2497 int i;
2498
2499 irq_complete_move(irq);
2500 move_native_irq(irq);
2501 /*
2502 * It appears there is an erratum which affects at least version 0x11
2503 * of I/O APIC (that's the 82093AA and cores integrated into various
2504 * chipsets). Under certain conditions a level-triggered interrupt is
2505 * erroneously delivered as edge-triggered one but the respective IRR
2506 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2507 * message but it will never arrive and further interrupts are blocked
2508 * from the source. The exact reason is so far unknown, but the
2509 * phenomenon was observed when two consecutive interrupt requests
2510 * from a given source get delivered to the same CPU and the source is
2511 * temporarily disabled in between.
2512 *
2513 * A workaround is to simulate an EOI message manually. We achieve it
2514 * by setting the trigger mode to edge and then to level when the edge
2515 * trigger mode gets detected in the TMR of a local APIC for a
2516 * level-triggered interrupt. We mask the source for the time of the
2517 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2518 * The idea is from Manfred Spraul. --macro
2519 */
2520 i = irq_cfg(irq)->vector;
2521
2522 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2523
2524 ack_APIC_irq();
2525
2526 if (!(v & (1 << (i & 0x1f)))) {
2527 atomic_inc(&irq_mis_count);
2528 spin_lock(&ioapic_lock);
2529 __mask_and_edge_IO_APIC_irq(irq);
2530 __unmask_and_level_IO_APIC_irq(irq);
2531 spin_unlock(&ioapic_lock);
2532 }
2533}
2534#endif
2535
2536static struct irq_chip ioapic_chip __read_mostly = {
2537 .name = "IO-APIC",
2538 .startup = startup_ioapic_irq,
2539 .mask = mask_IO_APIC_irq,
2540 .unmask = unmask_IO_APIC_irq,
2541 .ack = ack_apic_edge,
2542 .eoi = ack_apic_level,
2543#ifdef CONFIG_SMP
2544 .set_affinity = set_ioapic_affinity_irq,
2545#endif
2546 .retrigger = ioapic_retrigger_irq,
2547};
2548
2549#ifdef CONFIG_INTR_REMAP
2550static struct irq_chip ir_ioapic_chip __read_mostly = {
2551 .name = "IR-IO-APIC",
2552 .startup = startup_ioapic_irq,
2553 .mask = mask_IO_APIC_irq,
2554 .unmask = unmask_IO_APIC_irq,
2555 .ack = ack_x2apic_edge,
2556 .eoi = ack_x2apic_level,
2557#ifdef CONFIG_SMP
2558 .set_affinity = set_ir_ioapic_affinity_irq,
2559#endif
2560 .retrigger = ioapic_retrigger_irq,
2561};
2562#endif
2563
2564static inline void init_IO_APIC_traps(void)
2565{
2566 int irq;
2567 struct irq_desc *desc;
2568 struct irq_cfg *cfg;
2569
2570 /*
2571 * NOTE! The local APIC isn't very good at handling
2572 * multiple interrupts at the same interrupt level.
2573 * As the interrupt level is determined by taking the
2574 * vector number and shifting that right by 4, we
2575 * want to spread these out a bit so that they don't
2576 * all fall in the same interrupt level.
2577 *
2578 * Also, we've got to be careful not to trash gate
2579 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2580 */
2581 for_each_irq_cfg(cfg) {
2582 irq = cfg->irq;
2583 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2584 /*
2585 * Hmm.. We don't have an entry for this,
2586 * so default to an old-fashioned 8259
2587 * interrupt if we can..
2588 */
2589 if (irq < 16)
2590 make_8259A_irq(irq);
2591 else {
2592 desc = irq_to_desc(irq);
2593 /* Strange. Oh, well.. */
2594 desc->chip = &no_irq_chip;
2595 }
2596 }
2597 }
2598}
2599
2600/*
2601 * The local APIC irq-chip implementation:
2602 */
2603
2604static void mask_lapic_irq(unsigned int irq)
2605{
2606 unsigned long v;
2607
2608 v = apic_read(APIC_LVT0);
2609 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2610}
2611
2612static void unmask_lapic_irq(unsigned int irq)
2613{
2614 unsigned long v;
2615
2616 v = apic_read(APIC_LVT0);
2617 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2618}
2619
2620static void ack_lapic_irq (unsigned int irq)
2621{
2622 ack_APIC_irq();
2623}
2624
2625static struct irq_chip lapic_chip __read_mostly = {
2626 .name = "local-APIC",
2627 .mask = mask_lapic_irq,
2628 .unmask = unmask_lapic_irq,
2629 .ack = ack_lapic_irq,
2630};
2631
2632static void lapic_register_intr(int irq)
2633{
2634 struct irq_desc *desc;
2635
2636 desc = irq_to_desc(irq);
2637 desc->status &= ~IRQ_LEVEL;
2638 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2639 "edge");
2640}
2641
2642static void __init setup_nmi(void)
2643{
2644 /*
2645 * Dirty trick to enable the NMI watchdog ...
2646 * We put the 8259A master into AEOI mode and
2647 * unmask on all local APICs LVT0 as NMI.
2648 *
2649 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2650 * is from Maciej W. Rozycki - so we do not have to EOI from
2651 * the NMI handler or the timer interrupt.
2652 */
2653 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2654
2655 enable_NMI_through_LVT0();
2656
2657 apic_printk(APIC_VERBOSE, " done.\n");
2658}
2659
2660/*
2661 * This looks a bit hackish but it's about the only one way of sending
2662 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2663 * not support the ExtINT mode, unfortunately. We need to send these
2664 * cycles as some i82489DX-based boards have glue logic that keeps the
2665 * 8259A interrupt line asserted until INTA. --macro
2666 */
2667static inline void __init unlock_ExtINT_logic(void)
2668{
2669 int apic, pin, i;
2670 struct IO_APIC_route_entry entry0, entry1;
2671 unsigned char save_control, save_freq_select;
2672
2673 pin = find_isa_irq_pin(8, mp_INT);
2674 if (pin == -1) {
2675 WARN_ON_ONCE(1);
2676 return;
2677 }
2678 apic = find_isa_irq_apic(8, mp_INT);
2679 if (apic == -1) {
2680 WARN_ON_ONCE(1);
2681 return;
2682 }
2683
2684 entry0 = ioapic_read_entry(apic, pin);
2685 clear_IO_APIC_pin(apic, pin);
2686
2687 memset(&entry1, 0, sizeof(entry1));
2688
2689 entry1.dest_mode = 0; /* physical delivery */
2690 entry1.mask = 0; /* unmask IRQ now */
2691 entry1.dest = hard_smp_processor_id();
2692 entry1.delivery_mode = dest_ExtINT;
2693 entry1.polarity = entry0.polarity;
2694 entry1.trigger = 0;
2695 entry1.vector = 0;
2696
2697 ioapic_write_entry(apic, pin, entry1);
2698
2699 save_control = CMOS_READ(RTC_CONTROL);
2700 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2701 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2702 RTC_FREQ_SELECT);
2703 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2704
2705 i = 100;
2706 while (i-- > 0) {
2707 mdelay(10);
2708 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2709 i -= 10;
2710 }
2711
2712 CMOS_WRITE(save_control, RTC_CONTROL);
2713 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2714 clear_IO_APIC_pin(apic, pin);
2715
2716 ioapic_write_entry(apic, pin, entry0);
2717}
2718
2719static int disable_timer_pin_1 __initdata;
2720/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2721static int __init disable_timer_pin_setup(char *arg)
2722{
2723 disable_timer_pin_1 = 1;
2724 return 0;
2725}
2726early_param("disable_timer_pin_1", disable_timer_pin_setup);
2727
2728int timer_through_8259 __initdata;
2729
2730/*
2731 * This code may look a bit paranoid, but it's supposed to cooperate with
2732 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2733 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2734 * fanatically on his truly buggy board.
2735 *
2736 * FIXME: really need to revamp this for all platforms.
2737 */
2738static inline void __init check_timer(void)
2739{
2740 struct irq_cfg *cfg = irq_cfg(0);
2741 int apic1, pin1, apic2, pin2;
2742 unsigned long flags;
2743 unsigned int ver;
2744 int no_pin1 = 0;
2745
2746 local_irq_save(flags);
2747
2748 ver = apic_read(APIC_LVR);
2749 ver = GET_APIC_VERSION(ver);
2750
2751 /*
2752 * get/set the timer IRQ vector:
2753 */
2754 disable_8259A_irq(0);
2755 assign_irq_vector(0, TARGET_CPUS);
2756
2757 /*
2758 * As IRQ0 is to be enabled in the 8259A, the virtual
2759 * wire has to be disabled in the local APIC. Also
2760 * timer interrupts need to be acknowledged manually in
2761 * the 8259A for the i82489DX when using the NMI
2762 * watchdog as that APIC treats NMIs as level-triggered.
2763 * The AEOI mode will finish them in the 8259A
2764 * automatically.
2765 */
2766 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2767 init_8259A(1);
2768#ifdef CONFIG_X86_32
2769 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2770#endif
2771
2772 pin1 = find_isa_irq_pin(0, mp_INT);
2773 apic1 = find_isa_irq_apic(0, mp_INT);
2774 pin2 = ioapic_i8259.pin;
2775 apic2 = ioapic_i8259.apic;
2776
2777 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2778 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2779 cfg->vector, apic1, pin1, apic2, pin2);
2780
2781 /*
2782 * Some BIOS writers are clueless and report the ExtINTA
2783 * I/O APIC input from the cascaded 8259A as the timer
2784 * interrupt input. So just in case, if only one pin
2785 * was found above, try it both directly and through the
2786 * 8259A.
2787 */
2788 if (pin1 == -1) {
2789#ifdef CONFIG_INTR_REMAP
2790 if (intr_remapping_enabled)
2791 panic("BIOS bug: timer not connected to IO-APIC");
2792#endif
2793 pin1 = pin2;
2794 apic1 = apic2;
2795 no_pin1 = 1;
2796 } else if (pin2 == -1) {
2797 pin2 = pin1;
2798 apic2 = apic1;
2799 }
2800
2801 if (pin1 != -1) {
2802 /*
2803 * Ok, does IRQ0 through the IOAPIC work?
2804 */
2805 if (no_pin1) {
2806 add_pin_to_irq(0, apic1, pin1);
2807 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2808 }
2809 unmask_IO_APIC_irq(0);
2810 if (timer_irq_works()) {
2811 if (nmi_watchdog == NMI_IO_APIC) {
2812 setup_nmi();
2813 enable_8259A_irq(0);
2814 }
2815 if (disable_timer_pin_1 > 0)
2816 clear_IO_APIC_pin(0, pin1);
2817 goto out;
2818 }
2819#ifdef CONFIG_INTR_REMAP
2820 if (intr_remapping_enabled)
2821 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2822#endif
2823 clear_IO_APIC_pin(apic1, pin1);
2824 if (!no_pin1)
2825 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2826 "8254 timer not connected to IO-APIC\n");
2827
2828 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2829 "(IRQ0) through the 8259A ...\n");
2830 apic_printk(APIC_QUIET, KERN_INFO
2831 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2832 /*
2833 * legacy devices should be connected to IO APIC #0
2834 */
2835 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2836 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2837 unmask_IO_APIC_irq(0);
2838 enable_8259A_irq(0);
2839 if (timer_irq_works()) {
2840 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2841 timer_through_8259 = 1;
2842 if (nmi_watchdog == NMI_IO_APIC) {
2843 disable_8259A_irq(0);
2844 setup_nmi();
2845 enable_8259A_irq(0);
2846 }
2847 goto out;
2848 }
2849 /*
2850 * Cleanup, just in case ...
2851 */
2852 disable_8259A_irq(0);
2853 clear_IO_APIC_pin(apic2, pin2);
2854 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2855 }
2856
2857 if (nmi_watchdog == NMI_IO_APIC) {
2858 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2859 "through the IO-APIC - disabling NMI Watchdog!\n");
2860 nmi_watchdog = NMI_NONE;
2861 }
2862#ifdef CONFIG_X86_32
2863 timer_ack = 0;
2864#endif
2865
2866 apic_printk(APIC_QUIET, KERN_INFO
2867 "...trying to set up timer as Virtual Wire IRQ...\n");
2868
2869 lapic_register_intr(0);
2870 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2871 enable_8259A_irq(0);
2872
2873 if (timer_irq_works()) {
2874 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2875 goto out;
2876 }
2877 disable_8259A_irq(0);
2878 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2879 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2880
2881 apic_printk(APIC_QUIET, KERN_INFO
2882 "...trying to set up timer as ExtINT IRQ...\n");
2883
2884 init_8259A(0);
2885 make_8259A_irq(0);
2886 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2887
2888 unlock_ExtINT_logic();
2889
2890 if (timer_irq_works()) {
2891 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2892 goto out;
2893 }
2894 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2895 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2896 "report. Then try booting with the 'noapic' option.\n");
2897out:
2898 local_irq_restore(flags);
2899}
2900
2901/*
2902 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2903 * to devices. However there may be an I/O APIC pin available for
2904 * this interrupt regardless. The pin may be left unconnected, but
2905 * typically it will be reused as an ExtINT cascade interrupt for
2906 * the master 8259A. In the MPS case such a pin will normally be
2907 * reported as an ExtINT interrupt in the MP table. With ACPI
2908 * there is no provision for ExtINT interrupts, and in the absence
2909 * of an override it would be treated as an ordinary ISA I/O APIC
2910 * interrupt, that is edge-triggered and unmasked by default. We
2911 * used to do this, but it caused problems on some systems because
2912 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2913 * the same ExtINT cascade interrupt to drive the local APIC of the
2914 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2915 * the I/O APIC in all cases now. No actual device should request
2916 * it anyway. --macro
2917 */
2918#define PIC_IRQS (1 << PIC_CASCADE_IR)
2919
2920void __init setup_IO_APIC(void)
2921{
2922
2923#ifdef CONFIG_X86_32
2924 enable_IO_APIC();
2925#else
2926 /*
2927 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2928 */
2929#endif
2930
2931 io_apic_irqs = ~PIC_IRQS;
2932
2933 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2934 /*
2935 * Set up IO-APIC IRQ routing.
2936 */
2937#ifdef CONFIG_X86_32
2938 if (!acpi_ioapic)
2939 setup_ioapic_ids_from_mpc();
2940#endif
2941 sync_Arb_IDs();
2942 setup_IO_APIC_irqs();
2943 init_IO_APIC_traps();
2944 check_timer();
2945}
2946
2947/*
2948 * Called after all the initialization is done. If we didnt find any
2949 * APIC bugs then we can allow the modify fast path
2950 */
2951
2952static int __init io_apic_bug_finalize(void)
2953{
2954 if (sis_apic_bug == -1)
2955 sis_apic_bug = 0;
2956 return 0;
2957}
2958
2959late_initcall(io_apic_bug_finalize);
2960
2961struct sysfs_ioapic_data {
2962 struct sys_device dev;
2963 struct IO_APIC_route_entry entry[0];
2964};
2965static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2966
2967static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2968{
2969 struct IO_APIC_route_entry *entry;
2970 struct sysfs_ioapic_data *data;
2971 int i;
2972
2973 data = container_of(dev, struct sysfs_ioapic_data, dev);
2974 entry = data->entry;
2975 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2976 *entry = ioapic_read_entry(dev->id, i);
2977
2978 return 0;
2979}
2980
2981static int ioapic_resume(struct sys_device *dev)
2982{
2983 struct IO_APIC_route_entry *entry;
2984 struct sysfs_ioapic_data *data;
2985 unsigned long flags;
2986 union IO_APIC_reg_00 reg_00;
2987 int i;
2988
2989 data = container_of(dev, struct sysfs_ioapic_data, dev);
2990 entry = data->entry;
2991
2992 spin_lock_irqsave(&ioapic_lock, flags);
2993 reg_00.raw = io_apic_read(dev->id, 0);
2994 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2995 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2996 io_apic_write(dev->id, 0, reg_00.raw);
2997 }
2998 spin_unlock_irqrestore(&ioapic_lock, flags);
2999 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3000 ioapic_write_entry(dev->id, i, entry[i]);
3001
3002 return 0;
3003}
3004
3005static struct sysdev_class ioapic_sysdev_class = {
3006 .name = "ioapic",
3007 .suspend = ioapic_suspend,
3008 .resume = ioapic_resume,
3009};
3010
3011static int __init ioapic_init_sysfs(void)
3012{
3013 struct sys_device * dev;
3014 int i, size, error;
3015
3016 error = sysdev_class_register(&ioapic_sysdev_class);
3017 if (error)
3018 return error;
3019
3020 for (i = 0; i < nr_ioapics; i++ ) {
3021 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3022 * sizeof(struct IO_APIC_route_entry);
3023 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3024 if (!mp_ioapic_data[i]) {
3025 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3026 continue;
3027 }
3028 dev = &mp_ioapic_data[i]->dev;
3029 dev->id = i;
3030 dev->cls = &ioapic_sysdev_class;
3031 error = sysdev_register(dev);
3032 if (error) {
3033 kfree(mp_ioapic_data[i]);
3034 mp_ioapic_data[i] = NULL;
3035 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3036 continue;
3037 }
3038 }
3039
3040 return 0;
3041}
3042
3043device_initcall(ioapic_init_sysfs);
3044
3045/*
3046 * Dynamic irq allocate and deallocation
3047 */
3048unsigned int create_irq_nr(unsigned int irq_want)
3049{
3050 /* Allocate an unused irq */
3051 unsigned int irq;
3052 unsigned int new;
3053 unsigned long flags;
3054 struct irq_cfg *cfg_new;
3055
3056#ifndef CONFIG_HAVE_SPARSE_IRQ
3057 irq_want = nr_irqs - 1;
3058#endif
3059
3060 irq = 0;
3061 spin_lock_irqsave(&vector_lock, flags);
3062 for (new = irq_want; new > 0; new--) {
3063 if (platform_legacy_irq(new))
3064 continue;
3065 cfg_new = irq_cfg(new);
3066 if (cfg_new && cfg_new->vector != 0)
3067 continue;
3068 /* check if need to create one */
3069 if (!cfg_new)
3070 cfg_new = irq_cfg_alloc(new);
3071 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
3072 irq = new;
3073 break;
3074 }
3075 spin_unlock_irqrestore(&vector_lock, flags);
3076
3077 if (irq > 0) {
3078 dynamic_irq_init(irq);
3079 }
3080 return irq;
3081}
3082
3083int create_irq(void)
3084{
3085 int irq;
3086
3087 irq = create_irq_nr(nr_irqs - 1);
3088
3089 if (irq == 0)
3090 irq = -1;
3091
3092 return irq;
3093}
3094
3095void destroy_irq(unsigned int irq)
3096{
3097 unsigned long flags;
3098
3099 dynamic_irq_cleanup(irq);
3100
3101#ifdef CONFIG_INTR_REMAP
3102 free_irte(irq);
3103#endif
3104 spin_lock_irqsave(&vector_lock, flags);
3105 __clear_irq_vector(irq);
3106 spin_unlock_irqrestore(&vector_lock, flags);
3107}
3108
3109/*
3110 * MSI message composition
3111 */
3112#ifdef CONFIG_PCI_MSI
3113static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3114{
3115 struct irq_cfg *cfg;
3116 int err;
3117 unsigned dest;
3118 cpumask_t tmp;
3119
3120 tmp = TARGET_CPUS;
3121 err = assign_irq_vector(irq, tmp);
3122 if (err)
3123 return err;
3124
3125 cfg = irq_cfg(irq);
3126 cpus_and(tmp, cfg->domain, tmp);
3127 dest = cpu_mask_to_apicid(tmp);
3128
3129#ifdef CONFIG_INTR_REMAP
3130 if (irq_remapped(irq)) {
3131 struct irte irte;
3132 int ir_index;
3133 u16 sub_handle;
3134
3135 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3136 BUG_ON(ir_index == -1);
3137
3138 memset (&irte, 0, sizeof(irte));
3139
3140 irte.present = 1;
3141 irte.dst_mode = INT_DEST_MODE;
3142 irte.trigger_mode = 0; /* edge */
3143 irte.dlvry_mode = INT_DELIVERY_MODE;
3144 irte.vector = cfg->vector;
3145 irte.dest_id = IRTE_DEST(dest);
3146
3147 modify_irte(irq, &irte);
3148
3149 msg->address_hi = MSI_ADDR_BASE_HI;
3150 msg->data = sub_handle;
3151 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3152 MSI_ADDR_IR_SHV |
3153 MSI_ADDR_IR_INDEX1(ir_index) |
3154 MSI_ADDR_IR_INDEX2(ir_index);
3155 } else
3156#endif
3157 {
3158 msg->address_hi = MSI_ADDR_BASE_HI;
3159 msg->address_lo =
3160 MSI_ADDR_BASE_LO |
3161 ((INT_DEST_MODE == 0) ?
3162 MSI_ADDR_DEST_MODE_PHYSICAL:
3163 MSI_ADDR_DEST_MODE_LOGICAL) |
3164 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3165 MSI_ADDR_REDIRECTION_CPU:
3166 MSI_ADDR_REDIRECTION_LOWPRI) |
3167 MSI_ADDR_DEST_ID(dest);
3168
3169 msg->data =
3170 MSI_DATA_TRIGGER_EDGE |
3171 MSI_DATA_LEVEL_ASSERT |
3172 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3173 MSI_DATA_DELIVERY_FIXED:
3174 MSI_DATA_DELIVERY_LOWPRI) |
3175 MSI_DATA_VECTOR(cfg->vector);
3176 }
3177 return err;
3178}
3179
3180#ifdef CONFIG_SMP
3181static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3182{
3183 struct irq_cfg *cfg;
3184 struct msi_msg msg;
3185 unsigned int dest;
3186 cpumask_t tmp;
3187 struct irq_desc *desc;
3188
3189 cpus_and(tmp, mask, cpu_online_map);
3190 if (cpus_empty(tmp))
3191 return;
3192
3193 if (assign_irq_vector(irq, mask))
3194 return;
3195
3196 cfg = irq_cfg(irq);
3197 cpus_and(tmp, cfg->domain, mask);
3198 dest = cpu_mask_to_apicid(tmp);
3199
3200 read_msi_msg(irq, &msg);
3201
3202 msg.data &= ~MSI_DATA_VECTOR_MASK;
3203 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3204 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3205 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3206
3207 write_msi_msg(irq, &msg);
3208 desc = irq_to_desc(irq);
3209 desc->affinity = mask;
3210}
3211
3212#ifdef CONFIG_INTR_REMAP
3213/*
3214 * Migrate the MSI irq to another cpumask. This migration is
3215 * done in the process context using interrupt-remapping hardware.
3216 */
3217static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3218{
3219 struct irq_cfg *cfg;
3220 unsigned int dest;
3221 cpumask_t tmp, cleanup_mask;
3222 struct irte irte;
3223 struct irq_desc *desc;
3224
3225 cpus_and(tmp, mask, cpu_online_map);
3226 if (cpus_empty(tmp))
3227 return;
3228
3229 if (get_irte(irq, &irte))
3230 return;
3231
3232 if (assign_irq_vector(irq, mask))
3233 return;
3234
3235 cfg = irq_cfg(irq);
3236 cpus_and(tmp, cfg->domain, mask);
3237 dest = cpu_mask_to_apicid(tmp);
3238
3239 irte.vector = cfg->vector;
3240 irte.dest_id = IRTE_DEST(dest);
3241
3242 /*
3243 * atomically update the IRTE with the new destination and vector.
3244 */
3245 modify_irte(irq, &irte);
3246
3247 /*
3248 * After this point, all the interrupts will start arriving
3249 * at the new destination. So, time to cleanup the previous
3250 * vector allocation.
3251 */
3252 if (cfg->move_in_progress) {
3253 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3254 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3255 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3256 cfg->move_in_progress = 0;
3257 }
3258
3259 desc = irq_to_desc(irq);
3260 desc->affinity = mask;
3261}
3262#endif
3263#endif /* CONFIG_SMP */
3264
3265/*
3266 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3267 * which implement the MSI or MSI-X Capability Structure.
3268 */
3269static struct irq_chip msi_chip = {
3270 .name = "PCI-MSI",
3271 .unmask = unmask_msi_irq,
3272 .mask = mask_msi_irq,
3273 .ack = ack_apic_edge,
3274#ifdef CONFIG_SMP
3275 .set_affinity = set_msi_irq_affinity,
3276#endif
3277 .retrigger = ioapic_retrigger_irq,
3278};
3279
3280#ifdef CONFIG_INTR_REMAP
3281static struct irq_chip msi_ir_chip = {
3282 .name = "IR-PCI-MSI",
3283 .unmask = unmask_msi_irq,
3284 .mask = mask_msi_irq,
3285 .ack = ack_x2apic_edge,
3286#ifdef CONFIG_SMP
3287 .set_affinity = ir_set_msi_irq_affinity,
3288#endif
3289 .retrigger = ioapic_retrigger_irq,
3290};
3291
3292/*
3293 * Map the PCI dev to the corresponding remapping hardware unit
3294 * and allocate 'nvec' consecutive interrupt-remapping table entries
3295 * in it.
3296 */
3297static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3298{
3299 struct intel_iommu *iommu;
3300 int index;
3301
3302 iommu = map_dev_to_ir(dev);
3303 if (!iommu) {
3304 printk(KERN_ERR
3305 "Unable to map PCI %s to iommu\n", pci_name(dev));
3306 return -ENOENT;
3307 }
3308
3309 index = alloc_irte(iommu, irq, nvec);
3310 if (index < 0) {
3311 printk(KERN_ERR
3312 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3313 pci_name(dev));
3314 return -ENOSPC;
3315 }
3316 return index;
3317}
3318#endif
3319
3320static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3321{
3322 int ret;
3323 struct msi_msg msg;
3324
3325 ret = msi_compose_msg(dev, irq, &msg);
3326 if (ret < 0)
3327 return ret;
3328
3329 set_irq_msi(irq, desc);
3330 write_msi_msg(irq, &msg);
3331
3332#ifdef CONFIG_INTR_REMAP
3333 if (irq_remapped(irq)) {
3334 struct irq_desc *desc = irq_to_desc(irq);
3335 /*
3336 * irq migration in process context
3337 */
3338 desc->status |= IRQ_MOVE_PCNTXT;
3339 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3340 } else
3341#endif
3342 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3343
3344 return 0;
3345}
3346
3347static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3348{
3349 unsigned int irq;
3350
3351 irq = dev->bus->number;
3352 irq <<= 8;
3353 irq |= dev->devfn;
3354 irq <<= 12;
3355
3356 return irq;
3357}
3358
3359int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3360{
3361 unsigned int irq;
3362 int ret;
3363 unsigned int irq_want;
3364
3365 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3366
3367 irq = create_irq_nr(irq_want);
3368 if (irq == 0)
3369 return -1;
3370
3371#ifdef CONFIG_INTR_REMAP
3372 if (!intr_remapping_enabled)
3373 goto no_ir;
3374
3375 ret = msi_alloc_irte(dev, irq, 1);
3376 if (ret < 0)
3377 goto error;
3378no_ir:
3379#endif
3380 ret = setup_msi_irq(dev, desc, irq);
3381 if (ret < 0) {
3382 destroy_irq(irq);
3383 return ret;
3384 }
3385 return 0;
3386
3387#ifdef CONFIG_INTR_REMAP
3388error:
3389 destroy_irq(irq);
3390 return ret;
3391#endif
3392}
3393
3394int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3395{
3396 unsigned int irq;
3397 int ret, sub_handle;
3398 struct msi_desc *desc;
3399 unsigned int irq_want;
3400
3401#ifdef CONFIG_INTR_REMAP
3402 struct intel_iommu *iommu = 0;
3403 int index = 0;
3404#endif
3405
3406 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3407 sub_handle = 0;
3408 list_for_each_entry(desc, &dev->msi_list, list) {
3409 irq = create_irq_nr(irq_want--);
3410 if (irq == 0)
3411 return -1;
3412#ifdef CONFIG_INTR_REMAP
3413 if (!intr_remapping_enabled)
3414 goto no_ir;
3415
3416 if (!sub_handle) {
3417 /*
3418 * allocate the consecutive block of IRTE's
3419 * for 'nvec'
3420 */
3421 index = msi_alloc_irte(dev, irq, nvec);
3422 if (index < 0) {
3423 ret = index;
3424 goto error;
3425 }
3426 } else {
3427 iommu = map_dev_to_ir(dev);
3428 if (!iommu) {
3429 ret = -ENOENT;
3430 goto error;
3431 }
3432 /*
3433 * setup the mapping between the irq and the IRTE
3434 * base index, the sub_handle pointing to the
3435 * appropriate interrupt remap table entry.
3436 */
3437 set_irte_irq(irq, iommu, index, sub_handle);
3438 }
3439no_ir:
3440#endif
3441 ret = setup_msi_irq(dev, desc, irq);
3442 if (ret < 0)
3443 goto error;
3444 sub_handle++;
3445 }
3446 return 0;
3447
3448error:
3449 destroy_irq(irq);
3450 return ret;
3451}
3452
3453void arch_teardown_msi_irq(unsigned int irq)
3454{
3455 destroy_irq(irq);
3456}
3457
3458#ifdef CONFIG_DMAR
3459#ifdef CONFIG_SMP
3460static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3461{
3462 struct irq_cfg *cfg;
3463 struct msi_msg msg;
3464 unsigned int dest;
3465 cpumask_t tmp;
3466 struct irq_desc *desc;
3467
3468 cpus_and(tmp, mask, cpu_online_map);
3469 if (cpus_empty(tmp))
3470 return;
3471
3472 if (assign_irq_vector(irq, mask))
3473 return;
3474
3475 cfg = irq_cfg(irq);
3476 cpus_and(tmp, cfg->domain, mask);
3477 dest = cpu_mask_to_apicid(tmp);
3478
3479 dmar_msi_read(irq, &msg);
3480
3481 msg.data &= ~MSI_DATA_VECTOR_MASK;
3482 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3483 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3484 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3485
3486 dmar_msi_write(irq, &msg);
3487 desc = irq_to_desc(irq);
3488 desc->affinity = mask;
3489}
3490#endif /* CONFIG_SMP */
3491
3492struct irq_chip dmar_msi_type = {
3493 .name = "DMAR_MSI",
3494 .unmask = dmar_msi_unmask,
3495 .mask = dmar_msi_mask,
3496 .ack = ack_apic_edge,
3497#ifdef CONFIG_SMP
3498 .set_affinity = dmar_msi_set_affinity,
3499#endif
3500 .retrigger = ioapic_retrigger_irq,
3501};
3502
3503int arch_setup_dmar_msi(unsigned int irq)
3504{
3505 int ret;
3506 struct msi_msg msg;
3507
3508 ret = msi_compose_msg(NULL, irq, &msg);
3509 if (ret < 0)
3510 return ret;
3511 dmar_msi_write(irq, &msg);
3512 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3513 "edge");
3514 return 0;
3515}
3516#endif
3517
3518#endif /* CONFIG_PCI_MSI */
3519/*
3520 * Hypertransport interrupt support
3521 */
3522#ifdef CONFIG_HT_IRQ
3523
3524#ifdef CONFIG_SMP
3525
3526static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3527{
3528 struct ht_irq_msg msg;
3529 fetch_ht_irq_msg(irq, &msg);
3530
3531 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3532 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3533
3534 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3535 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3536
3537 write_ht_irq_msg(irq, &msg);
3538}
3539
3540static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3541{
3542 struct irq_cfg *cfg;
3543 unsigned int dest;
3544 cpumask_t tmp;
3545 struct irq_desc *desc;
3546
3547 cpus_and(tmp, mask, cpu_online_map);
3548 if (cpus_empty(tmp))
3549 return;
3550
3551 if (assign_irq_vector(irq, mask))
3552 return;
3553
3554 cfg = irq_cfg(irq);
3555 cpus_and(tmp, cfg->domain, mask);
3556 dest = cpu_mask_to_apicid(tmp);
3557
3558 target_ht_irq(irq, dest, cfg->vector);
3559 desc = irq_to_desc(irq);
3560 desc->affinity = mask;
3561}
3562#endif
3563
3564static struct irq_chip ht_irq_chip = {
3565 .name = "PCI-HT",
3566 .mask = mask_ht_irq,
3567 .unmask = unmask_ht_irq,
3568 .ack = ack_apic_edge,
3569#ifdef CONFIG_SMP
3570 .set_affinity = set_ht_irq_affinity,
3571#endif
3572 .retrigger = ioapic_retrigger_irq,
3573};
3574
3575int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3576{
3577 struct irq_cfg *cfg;
3578 int err;
3579 cpumask_t tmp;
3580
3581 tmp = TARGET_CPUS;
3582 err = assign_irq_vector(irq, tmp);
3583 if (!err) {
3584 struct ht_irq_msg msg;
3585 unsigned dest;
3586
3587 cfg = irq_cfg(irq);
3588 cpus_and(tmp, cfg->domain, tmp);
3589 dest = cpu_mask_to_apicid(tmp);
3590
3591 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3592
3593 msg.address_lo =
3594 HT_IRQ_LOW_BASE |
3595 HT_IRQ_LOW_DEST_ID(dest) |
3596 HT_IRQ_LOW_VECTOR(cfg->vector) |
3597 ((INT_DEST_MODE == 0) ?
3598 HT_IRQ_LOW_DM_PHYSICAL :
3599 HT_IRQ_LOW_DM_LOGICAL) |
3600 HT_IRQ_LOW_RQEOI_EDGE |
3601 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3602 HT_IRQ_LOW_MT_FIXED :
3603 HT_IRQ_LOW_MT_ARBITRATED) |
3604 HT_IRQ_LOW_IRQ_MASKED;
3605
3606 write_ht_irq_msg(irq, &msg);
3607
3608 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3609 handle_edge_irq, "edge");
3610 }
3611 return err;
3612}
3613#endif /* CONFIG_HT_IRQ */
3614
3615/* --------------------------------------------------------------------------
3616 ACPI-based IOAPIC Configuration
3617 -------------------------------------------------------------------------- */
3618
3619#ifdef CONFIG_ACPI
3620
3621#ifdef CONFIG_X86_32
3622int __init io_apic_get_unique_id(int ioapic, int apic_id)
3623{
3624 union IO_APIC_reg_00 reg_00;
3625 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3626 physid_mask_t tmp;
3627 unsigned long flags;
3628 int i = 0;
3629
3630 /*
3631 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3632 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3633 * supports up to 16 on one shared APIC bus.
3634 *
3635 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3636 * advantage of new APIC bus architecture.
3637 */
3638
3639 if (physids_empty(apic_id_map))
3640 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3641
3642 spin_lock_irqsave(&ioapic_lock, flags);
3643 reg_00.raw = io_apic_read(ioapic, 0);
3644 spin_unlock_irqrestore(&ioapic_lock, flags);
3645
3646 if (apic_id >= get_physical_broadcast()) {
3647 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3648 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3649 apic_id = reg_00.bits.ID;
3650 }
3651
3652 /*
3653 * Every APIC in a system must have a unique ID or we get lots of nice
3654 * 'stuck on smp_invalidate_needed IPI wait' messages.
3655 */
3656 if (check_apicid_used(apic_id_map, apic_id)) {
3657
3658 for (i = 0; i < get_physical_broadcast(); i++) {
3659 if (!check_apicid_used(apic_id_map, i))
3660 break;
3661 }
3662
3663 if (i == get_physical_broadcast())
3664 panic("Max apic_id exceeded!\n");
3665
3666 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3667 "trying %d\n", ioapic, apic_id, i);
3668
3669 apic_id = i;
3670 }
3671
3672 tmp = apicid_to_cpu_present(apic_id);
3673 physids_or(apic_id_map, apic_id_map, tmp);
3674
3675 if (reg_00.bits.ID != apic_id) {
3676 reg_00.bits.ID = apic_id;
3677
3678 spin_lock_irqsave(&ioapic_lock, flags);
3679 io_apic_write(ioapic, 0, reg_00.raw);
3680 reg_00.raw = io_apic_read(ioapic, 0);
3681 spin_unlock_irqrestore(&ioapic_lock, flags);
3682
3683 /* Sanity check */
3684 if (reg_00.bits.ID != apic_id) {
3685 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3686 return -1;
3687 }
3688 }
3689
3690 apic_printk(APIC_VERBOSE, KERN_INFO
3691 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3692
3693 return apic_id;
3694}
3695
3696int __init io_apic_get_version(int ioapic)
3697{
3698 union IO_APIC_reg_01 reg_01;
3699 unsigned long flags;
3700
3701 spin_lock_irqsave(&ioapic_lock, flags);
3702 reg_01.raw = io_apic_read(ioapic, 1);
3703 spin_unlock_irqrestore(&ioapic_lock, flags);
3704
3705 return reg_01.bits.version;
3706}
3707#endif
3708
3709int __init io_apic_get_redir_entries (int ioapic)
3710{
3711 union IO_APIC_reg_01 reg_01;
3712 unsigned long flags;
3713
3714 spin_lock_irqsave(&ioapic_lock, flags);
3715 reg_01.raw = io_apic_read(ioapic, 1);
3716 spin_unlock_irqrestore(&ioapic_lock, flags);
3717
3718 return reg_01.bits.entries;
3719}
3720
3721
3722int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3723{
3724 if (!IO_APIC_IRQ(irq)) {
3725 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3726 ioapic);
3727 return -EINVAL;
3728 }
3729
3730 /*
3731 * IRQs < 16 are already in the irq_2_pin[] map
3732 */
3733 if (irq >= 16)
3734 add_pin_to_irq(irq, ioapic, pin);
3735
3736 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3737
3738 return 0;
3739}
3740
3741
3742int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3743{
3744 int i;
3745
3746 if (skip_ioapic_setup)
3747 return -1;
3748
3749 for (i = 0; i < mp_irq_entries; i++)
3750 if (mp_irqs[i].mp_irqtype == mp_INT &&
3751 mp_irqs[i].mp_srcbusirq == bus_irq)
3752 break;
3753 if (i >= mp_irq_entries)
3754 return -1;
3755
3756 *trigger = irq_trigger(i);
3757 *polarity = irq_polarity(i);
3758 return 0;
3759}
3760
3761#endif /* CONFIG_ACPI */
3762
3763/*
3764 * This function currently is only a helper for the i386 smp boot process where
3765 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3766 * so mask in all cases should simply be TARGET_CPUS
3767 */
3768#ifdef CONFIG_SMP
3769void __init setup_ioapic_dest(void)
3770{
3771 int pin, ioapic, irq, irq_entry;
3772 struct irq_cfg *cfg;
3773
3774 if (skip_ioapic_setup == 1)
3775 return;
3776
3777 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3778 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3779 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3780 if (irq_entry == -1)
3781 continue;
3782 irq = pin_2_irq(irq_entry, ioapic, pin);
3783
3784 /* setup_IO_APIC_irqs could fail to get vector for some device
3785 * when you have too many devices, because at that time only boot
3786 * cpu is online.
3787 */
3788 cfg = irq_cfg(irq);
3789 if (!cfg->vector)
3790 setup_IO_APIC_irq(ioapic, pin, irq,
3791 irq_trigger(irq_entry),
3792 irq_polarity(irq_entry));
3793#ifdef CONFIG_INTR_REMAP
3794 else if (intr_remapping_enabled)
3795 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3796#endif
3797 else
3798 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3799 }
3800
3801 }
3802}
3803#endif
3804
3805#ifdef CONFIG_X86_64
3806#define IOAPIC_RESOURCE_NAME_SIZE 11
3807
3808static struct resource *ioapic_resources;
3809
3810static struct resource * __init ioapic_setup_resources(void)
3811{
3812 unsigned long n;
3813 struct resource *res;
3814 char *mem;
3815 int i;
3816
3817 if (nr_ioapics <= 0)
3818 return NULL;
3819
3820 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3821 n *= nr_ioapics;
3822
3823 mem = alloc_bootmem(n);
3824 res = (void *)mem;
3825
3826 if (mem != NULL) {
3827 mem += sizeof(struct resource) * nr_ioapics;
3828
3829 for (i = 0; i < nr_ioapics; i++) {
3830 res[i].name = mem;
3831 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3832 sprintf(mem, "IOAPIC %u", i);
3833 mem += IOAPIC_RESOURCE_NAME_SIZE;
3834 }
3835 }
3836
3837 ioapic_resources = res;
3838
3839 return res;
3840}
3841#endif
3842
3843void __init ioapic_init_mappings(void)
3844{
3845 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3846 int i;
3847#ifdef CONFIG_X86_64
3848 struct resource *ioapic_res;
3849
3850 ioapic_res = ioapic_setup_resources();
3851#endif
3852 for (i = 0; i < nr_ioapics; i++) {
3853 if (smp_found_config) {
3854 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3855#ifdef CONFIG_X86_32
3856 if (!ioapic_phys) {
3857 printk(KERN_ERR
3858 "WARNING: bogus zero IO-APIC "
3859 "address found in MPTABLE, "
3860 "disabling IO/APIC support!\n");
3861 smp_found_config = 0;
3862 skip_ioapic_setup = 1;
3863 goto fake_ioapic_page;
3864 }
3865#endif
3866 } else {
3867#ifdef CONFIG_X86_32
3868fake_ioapic_page:
3869#endif
3870 ioapic_phys = (unsigned long)
3871 alloc_bootmem_pages(PAGE_SIZE);
3872 ioapic_phys = __pa(ioapic_phys);
3873 }
3874 set_fixmap_nocache(idx, ioapic_phys);
3875 apic_printk(APIC_VERBOSE,
3876 "mapped IOAPIC to %08lx (%08lx)\n",
3877 __fix_to_virt(idx), ioapic_phys);
3878 idx++;
3879
3880#ifdef CONFIG_X86_64
3881 if (ioapic_res != NULL) {
3882 ioapic_res->start = ioapic_phys;
3883 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3884 ioapic_res++;
3885 }
3886#endif
3887 }
3888}
3889
3890#ifdef CONFIG_X86_64
3891static int __init ioapic_insert_resources(void)
3892{
3893 int i;
3894 struct resource *r = ioapic_resources;
3895
3896 if (!r) {
3897 printk(KERN_ERR
3898 "IO APIC resources could be not be allocated.\n");
3899 return -1;
3900 }
3901
3902 for (i = 0; i < nr_ioapics; i++) {
3903 insert_resource(&iomem_resource, r);
3904 r++;
3905 }
3906
3907 return 0;
3908}
3909
3910/* Insert the IO APIC resources after PCI initialization has occured to handle
3911 * IO APICS that are mapped in on a BAR in PCI space. */
3912late_initcall(ioapic_insert_resources);
3913#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 05:48:22 -0500