Merge branch 'x86/apic-cleanups' into x86/numa

11 files changed, 164 insertions, 559 deletions

diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 9e13763b6092..f60153d5de57 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -84,7 +84,6 @@ obj-$(CONFIG_DOUBLEFAULT) 	+= doublefault_32.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_VM86)              += vm86_32.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
-obj-$(CONFIG_EARLY_PRINTK_MRST) += early_printk_mrst.o
 
 obj-$(CONFIG_HPET_TIMER)        += hpet.o
 obj-$(CONFIG_APB_TIMER)         += apb_timer.o
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 71232b941b6c..1a5b9a8e6c4f 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -847,18 +847,6 @@ static int __init acpi_parse_fadt(struct acpi_table_header *table)
  * returns 0 on success, < 0 on error
  */
 
-static void __init acpi_register_lapic_address(unsigned long address)
-{
-        mp_lapic_addr = address;
-
-        set_fixmap_nocache(FIX_APIC_BASE, address);
-        if (boot_cpu_physical_apicid == -1U) {
-                boot_cpu_physical_apicid  = read_apic_id();
-                apic_version[boot_cpu_physical_apicid] =
-                         GET_APIC_VERSION(apic_read(APIC_LVR));
-        }
-}
-
 static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
 {
         int count;
@@ -880,7 +868,7 @@ static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
                 return count;
         }
 
-        acpi_register_lapic_address(acpi_lapic_addr);
+        register_lapic_address(acpi_lapic_addr);
 
         return count;
 }
@@ -907,7 +895,7 @@ static int __init acpi_parse_madt_lapic_entries(void)
                 return count;
         }
 
-        acpi_register_lapic_address(acpi_lapic_addr);
+        register_lapic_address(acpi_lapic_addr);
 
         count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_SAPIC,
                                       acpi_parse_sapic, MAX_APICS);
@@ -949,32 +937,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
 extern int es7000_plat;
 #endif
 
-static void assign_to_mp_irq(struct mpc_intsrc *m,
-                                    struct mpc_intsrc *mp_irq)
-{
-        memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
-}
-
-static int mp_irq_cmp(struct mpc_intsrc *mp_irq,
-                                struct mpc_intsrc *m)
-{
-        return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
-}
-
-static void save_mp_irq(struct mpc_intsrc *m)
-{
-        int i;
-
-        for (i = 0; i < mp_irq_entries; i++) {
-                if (!mp_irq_cmp(&mp_irqs[i], m))
-                        return;
-        }
-
-        assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
-        if (++mp_irq_entries == MAX_IRQ_SOURCES)
-                panic("Max # of irq sources exceeded!!\n");
-}
-
 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
 {
         int ioapic;
@@ -1005,7 +967,7 @@ void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
         mp_irq.dstapic = mp_ioapics[ioapic].apicid; /* APIC ID */
         mp_irq.dstirq = pin;    /* INTIN# */
 
-        save_mp_irq(&mp_irq);
+        mp_save_irq(&mp_irq);
 
         isa_irq_to_gsi[bus_irq] = gsi;
 }
@@ -1080,7 +1042,7 @@ void __init mp_config_acpi_legacy_irqs(void)
                 mp_irq.srcbusirq = i; /* Identity mapped */
                 mp_irq.dstirq = pin;
 
-                save_mp_irq(&mp_irq);
+                mp_save_irq(&mp_irq);
         }
 }
 
@@ -1117,7 +1079,7 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
         mp_irq.dstapic = mp_ioapics[ioapic].apicid;
         mp_irq.dstirq = mp_find_ioapic_pin(ioapic, gsi);
 
-        save_mp_irq(&mp_irq);
+        mp_save_irq(&mp_irq);
 #endif
         return 0;
 }
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 92543c73cf8e..7c9ab59653e8 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -315,6 +315,7 @@ static void apbt_setup_irq(struct apbt_dev *adev)
 
         if (system_state == SYSTEM_BOOTING) {
                 irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
+                irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
                 /* APB timer irqs are set up as mp_irqs, timer is edge type */
                 __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge");
                 if (request_irq(adev->irq, apbt_interrupt_handler,
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 3f838d537392..c0f6426cd337 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1195,12 +1195,15 @@ static void __cpuinit lapic_setup_esr(void)
                         oldvalue, value);
 }
 
-
 /**
  * setup_local_APIC - setup the local APIC
+ *
+ * Used to setup local APIC while initializing BSP or bringin up APs.
+ * Always called with preemption disabled.
  */
 void __cpuinit setup_local_APIC(void)
 {
+        int cpu = smp_processor_id();
         unsigned int value, queued;
         int i, j, acked = 0;
         unsigned long long tsc = 0, ntsc;
@@ -1225,8 +1228,6 @@ void __cpuinit setup_local_APIC(void)
 #endif
         perf_events_lapic_init();
 
-        preempt_disable();
-
         /*
          * Double-check whether this APIC is really registered.
          * This is meaningless in clustered apic mode, so we skip it.
@@ -1342,21 +1343,19 @@ void __cpuinit setup_local_APIC(void)
          * TODO: set up through-local-APIC from through-I/O-APIC? --macro
          */
         value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
-        if (!smp_processor_id() && (pic_mode || !value)) {
+        if (!cpu && (pic_mode || !value)) {
                 value = APIC_DM_EXTINT;
-                apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
-                                smp_processor_id());
+                apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
         } else {
                 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
-                apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
-                                smp_processor_id());
+                apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
         }
         apic_write(APIC_LVT0, value);
 
         /*
          * only the BP should see the LINT1 NMI signal, obviously.
          */
-        if (!smp_processor_id())
+        if (!cpu)
                 value = APIC_DM_NMI;
         else
                 value = APIC_DM_NMI | APIC_LVT_MASKED;
@@ -1364,11 +1363,9 @@ void __cpuinit setup_local_APIC(void)
                 value |= APIC_LVT_LEVEL_TRIGGER;
         apic_write(APIC_LVT1, value);
 
-        preempt_enable();
-
 #ifdef CONFIG_X86_MCE_INTEL
         /* Recheck CMCI information after local APIC is up on CPU #0 */
-        if (smp_processor_id() == 0)
+        if (!cpu)
                 cmci_recheck();
 #endif
 }
@@ -1530,13 +1527,60 @@ static int __init detect_init_APIC(void)
         return 0;
 }
 #else
+
+static int apic_verify(void)
+{
+        u32 features, h, l;
+
+        /*
+         * The APIC feature bit should now be enabled
+         * in `cpuid'
+         */
+        features = cpuid_edx(1);
+        if (!(features & (1 << X86_FEATURE_APIC))) {
+                pr_warning("Could not enable APIC!\n");
+                return -1;
+        }
+        set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
+        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
+
+        /* The BIOS may have set up the APIC at some other address */
+        rdmsr(MSR_IA32_APICBASE, l, h);
+        if (l & MSR_IA32_APICBASE_ENABLE)
+                mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+
+        pr_info("Found and enabled local APIC!\n");
+        return 0;
+}
+
+int apic_force_enable(void)
+{
+        u32 h, l;
+
+        if (disable_apic)
+                return -1;
+
+        /*
+         * Some BIOSes disable the local APIC in the APIC_BASE
+         * MSR. This can only be done in software for Intel P6 or later
+         * and AMD K7 (Model > 1) or later.
+         */
+        rdmsr(MSR_IA32_APICBASE, l, h);
+        if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                l &= ~MSR_IA32_APICBASE_BASE;
+                l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
+                wrmsr(MSR_IA32_APICBASE, l, h);
+                enabled_via_apicbase = 1;
+        }
+        return apic_verify();
+}
+
 /*
  * Detect and initialize APIC
  */
 static int __init detect_init_APIC(void)
 {
-        u32 h, l, features;
-
         /* Disabled by kernel option? */
         if (disable_apic)
                 return -1;
@@ -1566,38 +1610,12 @@ static int __init detect_init_APIC(void)
                                 "you can enable it with \"lapic\"\n");
                         return -1;
                 }
-                /*
-                 * Some BIOSes disable the local APIC in the APIC_BASE
-                 * MSR. This can only be done in software for Intel P6 or later
-                 * and AMD K7 (Model > 1) or later.
-                 */
-                rdmsr(MSR_IA32_APICBASE, l, h);
-                if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-                        pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-                        l &= ~MSR_IA32_APICBASE_BASE;
-                        l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
-                        wrmsr(MSR_IA32_APICBASE, l, h);
-                        enabled_via_apicbase = 1;
-                }
-        }
-        /*
-         * The APIC feature bit should now be enabled
-         * in `cpuid'
-         */
-        features = cpuid_edx(1);
-        if (!(features & (1 << X86_FEATURE_APIC))) {
-                pr_warning("Could not enable APIC!\n");
-                return -1;
+                if (apic_force_enable())
+                        return -1;
+        } else {
+                if (apic_verify())
+                        return -1;
         }
-        set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
-        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
-
-        /* The BIOS may have set up the APIC at some other address */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        if (l & MSR_IA32_APICBASE_ENABLE)
-                mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
-
-        pr_info("Found and enabled local APIC!\n");
 
         apic_pm_activate();
 
@@ -1609,28 +1627,6 @@ no_apic:
 }
 #endif
 
-#ifdef CONFIG_X86_64
-void __init early_init_lapic_mapping(void)
-{
-        /*
-         * If no local APIC can be found then go out
-         * : it means there is no mpatable and MADT
-         */
-        if (!smp_found_config)
-                return;
-
-        set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
-        apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
-                    APIC_BASE, mp_lapic_addr);
-
-        /*
-         * Fetch the APIC ID of the BSP in case we have a
-         * default configuration (or the MP table is broken).
-         */
-        boot_cpu_physical_apicid = read_apic_id();
-}
-#endif
-
 /**
  * init_apic_mappings - initialize APIC mappings
  */
@@ -1656,10 +1652,7 @@ void __init init_apic_mappings(void)
                  * acpi_register_lapic_address()
                  */
                 if (!acpi_lapic && !smp_found_config)
-                        set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
-
-                apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
-                                        APIC_BASE, apic_phys);
+                        register_lapic_address(apic_phys);
         }
 
         /*
@@ -1681,6 +1674,22 @@ void __init init_apic_mappings(void)
         }
 }
 
+void __init register_lapic_address(unsigned long address)
+{
+        mp_lapic_addr = address;
+
+        if (!x2apic_mode) {
+                set_fixmap_nocache(FIX_APIC_BASE, address);
+                apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
+                            APIC_BASE, mp_lapic_addr);
+        }
+        if (boot_cpu_physical_apicid == -1U) {
+                boot_cpu_physical_apicid  = read_apic_id();
+                apic_version[boot_cpu_physical_apicid] =
+                         GET_APIC_VERSION(apic_read(APIC_LVR));
+        }
+}
+
 /*
  * This initializes the IO-APIC and APIC hardware if this is
  * a UP kernel.
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 7cc0a721f628..bb61a552d8c6 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -126,6 +126,26 @@ static int __init parse_noapic(char *str)
 }
 early_param("noapic", parse_noapic);
 
+/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
+void mp_save_irq(struct mpc_intsrc *m)
+{
+        int i;
+
+        apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
+                " IRQ %02x, APIC ID %x, APIC INT %02x\n",
+                m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
+                m->srcbusirq, m->dstapic, m->dstirq);
+
+        for (i = 0; i < mp_irq_entries; i++) {
+                if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
+                        return;
+        }
+
+        memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
+        if (++mp_irq_entries == MAX_IRQ_SOURCES)
+                panic("Max # of irq sources exceeded!!\n");
+}
+
 struct irq_pin_list {
         int apic, pin;
         struct irq_pin_list *next;
@@ -136,6 +156,7 @@ static struct irq_pin_list *alloc_irq_pin_list(int node)
         return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
 }
 
+
 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 #ifdef CONFIG_SPARSE_IRQ
 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
@@ -1934,8 +1955,7 @@ void disable_IO_APIC(void)
  *
  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
  */
-
-void __init setup_ioapic_ids_from_mpc(void)
+void __init setup_ioapic_ids_from_mpc_nocheck(void)
 {
         union IO_APIC_reg_00 reg_00;
         physid_mask_t phys_id_present_map;
@@ -1944,15 +1964,6 @@ void __init setup_ioapic_ids_from_mpc(void)
         unsigned char old_id;
         unsigned long flags;
 
-        if (acpi_ioapic)
-                return;
-        /*
-         * Don't check I/O APIC IDs for xAPIC systems.  They have
-         * no meaning without the serial APIC bus.
-         */
-        if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-                || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
-                return;
         /*
          * This is broken; anything with a real cpu count has to
          * circumvent this idiocy regardless.
@@ -2006,7 +2017,6 @@ void __init setup_ioapic_ids_from_mpc(void)
                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
                 }
 
-
                 /*
                  * We need to adjust the IRQ routing table
                  * if the ID changed.
@@ -2018,9 +2028,12 @@ void __init setup_ioapic_ids_from_mpc(void)
                                                 = mp_ioapics[apic_id].apicid;
 
                 /*
-                 * Read the right value from the MPC table and
-                 * write it into the ID register.
+                 * Update the ID register according to the right value
+                 * from the MPC table if they are different.
                  */
+                if (mp_ioapics[apic_id].apicid == reg_00.bits.ID)
+                        continue;
+
                 apic_printk(APIC_VERBOSE, KERN_INFO
                         "...changing IO-APIC physical APIC ID to %d ...",
                         mp_ioapics[apic_id].apicid);
@@ -2042,6 +2055,21 @@ void __init setup_ioapic_ids_from_mpc(void)
                         apic_printk(APIC_VERBOSE, " ok.\n");
         }
 }
+
+void __init setup_ioapic_ids_from_mpc(void)
+{
+
+        if (acpi_ioapic)
+                return;
+        /*
+         * Don't check I/O APIC IDs for xAPIC systems.  They have
+         * no meaning without the serial APIC bus.
+         */
+        if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+                || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
+                return;
+        setup_ioapic_ids_from_mpc_nocheck();
+}
 #endif
 
 int no_timer_check __initdata;
@@ -3639,7 +3667,7 @@ int __init io_apic_get_redir_entries (int ioapic)
         return reg_01.bits.entries + 1;
 }
 
-void __init probe_nr_irqs_gsi(void)
+static void __init probe_nr_irqs_gsi(void)
 {
         int nr;
 
@@ -3956,7 +3984,7 @@ static struct resource * __init ioapic_setup_resources(int nr_ioapics)
         return res;
 }
 
-void __init ioapic_init_mappings(void)
+void __init ioapic_and_gsi_init(void)
 {
         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
         struct resource *ioapic_res;
@@ -3994,6 +4022,8 @@ fake_ioapic_page:
                 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
                 ioapic_res++;
         }
+
+        probe_nr_irqs_gsi();
 }
 
 void __init ioapic_insert_resources(void)
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index 4572f25f9325..cd28a350f7f9 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -240,7 +240,7 @@ static int __init setup_early_printk(char *buf)
                 if (!strncmp(buf, "xen", 3))
                         early_console_register(&xenboot_console, keep);
 #endif
-#ifdef CONFIG_X86_MRST_EARLY_PRINTK
+#ifdef CONFIG_EARLY_PRINTK_MRST
                 if (!strncmp(buf, "mrst", 4)) {
                         mrst_early_console_init();
                         early_console_register(&early_mrst_console, keep);
@@ -250,7 +250,6 @@ static int __init setup_early_printk(char *buf)
                         hsu_early_console_init();
                         early_console_register(&early_hsu_console, keep);
                 }
-
 #endif
                 buf++;
         }
diff --git a/arch/x86/kernel/early_printk_mrst.c b/arch/x86/kernel/early_printk_mrst.c
deleted file mode 100644
index 65df603622b2..000000000000
--- a/arch/x86/kernel/early_printk_mrst.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * early_printk_mrst.c - early consoles for Intel MID platforms
- *
- * Copyright (c) 2008-2010, Intel Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; version 2
- * of the License.
- */
-
-/*
- * This file implements two early consoles named mrst and hsu.
- * mrst is based on Maxim3110 spi-uart device, it exists in both
- * Moorestown and Medfield platforms, while hsu is based on a High
- * Speed UART device which only exists in the Medfield platform
- */
-
-#include <linux/serial_reg.h>
-#include <linux/serial_mfd.h>
-#include <linux/kmsg_dump.h>
-#include <linux/console.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/fixmap.h>
-#include <asm/pgtable.h>
-#include <asm/mrst.h>
-
-#define MRST_SPI_TIMEOUT                0x200000
-#define MRST_REGBASE_SPI0               0xff128000
-#define MRST_REGBASE_SPI1               0xff128400
-#define MRST_CLK_SPI0_REG               0xff11d86c
-
-/* Bit fields in CTRLR0 */
-#define SPI_DFS_OFFSET                  0
-
-#define SPI_FRF_OFFSET                  4
-#define SPI_FRF_SPI                     0x0
-#define SPI_FRF_SSP                     0x1
-#define SPI_FRF_MICROWIRE               0x2
-#define SPI_FRF_RESV                    0x3
-
-#define SPI_MODE_OFFSET                 6
-#define SPI_SCPH_OFFSET                 6
-#define SPI_SCOL_OFFSET                 7
-#define SPI_TMOD_OFFSET                 8
-#define SPI_TMOD_TR                     0x0             /* xmit & recv */
-#define SPI_TMOD_TO                     0x1             /* xmit only */
-#define SPI_TMOD_RO                     0x2             /* recv only */
-#define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
-
-#define SPI_SLVOE_OFFSET                10
-#define SPI_SRL_OFFSET                  11
-#define SPI_CFS_OFFSET                  12
-
-/* Bit fields in SR, 7 bits */
-#define SR_MASK                         0x7f            /* cover 7 bits */
-#define SR_BUSY                         (1 << 0)
-#define SR_TF_NOT_FULL                  (1 << 1)
-#define SR_TF_EMPT                      (1 << 2)
-#define SR_RF_NOT_EMPT                  (1 << 3)
-#define SR_RF_FULL                      (1 << 4)
-#define SR_TX_ERR                       (1 << 5)
-#define SR_DCOL                         (1 << 6)
-
-struct dw_spi_reg {
-        u32     ctrl0;
-        u32     ctrl1;
-        u32     ssienr;
-        u32     mwcr;
-        u32     ser;
-        u32     baudr;
-        u32     txfltr;
-        u32     rxfltr;
-        u32     txflr;
-        u32     rxflr;
-        u32     sr;
-        u32     imr;
-        u32     isr;
-        u32     risr;
-        u32     txoicr;
-        u32     rxoicr;
-        u32     rxuicr;
-        u32     msticr;
-        u32     icr;
-        u32     dmacr;
-        u32     dmatdlr;
-        u32     dmardlr;
-        u32     idr;
-        u32     version;
-
-        /* Currently operates as 32 bits, though only the low 16 bits matter */
-        u32     dr;
-} __packed;
-
-#define dw_readl(dw, name)              __raw_readl(&(dw)->name)
-#define dw_writel(dw, name, val)        __raw_writel((val), &(dw)->name)
-
-/* Default use SPI0 register for mrst, we will detect Penwell and use SPI1 */
-static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
-
-static u32 *pclk_spi0;
-/* Always contains an accessable address, start with 0 */
-static struct dw_spi_reg *pspi;
-
-static struct kmsg_dumper dw_dumper;
-static int dumper_registered;
-
-static void dw_kmsg_dump(struct kmsg_dumper *dumper,
-                        enum kmsg_dump_reason reason,
-                        const char *s1, unsigned long l1,
-                        const char *s2, unsigned long l2)
-{
-        int i;
-
-        /* When run to this, we'd better re-init the HW */
-        mrst_early_console_init();
-
-        for (i = 0; i < l1; i++)
-                early_mrst_console.write(&early_mrst_console, s1 + i, 1);
-        for (i = 0; i < l2; i++)
-                early_mrst_console.write(&early_mrst_console, s2 + i, 1);
-}
-
-/* Set the ratio rate to 115200, 8n1, IRQ disabled */
-static void max3110_write_config(void)
-{
-        u16 config;
-
-        config = 0xc001;
-        dw_writel(pspi, dr, config);
-}
-
-/* Translate char to a eligible word and send to max3110 */
-static void max3110_write_data(char c)
-{
-        u16 data;
-
-        data = 0x8000 | c;
-        dw_writel(pspi, dr, data);
-}
-
-void mrst_early_console_init(void)
-{
-        u32 ctrlr0 = 0;
-        u32 spi0_cdiv;
-        u32 freq; /* Freqency info only need be searched once */
-
-        /* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
-        pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
-                                                        MRST_CLK_SPI0_REG);
-        spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
-        freq = 100000000 / (spi0_cdiv + 1);
-
-        if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL)
-                mrst_spi_paddr = MRST_REGBASE_SPI1;
-
-        pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
-                                                mrst_spi_paddr);
-
-        /* Disable SPI controller */
-        dw_writel(pspi, ssienr, 0);
-
-        /* Set control param, 8 bits, transmit only mode */
-        ctrlr0 = dw_readl(pspi, ctrl0);
-
-        ctrlr0 &= 0xfcc0;
-        ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
-                      | (SPI_TMOD_TO << SPI_TMOD_OFFSET);
-        dw_writel(pspi, ctrl0, ctrlr0);
-
-        /*
-         * Change the spi0 clk to comply with 115200 bps, use 100000 to
-         * calculate the clk dividor to make the clock a little slower
-         * than real baud rate.
-         */
-        dw_writel(pspi, baudr, freq/100000);
-
-        /* Disable all INT for early phase */
-        dw_writel(pspi, imr, 0x0);
-
-        /* Set the cs to spi-uart */
-        dw_writel(pspi, ser, 0x2);
-
-        /* Enable the HW, the last step for HW init */
-        dw_writel(pspi, ssienr, 0x1);
-
-        /* Set the default configuration */
-        max3110_write_config();
-
-        /* Register the kmsg dumper */
-        if (!dumper_registered) {
-                dw_dumper.dump = dw_kmsg_dump;
-                kmsg_dump_register(&dw_dumper);
-                dumper_registered = 1;
-        }
-}
-
-/* Slave select should be called in the read/write function */
-static void early_mrst_spi_putc(char c)
-{
-        unsigned int timeout;
-        u32 sr;
-
-        timeout = MRST_SPI_TIMEOUT;
-        /* Early putc needs to make sure the TX FIFO is not full */
-        while (--timeout) {
-                sr = dw_readl(pspi, sr);
-                if (!(sr & SR_TF_NOT_FULL))
-                        cpu_relax();
-                else
-                        break;
-        }
-
-        if (!timeout)
-                pr_warning("MRST earlycon: timed out\n");
-        else
-                max3110_write_data(c);
-}
-
-/* Early SPI only uses polling mode */
-static void early_mrst_spi_write(struct console *con, const char *str, unsigned n)
-{
-        int i;
-
-        for (i = 0; i < n && *str; i++) {
-                if (*str == '\n')
-                        early_mrst_spi_putc('\r');
-                early_mrst_spi_putc(*str);
-                str++;
-        }
-}
-
-struct console early_mrst_console = {
-        .name =         "earlymrst",
-        .write =        early_mrst_spi_write,
-        .flags =        CON_PRINTBUFFER,
-        .index =        -1,
-};
-
-/*
- * Following is the early console based on Medfield HSU (High
- * Speed UART) device.
- */
-#define HSU_PORT2_PADDR         0xffa28180
-
-static void __iomem *phsu;
-
-void hsu_early_console_init(void)
-{
-        u8 lcr;
-
-        phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
-                                                        HSU_PORT2_PADDR);
-
-        /* Disable FIFO */
-        writeb(0x0, phsu + UART_FCR);
-
-        /* Set to default 115200 bps, 8n1 */
-        lcr = readb(phsu + UART_LCR);
-        writeb((0x80 | lcr), phsu + UART_LCR);
-        writeb(0x18, phsu + UART_DLL);
-        writeb(lcr,  phsu + UART_LCR);
-        writel(0x3600, phsu + UART_MUL*4);
-
-        writeb(0x8, phsu + UART_MCR);
-        writeb(0x7, phsu + UART_FCR);
-        writeb(0x3, phsu + UART_LCR);
-
-        /* Clear IRQ status */
-        readb(phsu + UART_LSR);
-        readb(phsu + UART_RX);
-        readb(phsu + UART_IIR);
-        readb(phsu + UART_MSR);
-
-        /* Enable FIFO */
-        writeb(0x7, phsu + UART_FCR);
-}
-
-#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
-
-static void early_hsu_putc(char ch)
-{
-        unsigned int timeout = 10000; /* 10ms */
-        u8 status;
-
-        while (--timeout) {
-                status = readb(phsu + UART_LSR);
-                if (status & BOTH_EMPTY)
-                        break;
-                udelay(1);
-        }
-
-        /* Only write the char when there was no timeout */
-        if (timeout)
-                writeb(ch, phsu + UART_TX);
-}
-
-static void early_hsu_write(struct console *con, const char *str, unsigned n)
-{
-        int i;
-
-        for (i = 0; i < n && *str; i++) {
-                if (*str == '\n')
-                        early_hsu_putc('\r');
-                early_hsu_putc(*str);
-                str++;
-        }
-}
-
-struct console early_hsu_console = {
-        .name =         "earlyhsu",
-        .write =        early_hsu_write,
-        .flags =        CON_PRINTBUFFER,
-        .index =        -1,
-};
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index 763310165fa0..7f138b3c3c52 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -61,6 +61,9 @@ void __init i386_start_kernel(void)
         case X86_SUBARCH_MRST:
                 x86_mrst_early_setup();
                 break;
+        case X86_SUBARCH_CE4100:
+                x86_ce4100_early_setup();
+                break;
         default:
                 i386_default_early_setup();
                 break;
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 9af64d9c4b67..01b0f6d06451 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -118,21 +118,8 @@ static void __init MP_bus_info(struct mpc_bus *m)
 
 static void __init MP_ioapic_info(struct mpc_ioapic *m)
 {
-        if (!(m->flags & MPC_APIC_USABLE))
-                return;
-
-        printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
-               m->apicid, m->apicver, m->apicaddr);
-
-        mp_register_ioapic(m->apicid, m->apicaddr, gsi_top);
-}
-
-static void print_MP_intsrc_info(struct mpc_intsrc *m)
-{
-        apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
-                " IRQ %02x, APIC ID %x, APIC INT %02x\n",
-                m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
-                m->srcbusirq, m->dstapic, m->dstirq);
+        if (m->flags & MPC_APIC_USABLE)
+                mp_register_ioapic(m->apicid, m->apicaddr, gsi_top);
 }
 
 static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
@@ -144,73 +131,11 @@ static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
                 mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq);
 }
 
-static void __init assign_to_mp_irq(struct mpc_intsrc *m,
-                                    struct mpc_intsrc *mp_irq)
-{
-        mp_irq->dstapic = m->dstapic;
-        mp_irq->type = m->type;
-        mp_irq->irqtype = m->irqtype;
-        mp_irq->irqflag = m->irqflag;
-        mp_irq->srcbus = m->srcbus;
-        mp_irq->srcbusirq = m->srcbusirq;
-        mp_irq->dstirq = m->dstirq;
-}
-
-static void __init assign_to_mpc_intsrc(struct mpc_intsrc *mp_irq,
-                                        struct mpc_intsrc *m)
-{
-        m->dstapic = mp_irq->dstapic;
-        m->type = mp_irq->type;
-        m->irqtype = mp_irq->irqtype;
-        m->irqflag = mp_irq->irqflag;
-        m->srcbus = mp_irq->srcbus;
-        m->srcbusirq = mp_irq->srcbusirq;
-        m->dstirq = mp_irq->dstirq;
-}
-
-static int __init mp_irq_mpc_intsrc_cmp(struct mpc_intsrc *mp_irq,
-                                        struct mpc_intsrc *m)
-{
-        if (mp_irq->dstapic != m->dstapic)
-                return 1;
-        if (mp_irq->type != m->type)
-                return 2;
-        if (mp_irq->irqtype != m->irqtype)
-                return 3;
-        if (mp_irq->irqflag != m->irqflag)
-                return 4;
-        if (mp_irq->srcbus != m->srcbus)
-                return 5;
-        if (mp_irq->srcbusirq != m->srcbusirq)
-                return 6;
-        if (mp_irq->dstirq != m->dstirq)
-                return 7;
-
-        return 0;
-}
-
-static void __init MP_intsrc_info(struct mpc_intsrc *m)
-{
-        int i;
-
-        print_MP_intsrc_info(m);
-
-        for (i = 0; i < mp_irq_entries; i++) {
-                if (!mp_irq_mpc_intsrc_cmp(&mp_irqs[i], m))
-                        return;
-        }
-
-        assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
-        if (++mp_irq_entries == MAX_IRQ_SOURCES)
-                panic("Max # of irq sources exceeded!!\n");
-}
 #else /* CONFIG_X86_IO_APIC */
 static inline void __init MP_bus_info(struct mpc_bus *m) {}
 static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {}
-static inline void __init MP_intsrc_info(struct mpc_intsrc *m) {}
 #endif /* CONFIG_X86_IO_APIC */
 
-
 static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
 {
         apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x,"
@@ -222,7 +147,6 @@ static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
 /*
  * Read/parse the MPC
  */
-
 static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)
 {
 
@@ -275,18 +199,6 @@ static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt)
 
 void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { }
 
-static void __init smp_register_lapic_address(unsigned long address)
-{
-        mp_lapic_addr = address;
-
-        set_fixmap_nocache(FIX_APIC_BASE, address);
-        if (boot_cpu_physical_apicid == -1U) {
-                boot_cpu_physical_apicid  = read_apic_id();
-                apic_version[boot_cpu_physical_apicid] =
-                         GET_APIC_VERSION(apic_read(APIC_LVR));
-        }
-}
-
 static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
 {
         char str[16];
@@ -301,17 +213,13 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
 #ifdef CONFIG_X86_32
         generic_mps_oem_check(mpc, oem, str);
 #endif
-        /* save the local APIC address, it might be non-default */
+        /* Initialize the lapic mapping */
         if (!acpi_lapic)
-                mp_lapic_addr = mpc->lapic;
+                register_lapic_address(mpc->lapic);
 
         if (early)
                 return 1;
 
-        /* Initialize the lapic mapping */
-        if (!acpi_lapic)
-                smp_register_lapic_address(mpc->lapic);
-
         if (mpc->oemptr)
                 x86_init.mpparse.smp_read_mpc_oem(mpc);
 
@@ -337,7 +245,7 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
                         skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
                         break;
                 case MP_INTSRC:
-                        MP_intsrc_info((struct mpc_intsrc *)mpt);
+                        mp_save_irq((struct mpc_intsrc *)mpt);
                         skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
                         break;
                 case MP_LINTSRC:
@@ -429,13 +337,13 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
 
                 intsrc.srcbusirq = i;
                 intsrc.dstirq = i ? i : 2;      /* IRQ0 to INTIN2 */
-                MP_intsrc_info(&intsrc);
+                mp_save_irq(&intsrc);
         }
 
         intsrc.irqtype = mp_ExtINT;
         intsrc.srcbusirq = 0;
         intsrc.dstirq = 0;      /* 8259A to INTIN0 */
-        MP_intsrc_info(&intsrc);
+        mp_save_irq(&intsrc);
 }
 
 
@@ -784,11 +692,11 @@ static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare)
         int i;
 
         apic_printk(APIC_VERBOSE, "OLD ");
-        print_MP_intsrc_info(m);
+        print_mp_irq_info(m);
 
         i = get_MP_intsrc_index(m);
         if (i > 0) {
-                assign_to_mpc_intsrc(&mp_irqs[i], m);
+                memcpy(m, &mp_irqs[i], sizeof(*m));
                 apic_printk(APIC_VERBOSE, "NEW ");
                 print_mp_irq_info(&mp_irqs[i]);
                 return;
@@ -875,14 +783,14 @@ static int  __init replace_intsrc_all(struct mpc_table *mpc,
                 if (nr_m_spare > 0) {
                         apic_printk(APIC_VERBOSE, "*NEW* found\n");
                         nr_m_spare--;
-                        assign_to_mpc_intsrc(&mp_irqs[i], m_spare[nr_m_spare]);
+                        memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i]));
                         m_spare[nr_m_spare] = NULL;
                 } else {
                         struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
                         count += sizeof(struct mpc_intsrc);
                         if (check_slot(mpc_new_phys, mpc_new_length, count) < 0)
                                 goto out;
-                        assign_to_mpc_intsrc(&mp_irqs[i], m);
+                        memcpy(m, &mp_irqs[i], sizeof(*m));
                         mpc->length = count;
                         mpt += sizeof(struct mpc_intsrc);
                 }
diff --git a/arch/x86/kernel/reboot_fixups_32.c b/arch/x86/kernel/reboot_fixups_32.c
index fda313ebbb03..c8e41e90f59c 100644
--- a/arch/x86/kernel/reboot_fixups_32.c
+++ b/arch/x86/kernel/reboot_fixups_32.c
@@ -43,17 +43,33 @@ static void rdc321x_reset(struct pci_dev *dev)
         outb(1, 0x92);
 }
 
+static void ce4100_reset(struct pci_dev *dev)
+{
+        int i;
+
+        for (i = 0; i < 10; i++) {
+                outb(0x2, 0xcf9);
+                udelay(50);
+        }
+}
+
 struct device_fixup {
         unsigned int vendor;
         unsigned int device;
         void (*reboot_fixup)(struct pci_dev *);
 };
 
+/*
+ * PCI ids solely used for fixups_table go here
+ */
+#define PCI_DEVICE_ID_INTEL_CE4100      0x0708
+
 static const struct device_fixup fixups_table[] = {
 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, cs5530a_warm_reset },
 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, cs5536_warm_reset },
 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE, cs5530a_warm_reset },
 { PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030, rdc321x_reset },
+{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100, ce4100_reset },
 };
 
 /*
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index df172c1e8238..0afb8c7e3803 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1035,10 +1035,7 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
         init_apic_mappings();
-        ioapic_init_mappings();
-
-        /* need to wait for io_apic is mapped */
-        probe_nr_irqs_gsi();
+        ioapic_and_gsi_init();
 
         kvm_guest_init();