diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-26 22:40:37 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-26 22:40:37 -0500 |
commit | f8ef15d6b9d8e38729cd740a43919adf88468119 (patch) | |
tree | f950b0342b8ae7ad0a11477cdf669015fc85366e /arch/x86/kernel | |
parent | 6515925b8259549b7f2187e25d3260306e3e85e5 (diff) | |
parent | ff1fb5f6b4925a536ffb8171e5f2dbd01ccfeb97 (diff) |
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar.
* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86: Add Intel IvyBridge event scheduling constraints
ftrace: Call ftrace cleanup module notifier after all other notifiers
tracing/syscalls: Allow archs to ignore tracing compat syscalls
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel.c | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 4914e94ad6e8..529c8931fc02 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c | |||
@@ -107,6 +107,27 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly = | |||
107 | EVENT_CONSTRAINT_END | 107 | EVENT_CONSTRAINT_END |
108 | }; | 108 | }; |
109 | 109 | ||
110 | static struct event_constraint intel_ivb_event_constraints[] __read_mostly = | ||
111 | { | ||
112 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | ||
113 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | ||
114 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | ||
115 | INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ | ||
116 | INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ | ||
117 | INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ | ||
118 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ | ||
119 | INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ | ||
120 | INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ | ||
121 | INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | ||
122 | INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ | ||
123 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ | ||
124 | INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ | ||
125 | INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | ||
126 | INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | ||
127 | INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | ||
128 | EVENT_CONSTRAINT_END | ||
129 | }; | ||
130 | |||
110 | static struct extra_reg intel_westmere_extra_regs[] __read_mostly = | 131 | static struct extra_reg intel_westmere_extra_regs[] __read_mostly = |
111 | { | 132 | { |
112 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), | 133 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), |
@@ -2095,7 +2116,7 @@ __init int intel_pmu_init(void) | |||
2095 | 2116 | ||
2096 | intel_pmu_lbr_init_snb(); | 2117 | intel_pmu_lbr_init_snb(); |
2097 | 2118 | ||
2098 | x86_pmu.event_constraints = intel_snb_event_constraints; | 2119 | x86_pmu.event_constraints = intel_ivb_event_constraints; |
2099 | x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; | 2120 | x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; |
2100 | x86_pmu.pebs_aliases = intel_pebs_aliases_snb; | 2121 | x86_pmu.pebs_aliases = intel_pebs_aliases_snb; |
2101 | x86_pmu.extra_regs = intel_snb_extra_regs; | 2122 | x86_pmu.extra_regs = intel_snb_extra_regs; |