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authorHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>2009-06-15 04:24:40 -0400
committerH. Peter Anvin <hpa@zytor.com>2009-06-16 19:56:08 -0400
commite8ce2c5ee826b3787202493effcd08d4b1e1e639 (patch)
tree45dfcd93086820963d196d88851d772d11b2f8e9 /arch/x86/kernel
parent5335612a574a45beab14193ec641ed2f45e7a523 (diff)
x86, mce: unify smp_thermal_interrupt, prepare
Let them in same shape. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_intel_64.c20
-rw-r--r--arch/x86/kernel/cpu/mcheck/p4.c10
2 files changed, 24 insertions, 6 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index a5232b2c4ca0..922e3a482f6f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -16,6 +16,14 @@
16#include <asm/idle.h> 16#include <asm/idle.h>
17#include <asm/therm_throt.h> 17#include <asm/therm_throt.h>
18 18
19static void unexpected_thermal_interrupt(void)
20{
21 printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
22 smp_processor_id());
23 add_taint(TAINT_MACHINE_CHECK);
24}
25
26/* P4/Xeon Thermal transition interrupt handler: */
19static void intel_thermal_interrupt(void) 27static void intel_thermal_interrupt(void)
20{ 28{
21 __u64 msr_val; 29 __u64 msr_val;
@@ -25,14 +33,22 @@ static void intel_thermal_interrupt(void)
25 mce_log_therm_throt_event(msr_val); 33 mce_log_therm_throt_event(msr_val);
26} 34}
27 35
36/* Thermal interrupt handler for this CPU setup: */
37static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt;
38
28asmlinkage void smp_thermal_interrupt(void) 39asmlinkage void smp_thermal_interrupt(void)
29{ 40{
30 ack_APIC_irq();
31 exit_idle(); 41 exit_idle();
32 irq_enter(); 42 irq_enter();
33 intel_thermal_interrupt();
34 inc_irq_stat(irq_thermal_count); 43 inc_irq_stat(irq_thermal_count);
44 intel_thermal_interrupt();
35 irq_exit(); 45 irq_exit();
46 ack_APIC_irq();
47}
48
49void intel_set_thermal_handler(void)
50{
51 vendor_thermal_interrupt = intel_thermal_interrupt;
36} 52}
37 53
38/* 54/*
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index ddeed6e295af..75313f5b624e 100644
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -12,6 +12,7 @@
12#include <asm/processor.h> 12#include <asm/processor.h>
13#include <asm/system.h> 13#include <asm/system.h>
14#include <asm/apic.h> 14#include <asm/apic.h>
15#include <asm/idle.h>
15#include <asm/mce.h> 16#include <asm/mce.h>
16#include <asm/msr.h> 17#include <asm/msr.h>
17 18
@@ -47,10 +48,9 @@ static void intel_thermal_interrupt(void)
47{ 48{
48 __u64 msr_val; 49 __u64 msr_val;
49 50
50 ack_APIC_irq();
51
52 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); 51 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
53 therm_throt_process(msr_val & THERM_STATUS_PROCHOT); 52 if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
53 mce_log_therm_throt_event(msr_val);
54} 54}
55 55
56/* Thermal interrupt handler for this CPU setup: */ 56/* Thermal interrupt handler for this CPU setup: */
@@ -58,10 +58,12 @@ static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt;
58 58
59void smp_thermal_interrupt(struct pt_regs *regs) 59void smp_thermal_interrupt(struct pt_regs *regs)
60{ 60{
61 exit_idle();
61 irq_enter(); 62 irq_enter();
62 vendor_thermal_interrupt();
63 inc_irq_stat(irq_thermal_count); 63 inc_irq_stat(irq_thermal_count);
64 vendor_thermal_interrupt();
64 irq_exit(); 65 irq_exit();
66 ack_APIC_irq();
65} 67}
66 68
67void intel_set_thermal_handler(void) 69void intel_set_thermal_handler(void)