x86: merge smp_store_cpu_info

now that it is the same between arches, put it into smpboot.c

Signed-off-by: Glauber Costa <gcosta@redhat.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 77 insertions, 0 deletions

diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index b13b9d55f9ce..a157a5245923 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -45,6 +45,83 @@ unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
 /* representing cpus for which sibling maps can be computed */
 static cpumask_t cpu_sibling_setup_map;
 
+#ifdef CONFIG_X86_32
+/* Set if we find a B stepping CPU */
+int __cpuinitdata smp_b_stepping;
+#endif
+
+static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_32
+        /*
+         * Mask B, Pentium, but not Pentium MMX
+         */
+        if (c->x86_vendor == X86_VENDOR_INTEL &&
+            c->x86 == 5 &&
+            c->x86_mask >= 1 && c->x86_mask <= 4 &&
+            c->x86_model <= 3)
+                /*
+                 * Remember we have B step Pentia with bugs
+                 */
+                smp_b_stepping = 1;
+
+        /*
+         * Certain Athlons might work (for various values of 'work') in SMP
+         * but they are not certified as MP capable.
+         */
+        if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
+
+                if (num_possible_cpus() == 1)
+                        goto valid_k7;
+
+                /* Athlon 660/661 is valid. */
+                if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
+                    (c->x86_mask == 1)))
+                        goto valid_k7;
+
+                /* Duron 670 is valid */
+                if ((c->x86_model == 7) && (c->x86_mask == 0))
+                        goto valid_k7;
+
+                /*
+                 * Athlon 662, Duron 671, and Athlon >model 7 have capability
+                 * bit. It's worth noting that the A5 stepping (662) of some
+                 * Athlon XP's have the MP bit set.
+                 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
+                 * more.
+                 */
+                if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
+                    ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
+                     (c->x86_model > 7))
+                        if (cpu_has_mp)
+                                goto valid_k7;
+
+                /* If we get here, not a certified SMP capable AMD system. */
+                add_taint(TAINT_UNSAFE_SMP);
+        }
+
+valid_k7:
+        ;
+#endif
+}
+
+/*
+ * The bootstrap kernel entry code has set these up. Save them for
+ * a given CPU
+ */
+
+void __cpuinit smp_store_cpu_info(int id)
+{
+        struct cpuinfo_x86 *c = &cpu_data(id);
+
+        *c = boot_cpu_data;
+        c->cpu_index = id;
+        if (id != 0)
+                identify_secondary_cpu(c);
+        smp_apply_quirks(c);
+}
+
+
 void __cpuinit set_cpu_sibling_map(int cpu)
 {
         int i;