x86: prevent unconditional writes to DebugCtl MSR

Otherwise, enabling (or better, subsequent disabling) of single
stepping would cause a kernel oops on CPUs not having this MSR.

The patch could have been added a conditional to the MSR write in
user_disable_single_step(), but centralizing the updates seems safer
and (looking forward) better manageable.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Markus Metzger <markus.t.metzger@intel.com>

Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 1ffce14cff6e..4f40272474dd 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -563,12 +563,12 @@ static inline void __switch_to_xtra(struct task_struct *prev_p,
                 /* we clear debugctl to make sure DS
                  * is not in use when we change it */
                 debugctl = 0;
-                wrmsrl(MSR_IA32_DEBUGCTLMSR, 0);
+                update_debugctlmsr(0);
                 wrmsrl(MSR_IA32_DS_AREA, next->ds_area_msr);
         }
 
         if (next->debugctlmsr != debugctl)
-                wrmsrl(MSR_IA32_DEBUGCTLMSR, next->debugctlmsr);
+                update_debugctlmsr(next->debugctlmsr);
 
         if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
                 loaddebug(next, 0);