diff options
author | Andreas Herrmann <andreas.herrmann3@amd.com> | 2008-09-18 15:12:10 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2008-09-23 05:38:53 -0400 |
commit | 09bfeea13cea843fb03eaa96b5d891fa0abdcc90 (patch) | |
tree | 83777d26c3029d373d67f61f6d08884ae275cea3 /arch/x86/kernel/process.c | |
parent | a8d6829044901a67732904be5f1eacdf8539604f (diff) |
x86: c1e_idle: don't mark TSC unstable if CPU has invariant TSC
Impact: Functional TSC is marked unstable on AMD family 0x10 and 0x11 CPUs.
This would be wrong because for those CPUs "invariant TSC" means:
"The TSC counts at the same rate in all P-states, all C states, S0,
or S1"
(See "Processor BIOS and Kernel Developer's Guides" for those CPUs.)
[ tglx: Changed C1E to AMD C1E in the printks to avoid confusion
with Intel C1E ]
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/process.c')
-rw-r--r-- | arch/x86/kernel/process.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index d8c2a299bfe5..876e91890777 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c | |||
@@ -270,8 +270,9 @@ static void c1e_idle(void) | |||
270 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | 270 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); |
271 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { | 271 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
272 | c1e_detected = 1; | 272 | c1e_detected = 1; |
273 | mark_tsc_unstable("TSC halt in C1E"); | 273 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
274 | printk(KERN_INFO "System has C1E enabled\n"); | 274 | mark_tsc_unstable("TSC halt in AMD C1E"); |
275 | printk(KERN_INFO "System has AMD C1E enabled\n"); | ||
275 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E); | 276 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E); |
276 | } | 277 | } |
277 | } | 278 | } |