x86, gart: add resume handling

If GART IOMMU is used on an AMD64 system, the northbridge registers
related to it should be restored during resume so that memory is not
corrupted.  Make gart_resume() handle that as appropriate.

Ref. http://lkml.org/lkml/2008/5/25/96 and the following thread.

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 52 insertions, 5 deletions

diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 3710097f02eb..f505c3890358 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -549,14 +549,63 @@ static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
         return aper_base;
 }
 
+static void enable_gart_translations(void)
+{
+        int i;
+
+        for (i = 0; i < num_k8_northbridges; i++) {
+                struct pci_dev *dev = k8_northbridges[i];
+
+                enable_gart_translation(dev, __pa(agp_gatt_table));
+        }
+}
+
+/*
+ * If fix_up_north_bridges is set, the north bridges have to be fixed up on
+ * resume in the same way as they are handled in gart_iommu_hole_init().
+ */
+static bool fix_up_north_bridges;
+static u32 aperture_order;
+static u32 aperture_alloc;
+
+void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
+{
+        fix_up_north_bridges = true;
+        aperture_order = aper_order;
+        aperture_alloc = aper_alloc;
+}
+
 static int gart_resume(struct sys_device *dev)
 {
+        printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
+
+        if (fix_up_north_bridges) {
+                int i;
+
+                printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
+
+                for (i = 0; i < num_k8_northbridges; i++) {
+                        struct pci_dev *dev = k8_northbridges[i];
+
+                        /*
+                         * Don't enable translations just yet.  That is the next
+                         * step.  Restore the pre-suspend aperture settings.
+                         */
+                        pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
+                                                aperture_order << 1);
+                        pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
+                                                aperture_alloc >> 25);
+                }
+        }
+
+        enable_gart_translations();
+
         return 0;
 }
 
 static int gart_suspend(struct sys_device *dev, pm_message_t state)
 {
-        return -EINVAL;
+        return 0;
 }
 
 static struct sysdev_class gart_sysdev_class = {
@@ -614,16 +663,14 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
         memset(gatt, 0, gatt_size);
         agp_gatt_table = gatt;
 
-        for (i = 0; i < num_k8_northbridges; i++) {
-                dev = k8_northbridges[i];
-                enable_gart_translation(dev, __pa(gatt));
-        }
+        enable_gart_translations();
 
         error = sysdev_class_register(&gart_sysdev_class);
         if (!error)
                 error = sysdev_register(&device_gart);
         if (error)
                 panic("Could not register gart_sysdev -- would corrupt data on next suspend");
+
         flush_gart();
 
         printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",