diff options
author | Darrick J. Wong <djwong@us.ibm.com> | 2010-06-24 17:26:47 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2010-06-25 10:14:58 -0400 |
commit | 499a00e92dd9a75395081f595e681629eb1eebad (patch) | |
tree | 763ab3fff9baa4f7b09ae97379321df5ccfa2724 /arch/x86/kernel/pci-calgary_64.c | |
parent | 890ffedc7c3e95595926379e28ad2e16e7d7c613 (diff) |
x86, Calgary: Increase max PHB number
Newer systems (x3950M2) can have 48 PHBs per chassis and 8
chassis, so bump the limits up and provide an explanation
of the requirements for each class.
Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: Corinna Schultz <cschultz@linux.vnet.ibm.com>
Cc: <stable@kernel.org>
LKML-Reference: <20100624212647.GI15515@tux1.beaverton.ibm.com>
[ v2: Fixed build bug, added back PHBS_PER_CALGARY == 4 ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/pci-calgary_64.c')
-rw-r--r-- | arch/x86/kernel/pci-calgary_64.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c index fb99f7edb341..0b96b5589f08 100644 --- a/arch/x86/kernel/pci-calgary_64.c +++ b/arch/x86/kernel/pci-calgary_64.c | |||
@@ -103,11 +103,16 @@ int use_calgary __read_mostly = 0; | |||
103 | #define PMR_SOFTSTOPFAULT 0x40000000 | 103 | #define PMR_SOFTSTOPFAULT 0x40000000 |
104 | #define PMR_HARDSTOP 0x20000000 | 104 | #define PMR_HARDSTOP 0x20000000 |
105 | 105 | ||
106 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | 106 | /* |
107 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ | 107 | * The maximum PHB bus number. |
108 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ | 108 | * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384 |
109 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | 109 | * x3950M2: 4 chassis, 48 PHBs per chassis = 192 |
110 | #define PHBS_PER_CALGARY 4 | 110 | * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 |
111 | * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 | ||
112 | */ | ||
113 | #define MAX_PHB_BUS_NUM 384 | ||
114 | |||
115 | #define PHBS_PER_CALGARY 4 | ||
111 | 116 | ||
112 | /* register offsets in Calgary's internal register space */ | 117 | /* register offsets in Calgary's internal register space */ |
113 | static const unsigned long tar_offsets[] = { | 118 | static const unsigned long tar_offsets[] = { |