diff options
author | Jacob Pan <jacob.jun.pan@linux.intel.com> | 2010-05-19 15:01:24 -0400 |
---|---|---|
committer | H. Peter Anvin <hpa@linux.intel.com> | 2010-05-19 16:32:29 -0400 |
commit | a0c173bd8a3fd0541be8e4ef962170e48d8811c7 (patch) | |
tree | 514845a2d34bac5816b2a6cbdfa4cb2674b99434 /arch/x86/kernel/mrst.c | |
parent | 1dedefd1a066a795a87afca9c0236e1a94de9bf6 (diff) |
x86, mrst: add cpu type detection
Medfield is the follow-up of Moorestown, it is treated under the same
HW sub-architecture. However, we do need to know the CPU type in order
for some of the driver to act accordingly.
We also have different optimal clock configuration for each CPU type.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
LKML-Reference: <1274295685-6774-3-git-send-email-jacob.jun.pan@linux.intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/mrst.c')
-rw-r--r-- | arch/x86/kernel/mrst.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c index e796448f0eb5..ceaebeb5866f 100644 --- a/arch/x86/kernel/mrst.c +++ b/arch/x86/kernel/mrst.c | |||
@@ -27,6 +27,8 @@ | |||
27 | 27 | ||
28 | static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM]; | 28 | static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM]; |
29 | static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM]; | 29 | static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM]; |
30 | static int mrst_cpu_chip; | ||
31 | |||
30 | int sfi_mtimer_num; | 32 | int sfi_mtimer_num; |
31 | 33 | ||
32 | struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; | 34 | struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; |
@@ -216,6 +218,28 @@ static void __init mrst_setup_boot_clock(void) | |||
216 | setup_boot_APIC_clock(); | 218 | setup_boot_APIC_clock(); |
217 | }; | 219 | }; |
218 | 220 | ||
221 | int mrst_identify_cpu(void) | ||
222 | { | ||
223 | return mrst_cpu_chip; | ||
224 | } | ||
225 | EXPORT_SYMBOL_GPL(mrst_identify_cpu); | ||
226 | |||
227 | void __cpuinit mrst_arch_setup(void) | ||
228 | { | ||
229 | if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27) | ||
230 | mrst_cpu_chip = MRST_CPU_CHIP_PENWELL; | ||
231 | else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26) | ||
232 | mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT; | ||
233 | else { | ||
234 | pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n", | ||
235 | boot_cpu_data.x86, boot_cpu_data.x86_model); | ||
236 | mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT; | ||
237 | } | ||
238 | pr_debug("Moorestown CPU %s identified\n", | ||
239 | (mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ? | ||
240 | "Lincroft" : "Penwell"); | ||
241 | } | ||
242 | |||
219 | /* | 243 | /* |
220 | * Moorestown specific x86_init function overrides and early setup | 244 | * Moorestown specific x86_init function overrides and early setup |
221 | * calls. | 245 | * calls. |
@@ -230,6 +254,8 @@ void __init x86_mrst_early_setup(void) | |||
230 | 254 | ||
231 | x86_init.irqs.pre_vector_init = x86_init_noop; | 255 | x86_init.irqs.pre_vector_init = x86_init_noop; |
232 | 256 | ||
257 | x86_init.oem.arch_setup = mrst_arch_setup; | ||
258 | |||
233 | x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock; | 259 | x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock; |
234 | 260 | ||
235 | x86_platform.calibrate_tsc = mrst_calibrate_tsc; | 261 | x86_platform.calibrate_tsc = mrst_calibrate_tsc; |