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authorDmitry Adamushko <dmitry.adamushko@gmail.com>2008-08-19 18:22:26 -0400
committerIngo Molnar <mingo@elte.hu>2008-08-20 06:18:57 -0400
commitd45de40934897c6ee5b05141f7895bbb28512395 (patch)
tree1b4c4a011071d188a08d0f5bce8caf6b2b0a93c2 /arch/x86/kernel/microcode_intel.c
parent8343ef2437c599d30568e6b5a257a40bf2f4902b (diff)
x86-microcode: generic interface refactoring
This is the 1st patch in the series. Here the aim was to avoid any significant changes, logically-wise. So it's mainly about generic interface refactoring: e.g. make microcode_{intel,amd}.c more about arch-specific details and less about policies like make-sure-we-run-on-a-target-cpu (no more set_cpus_allowed_ptr() here) and generic synchronization (no more microcode_mutex here). All in all, more line have been deleted than added. 4 files changed, 145 insertions(+), 198 deletions(-) Signed-off-by: Dmitry Adamushko <dmitry.adamushko@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/microcode_intel.c')
-rw-r--r--arch/x86/kernel/microcode_intel.c91
1 files changed, 15 insertions, 76 deletions
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 6dd8907ff22e..c9b53202ba3d 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -122,46 +122,37 @@ MODULE_LICENSE("GPL");
122/* serialize access to the physical write to MSR 0x79 */ 122/* serialize access to the physical write to MSR 0x79 */
123static DEFINE_SPINLOCK(microcode_update_lock); 123static DEFINE_SPINLOCK(microcode_update_lock);
124 124
125/* no concurrent ->write()s are allowed on /dev/cpu/microcode */ 125static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
126extern struct mutex microcode_mutex;
127
128extern struct ucode_cpu_info ucode_cpu_info[NR_CPUS];
129
130static void collect_cpu_info(int cpu_num)
131{ 126{
132 struct cpuinfo_x86 *c = &cpu_data(cpu_num); 127 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
133 struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
134 unsigned int val[2]; 128 unsigned int val[2];
135 129
136 /* We should bind the task to the CPU */ 130 memset(csig, 0, sizeof(*csig));
137 BUG_ON(raw_smp_processor_id() != cpu_num);
138 uci->pf = uci->rev = 0;
139 uci->mc.mc_intel = NULL;
140 uci->valid = 1;
141 131
142 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || 132 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
143 cpu_has(c, X86_FEATURE_IA64)) { 133 cpu_has(c, X86_FEATURE_IA64)) {
144 printk(KERN_ERR "microcode: CPU%d not a capable Intel " 134 printk(KERN_ERR "microcode: CPU%d not a capable Intel "
145 "processor\n", cpu_num); 135 "processor\n", cpu_num);
146 uci->valid = 0; 136 return -1;
147 return;
148 } 137 }
149 138
150 uci->sig = cpuid_eax(0x00000001); 139 csig->sig = cpuid_eax(0x00000001);
151 140
152 if ((c->x86_model >= 5) || (c->x86 > 6)) { 141 if ((c->x86_model >= 5) || (c->x86 > 6)) {
153 /* get processor flags from MSR 0x17 */ 142 /* get processor flags from MSR 0x17 */
154 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); 143 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
155 uci->pf = 1 << ((val[1] >> 18) & 7); 144 csig->pf = 1 << ((val[1] >> 18) & 7);
156 } 145 }
157 146
158 wrmsr(MSR_IA32_UCODE_REV, 0, 0); 147 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
159 /* see notes above for revision 1.07. Apparent chip bug */ 148 /* see notes above for revision 1.07. Apparent chip bug */
160 sync_core(); 149 sync_core();
161 /* get the current revision from MSR 0x8B */ 150 /* get the current revision from MSR 0x8B */
162 rdmsr(MSR_IA32_UCODE_REV, val[0], uci->rev); 151 rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
163 pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n", 152 pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
164 uci->sig, uci->pf, uci->rev); 153 csig->sig, csig->pf, csig->rev);
154
155 return 0;
165} 156}
166 157
167static inline int microcode_update_match(int cpu_num, 158static inline int microcode_update_match(int cpu_num,
@@ -169,8 +160,8 @@ static inline int microcode_update_match(int cpu_num,
169{ 160{
170 struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; 161 struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
171 162
172 if (!sigmatch(sig, uci->sig, pf, uci->pf) 163 if (!sigmatch(sig, uci->cpu_sig.sig, pf, uci->cpu_sig.pf)
173 || mc_header->rev <= uci->rev) 164 || mc_header->rev <= uci->cpu_sig.rev)
174 return 0; 165 return 0;
175 return 1; 166 return 1;
176} 167}
@@ -289,7 +280,7 @@ static int get_matching_microcode(void *mc, int cpu)
289find: 280find:
290 pr_debug("microcode: CPU%d found a matching microcode update with" 281 pr_debug("microcode: CPU%d found a matching microcode update with"
291 " version 0x%x (current=0x%x)\n", 282 " version 0x%x (current=0x%x)\n",
292 cpu, mc_header->rev, uci->rev); 283 cpu, mc_header->rev, uci->cpu_sig.rev);
293 new_mc = vmalloc(total_size); 284 new_mc = vmalloc(total_size);
294 if (!new_mc) { 285 if (!new_mc) {
295 printk(KERN_ERR "microcode: error! Can not allocate memory\n"); 286 printk(KERN_ERR "microcode: error! Can not allocate memory\n");
@@ -335,16 +326,16 @@ static void apply_microcode(int cpu)
335 spin_unlock_irqrestore(&microcode_update_lock, flags); 326 spin_unlock_irqrestore(&microcode_update_lock, flags);
336 if (val[1] != uci->mc.mc_intel->hdr.rev) { 327 if (val[1] != uci->mc.mc_intel->hdr.rev) {
337 printk(KERN_ERR "microcode: CPU%d update from revision " 328 printk(KERN_ERR "microcode: CPU%d update from revision "
338 "0x%x to 0x%x failed\n", cpu_num, uci->rev, val[1]); 329 "0x%x to 0x%x failed\n", cpu_num, uci->cpu_sig.rev, val[1]);
339 return; 330 return;
340 } 331 }
341 printk(KERN_INFO "microcode: CPU%d updated from revision " 332 printk(KERN_INFO "microcode: CPU%d updated from revision "
342 "0x%x to 0x%x, date = %04x-%02x-%02x \n", 333 "0x%x to 0x%x, date = %04x-%02x-%02x \n",
343 cpu_num, uci->rev, val[1], 334 cpu_num, uci->cpu_sig.rev, val[1],
344 uci->mc.mc_intel->hdr.date & 0xffff, 335 uci->mc.mc_intel->hdr.date & 0xffff,
345 uci->mc.mc_intel->hdr.date >> 24, 336 uci->mc.mc_intel->hdr.date >> 24,
346 (uci->mc.mc_intel->hdr.date >> 16) & 0xff); 337 (uci->mc.mc_intel->hdr.date >> 16) & 0xff);
347 uci->rev = val[1]; 338 uci->cpu_sig.rev = val[1];
348} 339}
349 340
350#ifdef CONFIG_MICROCODE_OLD_INTERFACE 341#ifdef CONFIG_MICROCODE_OLD_INTERFACE
@@ -459,70 +450,18 @@ static int cpu_request_microcode(int cpu)
459 return error; 450 return error;
460} 451}
461 452
462static int apply_microcode_check_cpu(int cpu)
463{
464 struct cpuinfo_x86 *c = &cpu_data(cpu);
465 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
466 cpumask_t old;
467 unsigned int val[2];
468 int err = 0;
469
470 /* Check if the microcode is available */
471 if (!uci->mc.mc_intel)
472 return 0;
473
474 old = current->cpus_allowed;
475 set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
476
477 /* Check if the microcode we have in memory matches the CPU */
478 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
479 cpu_has(c, X86_FEATURE_IA64) || uci->sig != cpuid_eax(0x00000001))
480 err = -EINVAL;
481
482 if (!err && ((c->x86_model >= 5) || (c->x86 > 6))) {
483 /* get processor flags from MSR 0x17 */
484 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
485 if (uci->pf != (1 << ((val[1] >> 18) & 7)))
486 err = -EINVAL;
487 }
488
489 if (!err) {
490 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
491 /* see notes above for revision 1.07. Apparent chip bug */
492 sync_core();
493 /* get the current revision from MSR 0x8B */
494 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
495 if (uci->rev != val[1])
496 err = -EINVAL;
497 }
498
499 if (!err)
500 apply_microcode(cpu);
501 else
502 printk(KERN_ERR "microcode: Could not apply microcode to CPU%d:"
503 " sig=0x%x, pf=0x%x, rev=0x%x\n",
504 cpu, uci->sig, uci->pf, uci->rev);
505
506 set_cpus_allowed_ptr(current, &old);
507 return err;
508}
509
510static void microcode_fini_cpu(int cpu) 453static void microcode_fini_cpu(int cpu)
511{ 454{
512 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 455 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
513 456
514 mutex_lock(&microcode_mutex);
515 uci->valid = 0;
516 vfree(uci->mc.mc_intel); 457 vfree(uci->mc.mc_intel);
517 uci->mc.mc_intel = NULL; 458 uci->mc.mc_intel = NULL;
518 mutex_unlock(&microcode_mutex);
519} 459}
520 460
521static struct microcode_ops microcode_intel_ops = { 461static struct microcode_ops microcode_intel_ops = {
522 .get_next_ucode = get_next_ucode, 462 .get_next_ucode = get_next_ucode,
523 .get_matching_microcode = get_matching_microcode, 463 .get_matching_microcode = get_matching_microcode,
524 .microcode_sanity_check = microcode_sanity_check, 464 .microcode_sanity_check = microcode_sanity_check,
525 .apply_microcode_check_cpu = apply_microcode_check_cpu,
526 .cpu_request_microcode = cpu_request_microcode, 465 .cpu_request_microcode = cpu_request_microcode,
527 .collect_cpu_info = collect_cpu_info, 466 .collect_cpu_info = collect_cpu_info,
528 .apply_microcode = apply_microcode, 467 .apply_microcode = apply_microcode,