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authorAndreas Herrmann <andreas.herrmann3@amd.com>2010-09-17 12:03:43 -0400
committerH. Peter Anvin <hpa@linux.intel.com>2010-09-20 17:22:58 -0400
commit23ac4ae827e6264e21b898f2cd3f601450aa02a6 (patch)
treed2948304b5be996cbf8ad15ade2e3b3baa760617 /arch/x86/kernel/k8.c
parent900f9ac9f12dc3dd6fc8e33e16df172eafcaead6 (diff)
x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB
The file names are somehow misleading as the code is not specific to AMD K8 CPUs anymore. The files accomodate code for other AMD CPU northbridges as well. Same is true for the config option which is valid for AMD CPU northbridges in general and not specific to K8. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160343.GD4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/k8.c')
-rw-r--r--arch/x86/kernel/k8.c145
1 files changed, 0 insertions, 145 deletions
diff --git a/arch/x86/kernel/k8.c b/arch/x86/kernel/k8.c
deleted file mode 100644
index 5de1b6b39639..000000000000
--- a/arch/x86/kernel/k8.c
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * Shared support code for AMD K8 northbridges and derivates.
3 * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
4 */
5#include <linux/types.h>
6#include <linux/slab.h>
7#include <linux/init.h>
8#include <linux/errno.h>
9#include <linux/module.h>
10#include <linux/spinlock.h>
11#include <asm/k8.h>
12
13static u32 *flush_words;
14
15struct pci_device_id k8_nb_ids[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
17 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
18 {}
19};
20EXPORT_SYMBOL(k8_nb_ids);
21
22struct k8_northbridge_info k8_northbridges;
23EXPORT_SYMBOL(k8_northbridges);
24
25static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
26{
27 do {
28 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
29 if (!dev)
30 break;
31 } while (!pci_match_id(&k8_nb_ids[0], dev));
32 return dev;
33}
34
35int cache_k8_northbridges(void)
36{
37 int i;
38 struct pci_dev *dev;
39
40 if (k8_northbridges.num)
41 return 0;
42
43 dev = NULL;
44 while ((dev = next_k8_northbridge(dev)) != NULL)
45 k8_northbridges.num++;
46
47 /* some CPU families (e.g. family 0x11) do not support GART */
48 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
49 k8_northbridges.gart_supported = 1;
50
51 k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
52 sizeof(void *), GFP_KERNEL);
53 if (!k8_northbridges.nb_misc)
54 return -ENOMEM;
55
56 if (!k8_northbridges.num) {
57 k8_northbridges.nb_misc[0] = NULL;
58 return 0;
59 }
60
61 if (k8_northbridges.gart_supported) {
62 flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
63 GFP_KERNEL);
64 if (!flush_words) {
65 kfree(k8_northbridges.nb_misc);
66 return -ENOMEM;
67 }
68 }
69
70 dev = NULL;
71 i = 0;
72 while ((dev = next_k8_northbridge(dev)) != NULL) {
73 k8_northbridges.nb_misc[i] = dev;
74 if (k8_northbridges.gart_supported)
75 pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
76 }
77 k8_northbridges.nb_misc[i] = NULL;
78 return 0;
79}
80EXPORT_SYMBOL_GPL(cache_k8_northbridges);
81
82/* Ignores subdevice/subvendor but as far as I can figure out
83 they're useless anyways */
84int __init early_is_k8_nb(u32 device)
85{
86 struct pci_device_id *id;
87 u32 vendor = device & 0xffff;
88 device >>= 16;
89 for (id = k8_nb_ids; id->vendor; id++)
90 if (vendor == id->vendor && device == id->device)
91 return 1;
92 return 0;
93}
94
95void k8_flush_garts(void)
96{
97 int flushed, i;
98 unsigned long flags;
99 static DEFINE_SPINLOCK(gart_lock);
100
101 if (!k8_northbridges.gart_supported)
102 return;
103
104 /* Avoid races between AGP and IOMMU. In theory it's not needed
105 but I'm not sure if the hardware won't lose flush requests
106 when another is pending. This whole thing is so expensive anyways
107 that it doesn't matter to serialize more. -AK */
108 spin_lock_irqsave(&gart_lock, flags);
109 flushed = 0;
110 for (i = 0; i < k8_northbridges.num; i++) {
111 pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
112 flush_words[i]|1);
113 flushed++;
114 }
115 for (i = 0; i < k8_northbridges.num; i++) {
116 u32 w;
117 /* Make sure the hardware actually executed the flush*/
118 for (;;) {
119 pci_read_config_dword(k8_northbridges.nb_misc[i],
120 0x9c, &w);
121 if (!(w & 1))
122 break;
123 cpu_relax();
124 }
125 }
126 spin_unlock_irqrestore(&gart_lock, flags);
127 if (!flushed)
128 printk("nothing to flush?\n");
129}
130EXPORT_SYMBOL_GPL(k8_flush_garts);
131
132static __init int init_k8_nbs(void)
133{
134 int err = 0;
135
136 err = cache_k8_northbridges();
137
138 if (err < 0)
139 printk(KERN_NOTICE "K8 NB: Cannot enumerate AMD northbridges.\n");
140
141 return err;
142}
143
144/* This has to go after the PCI subsystem */
145fs_initcall(init_k8_nbs);