diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-01-27 22:09:58 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-01-28 17:20:13 -0500 |
commit | 9b5bc8dc12421a4b17047061f473d85c1797d543 (patch) | |
tree | 69799378fb9e55dd8c23ceb39c646d7bf47523f8 /arch/x86/kernel/io_apic.c | |
parent | f8987a1093cc7a896137e264c24e04d4048e9f95 (diff) |
x86, apic: remove IRQ_DEST_MODE / IRQ_DELIVERY_MODE
Remove the wrapper macros IRQ_DEST_MODE and IRQ_DELIVERY_MODE.
The typical 32-bit and the 64-bit build all dereference via the genapic,
so it's pointless to hide that indirection via these ugly macros.
Furthermore, it also obscures subarchitecture details.
So replace it with apic->irq_dest_mode / etc. accesses.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/io_apic.c')
-rw-r--r-- | arch/x86/kernel/io_apic.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c index 5f967b9c9afd..301b6571d700 100644 --- a/arch/x86/kernel/io_apic.c +++ b/arch/x86/kernel/io_apic.c | |||
@@ -1514,9 +1514,9 @@ static int setup_ioapic_entry(int apic_id, int irq, | |||
1514 | memset(&irte, 0, sizeof(irte)); | 1514 | memset(&irte, 0, sizeof(irte)); |
1515 | 1515 | ||
1516 | irte.present = 1; | 1516 | irte.present = 1; |
1517 | irte.dst_mode = IRQ_DEST_MODE; | 1517 | irte.dst_mode = apic->irq_dest_mode; |
1518 | irte.trigger_mode = trigger; | 1518 | irte.trigger_mode = trigger; |
1519 | irte.dlvry_mode = IRQ_DELIVERY_MODE; | 1519 | irte.dlvry_mode = apic->irq_delivery_mode; |
1520 | irte.vector = vector; | 1520 | irte.vector = vector; |
1521 | irte.dest_id = IRTE_DEST(destination); | 1521 | irte.dest_id = IRTE_DEST(destination); |
1522 | 1522 | ||
@@ -1529,8 +1529,8 @@ static int setup_ioapic_entry(int apic_id, int irq, | |||
1529 | } else | 1529 | } else |
1530 | #endif | 1530 | #endif |
1531 | { | 1531 | { |
1532 | entry->delivery_mode = IRQ_DELIVERY_MODE; | 1532 | entry->delivery_mode = apic->irq_delivery_mode; |
1533 | entry->dest_mode = IRQ_DEST_MODE; | 1533 | entry->dest_mode = apic->irq_dest_mode; |
1534 | entry->dest = destination; | 1534 | entry->dest = destination; |
1535 | } | 1535 | } |
1536 | 1536 | ||
@@ -1659,10 +1659,10 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, | |||
1659 | * We use logical delivery to get the timer IRQ | 1659 | * We use logical delivery to get the timer IRQ |
1660 | * to the first CPU. | 1660 | * to the first CPU. |
1661 | */ | 1661 | */ |
1662 | entry.dest_mode = IRQ_DEST_MODE; | 1662 | entry.dest_mode = apic->irq_dest_mode; |
1663 | entry.mask = 1; /* mask IRQ now */ | 1663 | entry.mask = 1; /* mask IRQ now */ |
1664 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); | 1664 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1665 | entry.delivery_mode = IRQ_DELIVERY_MODE; | 1665 | entry.delivery_mode = apic->irq_delivery_mode; |
1666 | entry.polarity = 0; | 1666 | entry.polarity = 0; |
1667 | entry.trigger = 0; | 1667 | entry.trigger = 0; |
1668 | entry.vector = vector; | 1668 | entry.vector = vector; |
@@ -3279,9 +3279,9 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms | |||
3279 | memset (&irte, 0, sizeof(irte)); | 3279 | memset (&irte, 0, sizeof(irte)); |
3280 | 3280 | ||
3281 | irte.present = 1; | 3281 | irte.present = 1; |
3282 | irte.dst_mode = IRQ_DEST_MODE; | 3282 | irte.dst_mode = apic->irq_dest_mode; |
3283 | irte.trigger_mode = 0; /* edge */ | 3283 | irte.trigger_mode = 0; /* edge */ |
3284 | irte.dlvry_mode = IRQ_DELIVERY_MODE; | 3284 | irte.dlvry_mode = apic->irq_delivery_mode; |
3285 | irte.vector = cfg->vector; | 3285 | irte.vector = cfg->vector; |
3286 | irte.dest_id = IRTE_DEST(dest); | 3286 | irte.dest_id = IRTE_DEST(dest); |
3287 | 3287 | ||
@@ -3299,10 +3299,10 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms | |||
3299 | msg->address_hi = MSI_ADDR_BASE_HI; | 3299 | msg->address_hi = MSI_ADDR_BASE_HI; |
3300 | msg->address_lo = | 3300 | msg->address_lo = |
3301 | MSI_ADDR_BASE_LO | | 3301 | MSI_ADDR_BASE_LO | |
3302 | ((IRQ_DEST_MODE == 0) ? | 3302 | ((apic->irq_dest_mode == 0) ? |
3303 | MSI_ADDR_DEST_MODE_PHYSICAL: | 3303 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3304 | MSI_ADDR_DEST_MODE_LOGICAL) | | 3304 | MSI_ADDR_DEST_MODE_LOGICAL) | |
3305 | ((IRQ_DELIVERY_MODE != dest_LowestPrio) ? | 3305 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
3306 | MSI_ADDR_REDIRECTION_CPU: | 3306 | MSI_ADDR_REDIRECTION_CPU: |
3307 | MSI_ADDR_REDIRECTION_LOWPRI) | | 3307 | MSI_ADDR_REDIRECTION_LOWPRI) | |
3308 | MSI_ADDR_DEST_ID(dest); | 3308 | MSI_ADDR_DEST_ID(dest); |
@@ -3310,7 +3310,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms | |||
3310 | msg->data = | 3310 | msg->data = |
3311 | MSI_DATA_TRIGGER_EDGE | | 3311 | MSI_DATA_TRIGGER_EDGE | |
3312 | MSI_DATA_LEVEL_ASSERT | | 3312 | MSI_DATA_LEVEL_ASSERT | |
3313 | ((IRQ_DELIVERY_MODE != dest_LowestPrio) ? | 3313 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
3314 | MSI_DATA_DELIVERY_FIXED: | 3314 | MSI_DATA_DELIVERY_FIXED: |
3315 | MSI_DATA_DELIVERY_LOWPRI) | | 3315 | MSI_DATA_DELIVERY_LOWPRI) | |
3316 | MSI_DATA_VECTOR(cfg->vector); | 3316 | MSI_DATA_VECTOR(cfg->vector); |
@@ -3711,11 +3711,11 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |||
3711 | HT_IRQ_LOW_BASE | | 3711 | HT_IRQ_LOW_BASE | |
3712 | HT_IRQ_LOW_DEST_ID(dest) | | 3712 | HT_IRQ_LOW_DEST_ID(dest) | |
3713 | HT_IRQ_LOW_VECTOR(cfg->vector) | | 3713 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
3714 | ((IRQ_DEST_MODE == 0) ? | 3714 | ((apic->irq_dest_mode == 0) ? |
3715 | HT_IRQ_LOW_DM_PHYSICAL : | 3715 | HT_IRQ_LOW_DM_PHYSICAL : |
3716 | HT_IRQ_LOW_DM_LOGICAL) | | 3716 | HT_IRQ_LOW_DM_LOGICAL) | |
3717 | HT_IRQ_LOW_RQEOI_EDGE | | 3717 | HT_IRQ_LOW_RQEOI_EDGE | |
3718 | ((IRQ_DELIVERY_MODE != dest_LowestPrio) ? | 3718 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
3719 | HT_IRQ_LOW_MT_FIXED : | 3719 | HT_IRQ_LOW_MT_FIXED : |
3720 | HT_IRQ_LOW_MT_ARBITRATED) | | 3720 | HT_IRQ_LOW_MT_ARBITRATED) | |
3721 | HT_IRQ_LOW_IRQ_MASKED; | 3721 | HT_IRQ_LOW_IRQ_MASKED; |
@@ -3763,8 +3763,8 @@ int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |||
3763 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | 3763 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3764 | 3764 | ||
3765 | entry->vector = cfg->vector; | 3765 | entry->vector = cfg->vector; |
3766 | entry->delivery_mode = IRQ_DELIVERY_MODE; | 3766 | entry->delivery_mode = apic->irq_delivery_mode; |
3767 | entry->dest_mode = IRQ_DEST_MODE; | 3767 | entry->dest_mode = apic->irq_dest_mode; |
3768 | entry->polarity = 0; | 3768 | entry->polarity = 0; |
3769 | entry->trigger = 0; | 3769 | entry->trigger = 0; |
3770 | entry->mask = 0; | 3770 | entry->mask = 0; |