x86: do not promote TM3x00/TM5x00 to i686-class

We have been promoting Transmeta TM3x00/TM5x00 chips to i686-class
based on the notion that they contain all the user-space visible
features of an i686-class chip.  However, this is not actually true:
they lack the EA-taking long NOPs (0F 1F /0).  Since this is a
userspace-visible incompatibility, downgrade these CPUs to the
manufacturer-defined i586 level.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

1 files changed, 0 insertions, 7 deletions

diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index 200fb3f9ebfb..e8b422c1c512 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -76,13 +76,6 @@ static void __cpuinit init_transmeta(struct cpuinfo_x86 *c)
         /* All Transmeta CPUs have a constant TSC */
         set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
         
-        /* If we can run i686 user-space code, call us an i686 */
-#define USER686 ((1 << X86_FEATURE_TSC)|\
-                 (1 << X86_FEATURE_CX8)|\
-                 (1 << X86_FEATURE_CMOV))
-        if (c->x86 == 5 && (c->x86_capability[0] & USER686) == USER686)
-                c->x86 = 6;
-
 #ifdef CONFIG_SYSCTL
         /* randomize_va_space slows us down enormously;
            it probably triggers retranslation of x86->native bytecode */