aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86/kernel/cpu
diff options
context:
space:
mode:
authorDave Jones <davej@redhat.com>2011-05-19 18:51:07 -0400
committerDave Jones <davej@redhat.com>2011-05-19 18:51:07 -0400
commitbb0a56ecc4ba2a3db1b6ea6949c309886e3447d3 (patch)
tree680b1307d7d9c1a188b7483875f7a3287d8b51a0 /arch/x86/kernel/cpu
parent1a8e1463a49aaa452da1cefe184a00d4df47f1ef (diff)
[CPUFREQ] Move x86 drivers to drivers/cpufreq/
Signed-off-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r--arch/x86/kernel/cpu/Makefile1
-rw-r--r--arch/x86/kernel/cpu/cpufreq/Kconfig266
-rw-r--r--arch/x86/kernel/cpu/cpufreq/Makefile21
-rw-r--r--arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c773
-rw-r--r--arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c444
-rw-r--r--arch/x86/kernel/cpu/cpufreq/e_powersaver.c367
-rw-r--r--arch/x86/kernel/cpu/cpufreq/elanfreq.c309
-rw-r--r--arch/x86/kernel/cpu/cpufreq/gx-suspmod.c514
-rw-r--r--arch/x86/kernel/cpu/cpufreq/longhaul.c1024
-rw-r--r--arch/x86/kernel/cpu/cpufreq/longhaul.h353
-rw-r--r--arch/x86/kernel/cpu/cpufreq/longrun.c324
-rw-r--r--arch/x86/kernel/cpu/cpufreq/mperf.c51
-rw-r--r--arch/x86/kernel/cpu/cpufreq/mperf.h9
-rw-r--r--arch/x86/kernel/cpu/cpufreq/p4-clockmod.c329
-rw-r--r--arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c621
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k6.c261
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k7.c747
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k7.h43
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.c1607
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.h222
-rw-r--r--arch/x86/kernel/cpu/cpufreq/sc520_freq.c192
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c633
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-ich.c448
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-lib.c478
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-lib.h49
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-smi.c464
26 files changed, 0 insertions, 10550 deletions
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 3f0ebe429a01..6042981d0309 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -30,7 +30,6 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
30 30
31obj-$(CONFIG_X86_MCE) += mcheck/ 31obj-$(CONFIG_X86_MCE) += mcheck/
32obj-$(CONFIG_MTRR) += mtrr/ 32obj-$(CONFIG_MTRR) += mtrr/
33obj-$(CONFIG_CPU_FREQ) += cpufreq/
34 33
35obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o 34obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o
36 35
diff --git a/arch/x86/kernel/cpu/cpufreq/Kconfig b/arch/x86/kernel/cpu/cpufreq/Kconfig
deleted file mode 100644
index 870e6cc6ad28..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/Kconfig
+++ /dev/null
@@ -1,266 +0,0 @@
1#
2# CPU Frequency scaling
3#
4
5menu "CPU Frequency scaling"
6
7source "drivers/cpufreq/Kconfig"
8
9if CPU_FREQ
10
11comment "CPUFreq processor drivers"
12
13config X86_PCC_CPUFREQ
14 tristate "Processor Clocking Control interface driver"
15 depends on ACPI && ACPI_PROCESSOR
16 help
17 This driver adds support for the PCC interface.
18
19 For details, take a look at:
20 <file:Documentation/cpu-freq/pcc-cpufreq.txt>.
21
22 To compile this driver as a module, choose M here: the
23 module will be called pcc-cpufreq.
24
25 If in doubt, say N.
26
27config X86_ACPI_CPUFREQ
28 tristate "ACPI Processor P-States driver"
29 select CPU_FREQ_TABLE
30 depends on ACPI_PROCESSOR
31 help
32 This driver adds a CPUFreq driver which utilizes the ACPI
33 Processor Performance States.
34 This driver also supports Intel Enhanced Speedstep.
35
36 To compile this driver as a module, choose M here: the
37 module will be called acpi-cpufreq.
38
39 For details, take a look at <file:Documentation/cpu-freq/>.
40
41 If in doubt, say N.
42
43config ELAN_CPUFREQ
44 tristate "AMD Elan SC400 and SC410"
45 select CPU_FREQ_TABLE
46 depends on X86_ELAN
47 ---help---
48 This adds the CPUFreq driver for AMD Elan SC400 and SC410
49 processors.
50
51 You need to specify the processor maximum speed as boot
52 parameter: elanfreq=maxspeed (in kHz) or as module
53 parameter "max_freq".
54
55 For details, take a look at <file:Documentation/cpu-freq/>.
56
57 If in doubt, say N.
58
59config SC520_CPUFREQ
60 tristate "AMD Elan SC520"
61 select CPU_FREQ_TABLE
62 depends on X86_ELAN
63 ---help---
64 This adds the CPUFreq driver for AMD Elan SC520 processor.
65
66 For details, take a look at <file:Documentation/cpu-freq/>.
67
68 If in doubt, say N.
69
70
71config X86_POWERNOW_K6
72 tristate "AMD Mobile K6-2/K6-3 PowerNow!"
73 select CPU_FREQ_TABLE
74 depends on X86_32
75 help
76 This adds the CPUFreq driver for mobile AMD K6-2+ and mobile
77 AMD K6-3+ processors.
78
79 For details, take a look at <file:Documentation/cpu-freq/>.
80
81 If in doubt, say N.
82
83config X86_POWERNOW_K7
84 tristate "AMD Mobile Athlon/Duron PowerNow!"
85 select CPU_FREQ_TABLE
86 depends on X86_32
87 help
88 This adds the CPUFreq driver for mobile AMD K7 mobile processors.
89
90 For details, take a look at <file:Documentation/cpu-freq/>.
91
92 If in doubt, say N.
93
94config X86_POWERNOW_K7_ACPI
95 bool
96 depends on X86_POWERNOW_K7 && ACPI_PROCESSOR
97 depends on !(X86_POWERNOW_K7 = y && ACPI_PROCESSOR = m)
98 depends on X86_32
99 default y
100
101config X86_POWERNOW_K8
102 tristate "AMD Opteron/Athlon64 PowerNow!"
103 select CPU_FREQ_TABLE
104 depends on ACPI && ACPI_PROCESSOR
105 help
106 This adds the CPUFreq driver for K8/K10 Opteron/Athlon64 processors.
107
108 To compile this driver as a module, choose M here: the
109 module will be called powernow-k8.
110
111 For details, take a look at <file:Documentation/cpu-freq/>.
112
113config X86_GX_SUSPMOD
114 tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation"
115 depends on X86_32 && PCI
116 help
117 This add the CPUFreq driver for NatSemi Geode processors which
118 support suspend modulation.
119
120 For details, take a look at <file:Documentation/cpu-freq/>.
121
122 If in doubt, say N.
123
124config X86_SPEEDSTEP_CENTRINO
125 tristate "Intel Enhanced SpeedStep (deprecated)"
126 select CPU_FREQ_TABLE
127 select X86_SPEEDSTEP_CENTRINO_TABLE if X86_32
128 depends on X86_32 || (X86_64 && ACPI_PROCESSOR)
129 help
130 This is deprecated and this functionality is now merged into
131 acpi_cpufreq (X86_ACPI_CPUFREQ). Use that driver instead of
132 speedstep_centrino.
133 This adds the CPUFreq driver for Enhanced SpeedStep enabled
134 mobile CPUs. This means Intel Pentium M (Centrino) CPUs
135 or 64bit enabled Intel Xeons.
136
137 To compile this driver as a module, choose M here: the
138 module will be called speedstep-centrino.
139
140 For details, take a look at <file:Documentation/cpu-freq/>.
141
142 If in doubt, say N.
143
144config X86_SPEEDSTEP_CENTRINO_TABLE
145 bool "Built-in tables for Banias CPUs"
146 depends on X86_32 && X86_SPEEDSTEP_CENTRINO
147 default y
148 help
149 Use built-in tables for Banias CPUs if ACPI encoding
150 is not available.
151
152 If in doubt, say N.
153
154config X86_SPEEDSTEP_ICH
155 tristate "Intel Speedstep on ICH-M chipsets (ioport interface)"
156 select CPU_FREQ_TABLE
157 depends on X86_32
158 help
159 This adds the CPUFreq driver for certain mobile Intel Pentium III
160 (Coppermine), all mobile Intel Pentium III-M (Tualatin) and all
161 mobile Intel Pentium 4 P4-M on systems which have an Intel ICH2,
162 ICH3 or ICH4 southbridge.
163
164 For details, take a look at <file:Documentation/cpu-freq/>.
165
166 If in doubt, say N.
167
168config X86_SPEEDSTEP_SMI
169 tristate "Intel SpeedStep on 440BX/ZX/MX chipsets (SMI interface)"
170 select CPU_FREQ_TABLE
171 depends on X86_32 && EXPERIMENTAL
172 help
173 This adds the CPUFreq driver for certain mobile Intel Pentium III
174 (Coppermine), all mobile Intel Pentium III-M (Tualatin)
175 on systems which have an Intel 440BX/ZX/MX southbridge.
176
177 For details, take a look at <file:Documentation/cpu-freq/>.
178
179 If in doubt, say N.
180
181config X86_P4_CLOCKMOD
182 tristate "Intel Pentium 4 clock modulation"
183 select CPU_FREQ_TABLE
184 help
185 This adds the CPUFreq driver for Intel Pentium 4 / XEON
186 processors. When enabled it will lower CPU temperature by skipping
187 clocks.
188
189 This driver should be only used in exceptional
190 circumstances when very low power is needed because it causes severe
191 slowdowns and noticeable latencies. Normally Speedstep should be used
192 instead.
193
194 To compile this driver as a module, choose M here: the
195 module will be called p4-clockmod.
196
197 For details, take a look at <file:Documentation/cpu-freq/>.
198
199 Unless you are absolutely sure say N.
200
201config X86_CPUFREQ_NFORCE2
202 tristate "nVidia nForce2 FSB changing"
203 depends on X86_32 && EXPERIMENTAL
204 help
205 This adds the CPUFreq driver for FSB changing on nVidia nForce2
206 platforms.
207
208 For details, take a look at <file:Documentation/cpu-freq/>.
209
210 If in doubt, say N.
211
212config X86_LONGRUN
213 tristate "Transmeta LongRun"
214 depends on X86_32
215 help
216 This adds the CPUFreq driver for Transmeta Crusoe and Efficeon processors
217 which support LongRun.
218
219 For details, take a look at <file:Documentation/cpu-freq/>.
220
221 If in doubt, say N.
222
223config X86_LONGHAUL
224 tristate "VIA Cyrix III Longhaul"
225 select CPU_FREQ_TABLE
226 depends on X86_32 && ACPI_PROCESSOR
227 help
228 This adds the CPUFreq driver for VIA Samuel/CyrixIII,
229 VIA Cyrix Samuel/C3, VIA Cyrix Ezra and VIA Cyrix Ezra-T
230 processors.
231
232 For details, take a look at <file:Documentation/cpu-freq/>.
233
234 If in doubt, say N.
235
236config X86_E_POWERSAVER
237 tristate "VIA C7 Enhanced PowerSaver (DANGEROUS)"
238 select CPU_FREQ_TABLE
239 depends on X86_32 && EXPERIMENTAL
240 help
241 This adds the CPUFreq driver for VIA C7 processors. However, this driver
242 does not have any safeguards to prevent operating the CPU out of spec
243 and is thus considered dangerous. Please use the regular ACPI cpufreq
244 driver, enabled by CONFIG_X86_ACPI_CPUFREQ.
245
246 If in doubt, say N.
247
248comment "shared options"
249
250config X86_SPEEDSTEP_LIB
251 tristate
252 default (X86_SPEEDSTEP_ICH || X86_SPEEDSTEP_SMI || X86_P4_CLOCKMOD)
253
254config X86_SPEEDSTEP_RELAXED_CAP_CHECK
255 bool "Relaxed speedstep capability checks"
256 depends on X86_32 && (X86_SPEEDSTEP_SMI || X86_SPEEDSTEP_ICH)
257 help
258 Don't perform all checks for a speedstep capable system which would
259 normally be done. Some ancient or strange systems, though speedstep
260 capable, don't always indicate that they are speedstep capable. This
261 option lets the probing code bypass some of those checks if the
262 parameter "relaxed_check=1" is passed to the module.
263
264endif # CPU_FREQ
265
266endmenu
diff --git a/arch/x86/kernel/cpu/cpufreq/Makefile b/arch/x86/kernel/cpu/cpufreq/Makefile
deleted file mode 100644
index bd54bf67e6fb..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
1# Link order matters. K8 is preferred to ACPI because of firmware bugs in early
2# K8 systems. ACPI is preferred to all other hardware-specific drivers.
3# speedstep-* is preferred over p4-clockmod.
4
5obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o mperf.o
6obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o mperf.o
7obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o
8obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o
9obj-$(CONFIG_X86_POWERNOW_K7) += powernow-k7.o
10obj-$(CONFIG_X86_LONGHAUL) += longhaul.o
11obj-$(CONFIG_X86_E_POWERSAVER) += e_powersaver.o
12obj-$(CONFIG_ELAN_CPUFREQ) += elanfreq.o
13obj-$(CONFIG_SC520_CPUFREQ) += sc520_freq.o
14obj-$(CONFIG_X86_LONGRUN) += longrun.o
15obj-$(CONFIG_X86_GX_SUSPMOD) += gx-suspmod.o
16obj-$(CONFIG_X86_SPEEDSTEP_ICH) += speedstep-ich.o
17obj-$(CONFIG_X86_SPEEDSTEP_LIB) += speedstep-lib.o
18obj-$(CONFIG_X86_SPEEDSTEP_SMI) += speedstep-smi.o
19obj-$(CONFIG_X86_SPEEDSTEP_CENTRINO) += speedstep-centrino.o
20obj-$(CONFIG_X86_P4_CLOCKMOD) += p4-clockmod.o
21obj-$(CONFIG_X86_CPUFREQ_NFORCE2) += cpufreq-nforce2.o
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
deleted file mode 100644
index 4e04e1274388..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ /dev/null
@@ -1,773 +0,0 @@
1/*
2 * acpi-cpufreq.c - ACPI Processor P-States Driver
3 *
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com>
8 *
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 *
25 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/init.h>
31#include <linux/smp.h>
32#include <linux/sched.h>
33#include <linux/cpufreq.h>
34#include <linux/compiler.h>
35#include <linux/dmi.h>
36#include <linux/slab.h>
37
38#include <linux/acpi.h>
39#include <linux/io.h>
40#include <linux/delay.h>
41#include <linux/uaccess.h>
42
43#include <acpi/processor.h>
44
45#include <asm/msr.h>
46#include <asm/processor.h>
47#include <asm/cpufeature.h>
48#include "mperf.h"
49
50MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski");
51MODULE_DESCRIPTION("ACPI Processor P-States Driver");
52MODULE_LICENSE("GPL");
53
54enum {
55 UNDEFINED_CAPABLE = 0,
56 SYSTEM_INTEL_MSR_CAPABLE,
57 SYSTEM_IO_CAPABLE,
58};
59
60#define INTEL_MSR_RANGE (0xffff)
61
62struct acpi_cpufreq_data {
63 struct acpi_processor_performance *acpi_data;
64 struct cpufreq_frequency_table *freq_table;
65 unsigned int resume;
66 unsigned int cpu_feature;
67};
68
69static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data);
70
71/* acpi_perf_data is a pointer to percpu data. */
72static struct acpi_processor_performance __percpu *acpi_perf_data;
73
74static struct cpufreq_driver acpi_cpufreq_driver;
75
76static unsigned int acpi_pstate_strict;
77
78static int check_est_cpu(unsigned int cpuid)
79{
80 struct cpuinfo_x86 *cpu = &cpu_data(cpuid);
81
82 return cpu_has(cpu, X86_FEATURE_EST);
83}
84
85static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data)
86{
87 struct acpi_processor_performance *perf;
88 int i;
89
90 perf = data->acpi_data;
91
92 for (i = 0; i < perf->state_count; i++) {
93 if (value == perf->states[i].status)
94 return data->freq_table[i].frequency;
95 }
96 return 0;
97}
98
99static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data)
100{
101 int i;
102 struct acpi_processor_performance *perf;
103
104 msr &= INTEL_MSR_RANGE;
105 perf = data->acpi_data;
106
107 for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
108 if (msr == perf->states[data->freq_table[i].index].status)
109 return data->freq_table[i].frequency;
110 }
111 return data->freq_table[0].frequency;
112}
113
114static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data)
115{
116 switch (data->cpu_feature) {
117 case SYSTEM_INTEL_MSR_CAPABLE:
118 return extract_msr(val, data);
119 case SYSTEM_IO_CAPABLE:
120 return extract_io(val, data);
121 default:
122 return 0;
123 }
124}
125
126struct msr_addr {
127 u32 reg;
128};
129
130struct io_addr {
131 u16 port;
132 u8 bit_width;
133};
134
135struct drv_cmd {
136 unsigned int type;
137 const struct cpumask *mask;
138 union {
139 struct msr_addr msr;
140 struct io_addr io;
141 } addr;
142 u32 val;
143};
144
145/* Called via smp_call_function_single(), on the target CPU */
146static void do_drv_read(void *_cmd)
147{
148 struct drv_cmd *cmd = _cmd;
149 u32 h;
150
151 switch (cmd->type) {
152 case SYSTEM_INTEL_MSR_CAPABLE:
153 rdmsr(cmd->addr.msr.reg, cmd->val, h);
154 break;
155 case SYSTEM_IO_CAPABLE:
156 acpi_os_read_port((acpi_io_address)cmd->addr.io.port,
157 &cmd->val,
158 (u32)cmd->addr.io.bit_width);
159 break;
160 default:
161 break;
162 }
163}
164
165/* Called via smp_call_function_many(), on the target CPUs */
166static void do_drv_write(void *_cmd)
167{
168 struct drv_cmd *cmd = _cmd;
169 u32 lo, hi;
170
171 switch (cmd->type) {
172 case SYSTEM_INTEL_MSR_CAPABLE:
173 rdmsr(cmd->addr.msr.reg, lo, hi);
174 lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE);
175 wrmsr(cmd->addr.msr.reg, lo, hi);
176 break;
177 case SYSTEM_IO_CAPABLE:
178 acpi_os_write_port((acpi_io_address)cmd->addr.io.port,
179 cmd->val,
180 (u32)cmd->addr.io.bit_width);
181 break;
182 default:
183 break;
184 }
185}
186
187static void drv_read(struct drv_cmd *cmd)
188{
189 int err;
190 cmd->val = 0;
191
192 err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1);
193 WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */
194}
195
196static void drv_write(struct drv_cmd *cmd)
197{
198 int this_cpu;
199
200 this_cpu = get_cpu();
201 if (cpumask_test_cpu(this_cpu, cmd->mask))
202 do_drv_write(cmd);
203 smp_call_function_many(cmd->mask, do_drv_write, cmd, 1);
204 put_cpu();
205}
206
207static u32 get_cur_val(const struct cpumask *mask)
208{
209 struct acpi_processor_performance *perf;
210 struct drv_cmd cmd;
211
212 if (unlikely(cpumask_empty(mask)))
213 return 0;
214
215 switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) {
216 case SYSTEM_INTEL_MSR_CAPABLE:
217 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
218 cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
219 break;
220 case SYSTEM_IO_CAPABLE:
221 cmd.type = SYSTEM_IO_CAPABLE;
222 perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data;
223 cmd.addr.io.port = perf->control_register.address;
224 cmd.addr.io.bit_width = perf->control_register.bit_width;
225 break;
226 default:
227 return 0;
228 }
229
230 cmd.mask = mask;
231 drv_read(&cmd);
232
233 pr_debug("get_cur_val = %u\n", cmd.val);
234
235 return cmd.val;
236}
237
238static unsigned int get_cur_freq_on_cpu(unsigned int cpu)
239{
240 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, cpu);
241 unsigned int freq;
242 unsigned int cached_freq;
243
244 pr_debug("get_cur_freq_on_cpu (%d)\n", cpu);
245
246 if (unlikely(data == NULL ||
247 data->acpi_data == NULL || data->freq_table == NULL)) {
248 return 0;
249 }
250
251 cached_freq = data->freq_table[data->acpi_data->state].frequency;
252 freq = extract_freq(get_cur_val(cpumask_of(cpu)), data);
253 if (freq != cached_freq) {
254 /*
255 * The dreaded BIOS frequency change behind our back.
256 * Force set the frequency on next target call.
257 */
258 data->resume = 1;
259 }
260
261 pr_debug("cur freq = %u\n", freq);
262
263 return freq;
264}
265
266static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq,
267 struct acpi_cpufreq_data *data)
268{
269 unsigned int cur_freq;
270 unsigned int i;
271
272 for (i = 0; i < 100; i++) {
273 cur_freq = extract_freq(get_cur_val(mask), data);
274 if (cur_freq == freq)
275 return 1;
276 udelay(10);
277 }
278 return 0;
279}
280
281static int acpi_cpufreq_target(struct cpufreq_policy *policy,
282 unsigned int target_freq, unsigned int relation)
283{
284 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
285 struct acpi_processor_performance *perf;
286 struct cpufreq_freqs freqs;
287 struct drv_cmd cmd;
288 unsigned int next_state = 0; /* Index into freq_table */
289 unsigned int next_perf_state = 0; /* Index into perf table */
290 unsigned int i;
291 int result = 0;
292
293 pr_debug("acpi_cpufreq_target %d (%d)\n", target_freq, policy->cpu);
294
295 if (unlikely(data == NULL ||
296 data->acpi_data == NULL || data->freq_table == NULL)) {
297 return -ENODEV;
298 }
299
300 perf = data->acpi_data;
301 result = cpufreq_frequency_table_target(policy,
302 data->freq_table,
303 target_freq,
304 relation, &next_state);
305 if (unlikely(result)) {
306 result = -ENODEV;
307 goto out;
308 }
309
310 next_perf_state = data->freq_table[next_state].index;
311 if (perf->state == next_perf_state) {
312 if (unlikely(data->resume)) {
313 pr_debug("Called after resume, resetting to P%d\n",
314 next_perf_state);
315 data->resume = 0;
316 } else {
317 pr_debug("Already at target state (P%d)\n",
318 next_perf_state);
319 goto out;
320 }
321 }
322
323 switch (data->cpu_feature) {
324 case SYSTEM_INTEL_MSR_CAPABLE:
325 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
326 cmd.addr.msr.reg = MSR_IA32_PERF_CTL;
327 cmd.val = (u32) perf->states[next_perf_state].control;
328 break;
329 case SYSTEM_IO_CAPABLE:
330 cmd.type = SYSTEM_IO_CAPABLE;
331 cmd.addr.io.port = perf->control_register.address;
332 cmd.addr.io.bit_width = perf->control_register.bit_width;
333 cmd.val = (u32) perf->states[next_perf_state].control;
334 break;
335 default:
336 result = -ENODEV;
337 goto out;
338 }
339
340 /* cpufreq holds the hotplug lock, so we are safe from here on */
341 if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY)
342 cmd.mask = policy->cpus;
343 else
344 cmd.mask = cpumask_of(policy->cpu);
345
346 freqs.old = perf->states[perf->state].core_frequency * 1000;
347 freqs.new = data->freq_table[next_state].frequency;
348 for_each_cpu(i, policy->cpus) {
349 freqs.cpu = i;
350 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
351 }
352
353 drv_write(&cmd);
354
355 if (acpi_pstate_strict) {
356 if (!check_freqs(cmd.mask, freqs.new, data)) {
357 pr_debug("acpi_cpufreq_target failed (%d)\n",
358 policy->cpu);
359 result = -EAGAIN;
360 goto out;
361 }
362 }
363
364 for_each_cpu(i, policy->cpus) {
365 freqs.cpu = i;
366 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
367 }
368 perf->state = next_perf_state;
369
370out:
371 return result;
372}
373
374static int acpi_cpufreq_verify(struct cpufreq_policy *policy)
375{
376 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
377
378 pr_debug("acpi_cpufreq_verify\n");
379
380 return cpufreq_frequency_table_verify(policy, data->freq_table);
381}
382
383static unsigned long
384acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu)
385{
386 struct acpi_processor_performance *perf = data->acpi_data;
387
388 if (cpu_khz) {
389 /* search the closest match to cpu_khz */
390 unsigned int i;
391 unsigned long freq;
392 unsigned long freqn = perf->states[0].core_frequency * 1000;
393
394 for (i = 0; i < (perf->state_count-1); i++) {
395 freq = freqn;
396 freqn = perf->states[i+1].core_frequency * 1000;
397 if ((2 * cpu_khz) > (freqn + freq)) {
398 perf->state = i;
399 return freq;
400 }
401 }
402 perf->state = perf->state_count-1;
403 return freqn;
404 } else {
405 /* assume CPU is at P0... */
406 perf->state = 0;
407 return perf->states[0].core_frequency * 1000;
408 }
409}
410
411static void free_acpi_perf_data(void)
412{
413 unsigned int i;
414
415 /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */
416 for_each_possible_cpu(i)
417 free_cpumask_var(per_cpu_ptr(acpi_perf_data, i)
418 ->shared_cpu_map);
419 free_percpu(acpi_perf_data);
420}
421
422/*
423 * acpi_cpufreq_early_init - initialize ACPI P-States library
424 *
425 * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c)
426 * in order to determine correct frequency and voltage pairings. We can
427 * do _PDC and _PSD and find out the processor dependency for the
428 * actual init that will happen later...
429 */
430static int __init acpi_cpufreq_early_init(void)
431{
432 unsigned int i;
433 pr_debug("acpi_cpufreq_early_init\n");
434
435 acpi_perf_data = alloc_percpu(struct acpi_processor_performance);
436 if (!acpi_perf_data) {
437 pr_debug("Memory allocation error for acpi_perf_data.\n");
438 return -ENOMEM;
439 }
440 for_each_possible_cpu(i) {
441 if (!zalloc_cpumask_var_node(
442 &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map,
443 GFP_KERNEL, cpu_to_node(i))) {
444
445 /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */
446 free_acpi_perf_data();
447 return -ENOMEM;
448 }
449 }
450
451 /* Do initialization in ACPI core */
452 acpi_processor_preregister_performance(acpi_perf_data);
453 return 0;
454}
455
456#ifdef CONFIG_SMP
457/*
458 * Some BIOSes do SW_ANY coordination internally, either set it up in hw
459 * or do it in BIOS firmware and won't inform about it to OS. If not
460 * detected, this has a side effect of making CPU run at a different speed
461 * than OS intended it to run at. Detect it and handle it cleanly.
462 */
463static int bios_with_sw_any_bug;
464
465static int sw_any_bug_found(const struct dmi_system_id *d)
466{
467 bios_with_sw_any_bug = 1;
468 return 0;
469}
470
471static const struct dmi_system_id sw_any_bug_dmi_table[] = {
472 {
473 .callback = sw_any_bug_found,
474 .ident = "Supermicro Server X6DLP",
475 .matches = {
476 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
477 DMI_MATCH(DMI_BIOS_VERSION, "080010"),
478 DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"),
479 },
480 },
481 { }
482};
483
484static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c)
485{
486 /* Intel Xeon Processor 7100 Series Specification Update
487 * http://www.intel.com/Assets/PDF/specupdate/314554.pdf
488 * AL30: A Machine Check Exception (MCE) Occurring during an
489 * Enhanced Intel SpeedStep Technology Ratio Change May Cause
490 * Both Processor Cores to Lock Up. */
491 if (c->x86_vendor == X86_VENDOR_INTEL) {
492 if ((c->x86 == 15) &&
493 (c->x86_model == 6) &&
494 (c->x86_mask == 8)) {
495 printk(KERN_INFO "acpi-cpufreq: Intel(R) "
496 "Xeon(R) 7100 Errata AL30, processors may "
497 "lock up on frequency changes: disabling "
498 "acpi-cpufreq.\n");
499 return -ENODEV;
500 }
501 }
502 return 0;
503}
504#endif
505
506static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
507{
508 unsigned int i;
509 unsigned int valid_states = 0;
510 unsigned int cpu = policy->cpu;
511 struct acpi_cpufreq_data *data;
512 unsigned int result = 0;
513 struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
514 struct acpi_processor_performance *perf;
515#ifdef CONFIG_SMP
516 static int blacklisted;
517#endif
518
519 pr_debug("acpi_cpufreq_cpu_init\n");
520
521#ifdef CONFIG_SMP
522 if (blacklisted)
523 return blacklisted;
524 blacklisted = acpi_cpufreq_blacklist(c);
525 if (blacklisted)
526 return blacklisted;
527#endif
528
529 data = kzalloc(sizeof(struct acpi_cpufreq_data), GFP_KERNEL);
530 if (!data)
531 return -ENOMEM;
532
533 data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu);
534 per_cpu(acfreq_data, cpu) = data;
535
536 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC))
537 acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS;
538
539 result = acpi_processor_register_performance(data->acpi_data, cpu);
540 if (result)
541 goto err_free;
542
543 perf = data->acpi_data;
544 policy->shared_type = perf->shared_type;
545
546 /*
547 * Will let policy->cpus know about dependency only when software
548 * coordination is required.
549 */
550 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL ||
551 policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
552 cpumask_copy(policy->cpus, perf->shared_cpu_map);
553 }
554 cpumask_copy(policy->related_cpus, perf->shared_cpu_map);
555
556#ifdef CONFIG_SMP
557 dmi_check_system(sw_any_bug_dmi_table);
558 if (bios_with_sw_any_bug && cpumask_weight(policy->cpus) == 1) {
559 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
560 cpumask_copy(policy->cpus, cpu_core_mask(cpu));
561 }
562#endif
563
564 /* capability check */
565 if (perf->state_count <= 1) {
566 pr_debug("No P-States\n");
567 result = -ENODEV;
568 goto err_unreg;
569 }
570
571 if (perf->control_register.space_id != perf->status_register.space_id) {
572 result = -ENODEV;
573 goto err_unreg;
574 }
575
576 switch (perf->control_register.space_id) {
577 case ACPI_ADR_SPACE_SYSTEM_IO:
578 pr_debug("SYSTEM IO addr space\n");
579 data->cpu_feature = SYSTEM_IO_CAPABLE;
580 break;
581 case ACPI_ADR_SPACE_FIXED_HARDWARE:
582 pr_debug("HARDWARE addr space\n");
583 if (!check_est_cpu(cpu)) {
584 result = -ENODEV;
585 goto err_unreg;
586 }
587 data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE;
588 break;
589 default:
590 pr_debug("Unknown addr space %d\n",
591 (u32) (perf->control_register.space_id));
592 result = -ENODEV;
593 goto err_unreg;
594 }
595
596 data->freq_table = kmalloc(sizeof(struct cpufreq_frequency_table) *
597 (perf->state_count+1), GFP_KERNEL);
598 if (!data->freq_table) {
599 result = -ENOMEM;
600 goto err_unreg;
601 }
602
603 /* detect transition latency */
604 policy->cpuinfo.transition_latency = 0;
605 for (i = 0; i < perf->state_count; i++) {
606 if ((perf->states[i].transition_latency * 1000) >
607 policy->cpuinfo.transition_latency)
608 policy->cpuinfo.transition_latency =
609 perf->states[i].transition_latency * 1000;
610 }
611
612 /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */
613 if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE &&
614 policy->cpuinfo.transition_latency > 20 * 1000) {
615 policy->cpuinfo.transition_latency = 20 * 1000;
616 printk_once(KERN_INFO
617 "P-state transition latency capped at 20 uS\n");
618 }
619
620 /* table init */
621 for (i = 0; i < perf->state_count; i++) {
622 if (i > 0 && perf->states[i].core_frequency >=
623 data->freq_table[valid_states-1].frequency / 1000)
624 continue;
625
626 data->freq_table[valid_states].index = i;
627 data->freq_table[valid_states].frequency =
628 perf->states[i].core_frequency * 1000;
629 valid_states++;
630 }
631 data->freq_table[valid_states].frequency = CPUFREQ_TABLE_END;
632 perf->state = 0;
633
634 result = cpufreq_frequency_table_cpuinfo(policy, data->freq_table);
635 if (result)
636 goto err_freqfree;
637
638 if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq)
639 printk(KERN_WARNING FW_WARN "P-state 0 is not max freq\n");
640
641 switch (perf->control_register.space_id) {
642 case ACPI_ADR_SPACE_SYSTEM_IO:
643 /* Current speed is unknown and not detectable by IO port */
644 policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu);
645 break;
646 case ACPI_ADR_SPACE_FIXED_HARDWARE:
647 acpi_cpufreq_driver.get = get_cur_freq_on_cpu;
648 policy->cur = get_cur_freq_on_cpu(cpu);
649 break;
650 default:
651 break;
652 }
653
654 /* notify BIOS that we exist */
655 acpi_processor_notify_smm(THIS_MODULE);
656
657 /* Check for APERF/MPERF support in hardware */
658 if (cpu_has(c, X86_FEATURE_APERFMPERF))
659 acpi_cpufreq_driver.getavg = cpufreq_get_measured_perf;
660
661 pr_debug("CPU%u - ACPI performance management activated.\n", cpu);
662 for (i = 0; i < perf->state_count; i++)
663 pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n",
664 (i == perf->state ? '*' : ' '), i,
665 (u32) perf->states[i].core_frequency,
666 (u32) perf->states[i].power,
667 (u32) perf->states[i].transition_latency);
668
669 cpufreq_frequency_table_get_attr(data->freq_table, policy->cpu);
670
671 /*
672 * the first call to ->target() should result in us actually
673 * writing something to the appropriate registers.
674 */
675 data->resume = 1;
676
677 return result;
678
679err_freqfree:
680 kfree(data->freq_table);
681err_unreg:
682 acpi_processor_unregister_performance(perf, cpu);
683err_free:
684 kfree(data);
685 per_cpu(acfreq_data, cpu) = NULL;
686
687 return result;
688}
689
690static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
691{
692 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
693
694 pr_debug("acpi_cpufreq_cpu_exit\n");
695
696 if (data) {
697 cpufreq_frequency_table_put_attr(policy->cpu);
698 per_cpu(acfreq_data, policy->cpu) = NULL;
699 acpi_processor_unregister_performance(data->acpi_data,
700 policy->cpu);
701 kfree(data->freq_table);
702 kfree(data);
703 }
704
705 return 0;
706}
707
708static int acpi_cpufreq_resume(struct cpufreq_policy *policy)
709{
710 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu);
711
712 pr_debug("acpi_cpufreq_resume\n");
713
714 data->resume = 1;
715
716 return 0;
717}
718
719static struct freq_attr *acpi_cpufreq_attr[] = {
720 &cpufreq_freq_attr_scaling_available_freqs,
721 NULL,
722};
723
724static struct cpufreq_driver acpi_cpufreq_driver = {
725 .verify = acpi_cpufreq_verify,
726 .target = acpi_cpufreq_target,
727 .bios_limit = acpi_processor_get_bios_limit,
728 .init = acpi_cpufreq_cpu_init,
729 .exit = acpi_cpufreq_cpu_exit,
730 .resume = acpi_cpufreq_resume,
731 .name = "acpi-cpufreq",
732 .owner = THIS_MODULE,
733 .attr = acpi_cpufreq_attr,
734};
735
736static int __init acpi_cpufreq_init(void)
737{
738 int ret;
739
740 if (acpi_disabled)
741 return 0;
742
743 pr_debug("acpi_cpufreq_init\n");
744
745 ret = acpi_cpufreq_early_init();
746 if (ret)
747 return ret;
748
749 ret = cpufreq_register_driver(&acpi_cpufreq_driver);
750 if (ret)
751 free_acpi_perf_data();
752
753 return ret;
754}
755
756static void __exit acpi_cpufreq_exit(void)
757{
758 pr_debug("acpi_cpufreq_exit\n");
759
760 cpufreq_unregister_driver(&acpi_cpufreq_driver);
761
762 free_percpu(acpi_perf_data);
763}
764
765module_param(acpi_pstate_strict, uint, 0644);
766MODULE_PARM_DESC(acpi_pstate_strict,
767 "value 0 or non-zero. non-zero -> strict ACPI checks are "
768 "performed during frequency changes.");
769
770late_initcall(acpi_cpufreq_init);
771module_exit(acpi_cpufreq_exit);
772
773MODULE_ALIAS("acpi");
diff --git a/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
deleted file mode 100644
index 7bac808804f3..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ /dev/null
@@ -1,444 +0,0 @@
1/*
2 * (C) 2004-2006 Sebastian Witt <se.witt@gmx.net>
3 *
4 * Licensed under the terms of the GNU GPL License version 2.
5 * Based upon reverse engineered information
6 *
7 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/cpufreq.h>
15#include <linux/pci.h>
16#include <linux/delay.h>
17
18#define NFORCE2_XTAL 25
19#define NFORCE2_BOOTFSB 0x48
20#define NFORCE2_PLLENABLE 0xa8
21#define NFORCE2_PLLREG 0xa4
22#define NFORCE2_PLLADR 0xa0
23#define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
24
25#define NFORCE2_MIN_FSB 50
26#define NFORCE2_SAFE_DISTANCE 50
27
28/* Delay in ms between FSB changes */
29/* #define NFORCE2_DELAY 10 */
30
31/*
32 * nforce2_chipset:
33 * FSB is changed using the chipset
34 */
35static struct pci_dev *nforce2_dev;
36
37/* fid:
38 * multiplier * 10
39 */
40static int fid;
41
42/* min_fsb, max_fsb:
43 * minimum and maximum FSB (= FSB at boot time)
44 */
45static int min_fsb;
46static int max_fsb;
47
48MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
49MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
50MODULE_LICENSE("GPL");
51
52module_param(fid, int, 0444);
53module_param(min_fsb, int, 0444);
54
55MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
56MODULE_PARM_DESC(min_fsb,
57 "Minimum FSB to use, if not defined: current FSB - 50");
58
59#define PFX "cpufreq-nforce2: "
60
61/**
62 * nforce2_calc_fsb - calculate FSB
63 * @pll: PLL value
64 *
65 * Calculates FSB from PLL value
66 */
67static int nforce2_calc_fsb(int pll)
68{
69 unsigned char mul, div;
70
71 mul = (pll >> 8) & 0xff;
72 div = pll & 0xff;
73
74 if (div > 0)
75 return NFORCE2_XTAL * mul / div;
76
77 return 0;
78}
79
80/**
81 * nforce2_calc_pll - calculate PLL value
82 * @fsb: FSB
83 *
84 * Calculate PLL value for given FSB
85 */
86static int nforce2_calc_pll(unsigned int fsb)
87{
88 unsigned char xmul, xdiv;
89 unsigned char mul = 0, div = 0;
90 int tried = 0;
91
92 /* Try to calculate multiplier and divider up to 4 times */
93 while (((mul == 0) || (div == 0)) && (tried <= 3)) {
94 for (xdiv = 2; xdiv <= 0x80; xdiv++)
95 for (xmul = 1; xmul <= 0xfe; xmul++)
96 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
97 fsb + tried) {
98 mul = xmul;
99 div = xdiv;
100 }
101 tried++;
102 }
103
104 if ((mul == 0) || (div == 0))
105 return -1;
106
107 return NFORCE2_PLL(mul, div);
108}
109
110/**
111 * nforce2_write_pll - write PLL value to chipset
112 * @pll: PLL value
113 *
114 * Writes new FSB PLL value to chipset
115 */
116static void nforce2_write_pll(int pll)
117{
118 int temp;
119
120 /* Set the pll addr. to 0x00 */
121 pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);
122
123 /* Now write the value in all 64 registers */
124 for (temp = 0; temp <= 0x3f; temp++)
125 pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
126
127 return;
128}
129
130/**
131 * nforce2_fsb_read - Read FSB
132 *
133 * Read FSB from chipset
134 * If bootfsb != 0, return FSB at boot-time
135 */
136static unsigned int nforce2_fsb_read(int bootfsb)
137{
138 struct pci_dev *nforce2_sub5;
139 u32 fsb, temp = 0;
140
141 /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
142 nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
143 PCI_ANY_ID, PCI_ANY_ID, NULL);
144 if (!nforce2_sub5)
145 return 0;
146
147 pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
148 fsb /= 1000000;
149
150 /* Check if PLL register is already set */
151 pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
152
153 if (bootfsb || !temp)
154 return fsb;
155
156 /* Use PLL register FSB value */
157 pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
158 fsb = nforce2_calc_fsb(temp);
159
160 return fsb;
161}
162
163/**
164 * nforce2_set_fsb - set new FSB
165 * @fsb: New FSB
166 *
167 * Sets new FSB
168 */
169static int nforce2_set_fsb(unsigned int fsb)
170{
171 u32 temp = 0;
172 unsigned int tfsb;
173 int diff;
174 int pll = 0;
175
176 if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
177 printk(KERN_ERR PFX "FSB %d is out of range!\n", fsb);
178 return -EINVAL;
179 }
180
181 tfsb = nforce2_fsb_read(0);
182 if (!tfsb) {
183 printk(KERN_ERR PFX "Error while reading the FSB\n");
184 return -EINVAL;
185 }
186
187 /* First write? Then set actual value */
188 pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
189 if (!temp) {
190 pll = nforce2_calc_pll(tfsb);
191
192 if (pll < 0)
193 return -EINVAL;
194
195 nforce2_write_pll(pll);
196 }
197
198 /* Enable write access */
199 temp = 0x01;
200 pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);
201
202 diff = tfsb - fsb;
203
204 if (!diff)
205 return 0;
206
207 while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
208 if (diff < 0)
209 tfsb++;
210 else
211 tfsb--;
212
213 /* Calculate the PLL reg. value */
214 pll = nforce2_calc_pll(tfsb);
215 if (pll == -1)
216 return -EINVAL;
217
218 nforce2_write_pll(pll);
219#ifdef NFORCE2_DELAY
220 mdelay(NFORCE2_DELAY);
221#endif
222 }
223
224 temp = 0x40;
225 pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);
226
227 return 0;
228}
229
230/**
231 * nforce2_get - get the CPU frequency
232 * @cpu: CPU number
233 *
234 * Returns the CPU frequency
235 */
236static unsigned int nforce2_get(unsigned int cpu)
237{
238 if (cpu)
239 return 0;
240 return nforce2_fsb_read(0) * fid * 100;
241}
242
243/**
244 * nforce2_target - set a new CPUFreq policy
245 * @policy: new policy
246 * @target_freq: the target frequency
247 * @relation: how that frequency relates to achieved frequency
248 * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
249 *
250 * Sets a new CPUFreq policy.
251 */
252static int nforce2_target(struct cpufreq_policy *policy,
253 unsigned int target_freq, unsigned int relation)
254{
255/* unsigned long flags; */
256 struct cpufreq_freqs freqs;
257 unsigned int target_fsb;
258
259 if ((target_freq > policy->max) || (target_freq < policy->min))
260 return -EINVAL;
261
262 target_fsb = target_freq / (fid * 100);
263
264 freqs.old = nforce2_get(policy->cpu);
265 freqs.new = target_fsb * fid * 100;
266 freqs.cpu = 0; /* Only one CPU on nForce2 platforms */
267
268 if (freqs.old == freqs.new)
269 return 0;
270
271 pr_debug("Old CPU frequency %d kHz, new %d kHz\n",
272 freqs.old, freqs.new);
273
274 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
275
276 /* Disable IRQs */
277 /* local_irq_save(flags); */
278
279 if (nforce2_set_fsb(target_fsb) < 0)
280 printk(KERN_ERR PFX "Changing FSB to %d failed\n",
281 target_fsb);
282 else
283 pr_debug("Changed FSB successfully to %d\n",
284 target_fsb);
285
286 /* Enable IRQs */
287 /* local_irq_restore(flags); */
288
289 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
290
291 return 0;
292}
293
294/**
295 * nforce2_verify - verifies a new CPUFreq policy
296 * @policy: new policy
297 */
298static int nforce2_verify(struct cpufreq_policy *policy)
299{
300 unsigned int fsb_pol_max;
301
302 fsb_pol_max = policy->max / (fid * 100);
303
304 if (policy->min < (fsb_pol_max * fid * 100))
305 policy->max = (fsb_pol_max + 1) * fid * 100;
306
307 cpufreq_verify_within_limits(policy,
308 policy->cpuinfo.min_freq,
309 policy->cpuinfo.max_freq);
310 return 0;
311}
312
313static int nforce2_cpu_init(struct cpufreq_policy *policy)
314{
315 unsigned int fsb;
316 unsigned int rfid;
317
318 /* capability check */
319 if (policy->cpu != 0)
320 return -ENODEV;
321
322 /* Get current FSB */
323 fsb = nforce2_fsb_read(0);
324
325 if (!fsb)
326 return -EIO;
327
328 /* FIX: Get FID from CPU */
329 if (!fid) {
330 if (!cpu_khz) {
331 printk(KERN_WARNING PFX
332 "cpu_khz not set, can't calculate multiplier!\n");
333 return -ENODEV;
334 }
335
336 fid = cpu_khz / (fsb * 100);
337 rfid = fid % 5;
338
339 if (rfid) {
340 if (rfid > 2)
341 fid += 5 - rfid;
342 else
343 fid -= rfid;
344 }
345 }
346
347 printk(KERN_INFO PFX "FSB currently at %i MHz, FID %d.%d\n", fsb,
348 fid / 10, fid % 10);
349
350 /* Set maximum FSB to FSB at boot time */
351 max_fsb = nforce2_fsb_read(1);
352
353 if (!max_fsb)
354 return -EIO;
355
356 if (!min_fsb)
357 min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
358
359 if (min_fsb < NFORCE2_MIN_FSB)
360 min_fsb = NFORCE2_MIN_FSB;
361
362 /* cpuinfo and default policy values */
363 policy->cpuinfo.min_freq = min_fsb * fid * 100;
364 policy->cpuinfo.max_freq = max_fsb * fid * 100;
365 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
366 policy->cur = nforce2_get(policy->cpu);
367 policy->min = policy->cpuinfo.min_freq;
368 policy->max = policy->cpuinfo.max_freq;
369
370 return 0;
371}
372
373static int nforce2_cpu_exit(struct cpufreq_policy *policy)
374{
375 return 0;
376}
377
378static struct cpufreq_driver nforce2_driver = {
379 .name = "nforce2",
380 .verify = nforce2_verify,
381 .target = nforce2_target,
382 .get = nforce2_get,
383 .init = nforce2_cpu_init,
384 .exit = nforce2_cpu_exit,
385 .owner = THIS_MODULE,
386};
387
388/**
389 * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
390 *
391 * Detects nForce2 A2 and C1 stepping
392 *
393 */
394static int nforce2_detect_chipset(void)
395{
396 nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
397 PCI_DEVICE_ID_NVIDIA_NFORCE2,
398 PCI_ANY_ID, PCI_ANY_ID, NULL);
399
400 if (nforce2_dev == NULL)
401 return -ENODEV;
402
403 printk(KERN_INFO PFX "Detected nForce2 chipset revision %X\n",
404 nforce2_dev->revision);
405 printk(KERN_INFO PFX
406 "FSB changing is maybe unstable and can lead to "
407 "crashes and data loss.\n");
408
409 return 0;
410}
411
412/**
413 * nforce2_init - initializes the nForce2 CPUFreq driver
414 *
415 * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
416 * devices, -EINVAL on problems during initiatization, and zero on
417 * success.
418 */
419static int __init nforce2_init(void)
420{
421 /* TODO: do we need to detect the processor? */
422
423 /* detect chipset */
424 if (nforce2_detect_chipset()) {
425 printk(KERN_INFO PFX "No nForce2 chipset.\n");
426 return -ENODEV;
427 }
428
429 return cpufreq_register_driver(&nforce2_driver);
430}
431
432/**
433 * nforce2_exit - unregisters cpufreq module
434 *
435 * Unregisters nForce2 FSB change support.
436 */
437static void __exit nforce2_exit(void)
438{
439 cpufreq_unregister_driver(&nforce2_driver);
440}
441
442module_init(nforce2_init);
443module_exit(nforce2_exit);
444
diff --git a/arch/x86/kernel/cpu/cpufreq/e_powersaver.c b/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
deleted file mode 100644
index 35a257dd4bb7..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
+++ /dev/null
@@ -1,367 +0,0 @@
1/*
2 * Based on documentation provided by Dave Jones. Thanks!
3 *
4 * Licensed under the terms of the GNU GPL License version 2.
5 *
6 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/cpufreq.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/timex.h>
16#include <linux/io.h>
17#include <linux/delay.h>
18
19#include <asm/msr.h>
20#include <asm/tsc.h>
21
22#define EPS_BRAND_C7M 0
23#define EPS_BRAND_C7 1
24#define EPS_BRAND_EDEN 2
25#define EPS_BRAND_C3 3
26#define EPS_BRAND_C7D 4
27
28struct eps_cpu_data {
29 u32 fsb;
30 struct cpufreq_frequency_table freq_table[];
31};
32
33static struct eps_cpu_data *eps_cpu[NR_CPUS];
34
35
36static unsigned int eps_get(unsigned int cpu)
37{
38 struct eps_cpu_data *centaur;
39 u32 lo, hi;
40
41 if (cpu)
42 return 0;
43 centaur = eps_cpu[cpu];
44 if (centaur == NULL)
45 return 0;
46
47 /* Return current frequency */
48 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
49 return centaur->fsb * ((lo >> 8) & 0xff);
50}
51
52static int eps_set_state(struct eps_cpu_data *centaur,
53 unsigned int cpu,
54 u32 dest_state)
55{
56 struct cpufreq_freqs freqs;
57 u32 lo, hi;
58 int err = 0;
59 int i;
60
61 freqs.old = eps_get(cpu);
62 freqs.new = centaur->fsb * ((dest_state >> 8) & 0xff);
63 freqs.cpu = cpu;
64 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
65
66 /* Wait while CPU is busy */
67 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
68 i = 0;
69 while (lo & ((1 << 16) | (1 << 17))) {
70 udelay(16);
71 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
72 i++;
73 if (unlikely(i > 64)) {
74 err = -ENODEV;
75 goto postchange;
76 }
77 }
78 /* Set new multiplier and voltage */
79 wrmsr(MSR_IA32_PERF_CTL, dest_state & 0xffff, 0);
80 /* Wait until transition end */
81 i = 0;
82 do {
83 udelay(16);
84 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
85 i++;
86 if (unlikely(i > 64)) {
87 err = -ENODEV;
88 goto postchange;
89 }
90 } while (lo & ((1 << 16) | (1 << 17)));
91
92 /* Return current frequency */
93postchange:
94 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
95 freqs.new = centaur->fsb * ((lo >> 8) & 0xff);
96
97#ifdef DEBUG
98 {
99 u8 current_multiplier, current_voltage;
100
101 /* Print voltage and multiplier */
102 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
103 current_voltage = lo & 0xff;
104 printk(KERN_INFO "eps: Current voltage = %dmV\n",
105 current_voltage * 16 + 700);
106 current_multiplier = (lo >> 8) & 0xff;
107 printk(KERN_INFO "eps: Current multiplier = %d\n",
108 current_multiplier);
109 }
110#endif
111 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
112 return err;
113}
114
115static int eps_target(struct cpufreq_policy *policy,
116 unsigned int target_freq,
117 unsigned int relation)
118{
119 struct eps_cpu_data *centaur;
120 unsigned int newstate = 0;
121 unsigned int cpu = policy->cpu;
122 unsigned int dest_state;
123 int ret;
124
125 if (unlikely(eps_cpu[cpu] == NULL))
126 return -ENODEV;
127 centaur = eps_cpu[cpu];
128
129 if (unlikely(cpufreq_frequency_table_target(policy,
130 &eps_cpu[cpu]->freq_table[0],
131 target_freq,
132 relation,
133 &newstate))) {
134 return -EINVAL;
135 }
136
137 /* Make frequency transition */
138 dest_state = centaur->freq_table[newstate].index & 0xffff;
139 ret = eps_set_state(centaur, cpu, dest_state);
140 if (ret)
141 printk(KERN_ERR "eps: Timeout!\n");
142 return ret;
143}
144
145static int eps_verify(struct cpufreq_policy *policy)
146{
147 return cpufreq_frequency_table_verify(policy,
148 &eps_cpu[policy->cpu]->freq_table[0]);
149}
150
151static int eps_cpu_init(struct cpufreq_policy *policy)
152{
153 unsigned int i;
154 u32 lo, hi;
155 u64 val;
156 u8 current_multiplier, current_voltage;
157 u8 max_multiplier, max_voltage;
158 u8 min_multiplier, min_voltage;
159 u8 brand = 0;
160 u32 fsb;
161 struct eps_cpu_data *centaur;
162 struct cpuinfo_x86 *c = &cpu_data(0);
163 struct cpufreq_frequency_table *f_table;
164 int k, step, voltage;
165 int ret;
166 int states;
167
168 if (policy->cpu != 0)
169 return -ENODEV;
170
171 /* Check brand */
172 printk(KERN_INFO "eps: Detected VIA ");
173
174 switch (c->x86_model) {
175 case 10:
176 rdmsr(0x1153, lo, hi);
177 brand = (((lo >> 2) ^ lo) >> 18) & 3;
178 printk(KERN_CONT "Model A ");
179 break;
180 case 13:
181 rdmsr(0x1154, lo, hi);
182 brand = (((lo >> 4) ^ (lo >> 2))) & 0x000000ff;
183 printk(KERN_CONT "Model D ");
184 break;
185 }
186
187 switch (brand) {
188 case EPS_BRAND_C7M:
189 printk(KERN_CONT "C7-M\n");
190 break;
191 case EPS_BRAND_C7:
192 printk(KERN_CONT "C7\n");
193 break;
194 case EPS_BRAND_EDEN:
195 printk(KERN_CONT "Eden\n");
196 break;
197 case EPS_BRAND_C7D:
198 printk(KERN_CONT "C7-D\n");
199 break;
200 case EPS_BRAND_C3:
201 printk(KERN_CONT "C3\n");
202 return -ENODEV;
203 break;
204 }
205 /* Enable Enhanced PowerSaver */
206 rdmsrl(MSR_IA32_MISC_ENABLE, val);
207 if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
208 val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
209 wrmsrl(MSR_IA32_MISC_ENABLE, val);
210 /* Can be locked at 0 */
211 rdmsrl(MSR_IA32_MISC_ENABLE, val);
212 if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
213 printk(KERN_INFO "eps: Can't enable Enhanced PowerSaver\n");
214 return -ENODEV;
215 }
216 }
217
218 /* Print voltage and multiplier */
219 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
220 current_voltage = lo & 0xff;
221 printk(KERN_INFO "eps: Current voltage = %dmV\n",
222 current_voltage * 16 + 700);
223 current_multiplier = (lo >> 8) & 0xff;
224 printk(KERN_INFO "eps: Current multiplier = %d\n", current_multiplier);
225
226 /* Print limits */
227 max_voltage = hi & 0xff;
228 printk(KERN_INFO "eps: Highest voltage = %dmV\n",
229 max_voltage * 16 + 700);
230 max_multiplier = (hi >> 8) & 0xff;
231 printk(KERN_INFO "eps: Highest multiplier = %d\n", max_multiplier);
232 min_voltage = (hi >> 16) & 0xff;
233 printk(KERN_INFO "eps: Lowest voltage = %dmV\n",
234 min_voltage * 16 + 700);
235 min_multiplier = (hi >> 24) & 0xff;
236 printk(KERN_INFO "eps: Lowest multiplier = %d\n", min_multiplier);
237
238 /* Sanity checks */
239 if (current_multiplier == 0 || max_multiplier == 0
240 || min_multiplier == 0)
241 return -EINVAL;
242 if (current_multiplier > max_multiplier
243 || max_multiplier <= min_multiplier)
244 return -EINVAL;
245 if (current_voltage > 0x1f || max_voltage > 0x1f)
246 return -EINVAL;
247 if (max_voltage < min_voltage)
248 return -EINVAL;
249
250 /* Calc FSB speed */
251 fsb = cpu_khz / current_multiplier;
252 /* Calc number of p-states supported */
253 if (brand == EPS_BRAND_C7M)
254 states = max_multiplier - min_multiplier + 1;
255 else
256 states = 2;
257
258 /* Allocate private data and frequency table for current cpu */
259 centaur = kzalloc(sizeof(struct eps_cpu_data)
260 + (states + 1) * sizeof(struct cpufreq_frequency_table),
261 GFP_KERNEL);
262 if (!centaur)
263 return -ENOMEM;
264 eps_cpu[0] = centaur;
265
266 /* Copy basic values */
267 centaur->fsb = fsb;
268
269 /* Fill frequency and MSR value table */
270 f_table = &centaur->freq_table[0];
271 if (brand != EPS_BRAND_C7M) {
272 f_table[0].frequency = fsb * min_multiplier;
273 f_table[0].index = (min_multiplier << 8) | min_voltage;
274 f_table[1].frequency = fsb * max_multiplier;
275 f_table[1].index = (max_multiplier << 8) | max_voltage;
276 f_table[2].frequency = CPUFREQ_TABLE_END;
277 } else {
278 k = 0;
279 step = ((max_voltage - min_voltage) * 256)
280 / (max_multiplier - min_multiplier);
281 for (i = min_multiplier; i <= max_multiplier; i++) {
282 voltage = (k * step) / 256 + min_voltage;
283 f_table[k].frequency = fsb * i;
284 f_table[k].index = (i << 8) | voltage;
285 k++;
286 }
287 f_table[k].frequency = CPUFREQ_TABLE_END;
288 }
289
290 policy->cpuinfo.transition_latency = 140000; /* 844mV -> 700mV in ns */
291 policy->cur = fsb * current_multiplier;
292
293 ret = cpufreq_frequency_table_cpuinfo(policy, &centaur->freq_table[0]);
294 if (ret) {
295 kfree(centaur);
296 return ret;
297 }
298
299 cpufreq_frequency_table_get_attr(&centaur->freq_table[0], policy->cpu);
300 return 0;
301}
302
303static int eps_cpu_exit(struct cpufreq_policy *policy)
304{
305 unsigned int cpu = policy->cpu;
306 struct eps_cpu_data *centaur;
307 u32 lo, hi;
308
309 if (eps_cpu[cpu] == NULL)
310 return -ENODEV;
311 centaur = eps_cpu[cpu];
312
313 /* Get max frequency */
314 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
315 /* Set max frequency */
316 eps_set_state(centaur, cpu, hi & 0xffff);
317 /* Bye */
318 cpufreq_frequency_table_put_attr(policy->cpu);
319 kfree(eps_cpu[cpu]);
320 eps_cpu[cpu] = NULL;
321 return 0;
322}
323
324static struct freq_attr *eps_attr[] = {
325 &cpufreq_freq_attr_scaling_available_freqs,
326 NULL,
327};
328
329static struct cpufreq_driver eps_driver = {
330 .verify = eps_verify,
331 .target = eps_target,
332 .init = eps_cpu_init,
333 .exit = eps_cpu_exit,
334 .get = eps_get,
335 .name = "e_powersaver",
336 .owner = THIS_MODULE,
337 .attr = eps_attr,
338};
339
340static int __init eps_init(void)
341{
342 struct cpuinfo_x86 *c = &cpu_data(0);
343
344 /* This driver will work only on Centaur C7 processors with
345 * Enhanced SpeedStep/PowerSaver registers */
346 if (c->x86_vendor != X86_VENDOR_CENTAUR
347 || c->x86 != 6 || c->x86_model < 10)
348 return -ENODEV;
349 if (!cpu_has(c, X86_FEATURE_EST))
350 return -ENODEV;
351
352 if (cpufreq_register_driver(&eps_driver))
353 return -EINVAL;
354 return 0;
355}
356
357static void __exit eps_exit(void)
358{
359 cpufreq_unregister_driver(&eps_driver);
360}
361
362MODULE_AUTHOR("Rafal Bilski <rafalbilski@interia.pl>");
363MODULE_DESCRIPTION("Enhanced PowerSaver driver for VIA C7 CPU's.");
364MODULE_LICENSE("GPL");
365
366module_init(eps_init);
367module_exit(eps_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/elanfreq.c b/arch/x86/kernel/cpu/cpufreq/elanfreq.c
deleted file mode 100644
index c587db472a75..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/elanfreq.c
+++ /dev/null
@@ -1,309 +0,0 @@
1/*
2 * elanfreq: cpufreq driver for the AMD ELAN family
3 *
4 * (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de>
5 *
6 * Parts of this code are (c) Sven Geggus <sven@geggus.net>
7 *
8 * All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * 2002-02-13: - initial revision for 2.4.18-pre9 by Robert Schwebel
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22
23#include <linux/delay.h>
24#include <linux/cpufreq.h>
25
26#include <asm/msr.h>
27#include <linux/timex.h>
28#include <linux/io.h>
29
30#define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
31#define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */
32
33/* Module parameter */
34static int max_freq;
35
36struct s_elan_multiplier {
37 int clock; /* frequency in kHz */
38 int val40h; /* PMU Force Mode register */
39 int val80h; /* CPU Clock Speed Register */
40};
41
42/*
43 * It is important that the frequencies
44 * are listed in ascending order here!
45 */
46static struct s_elan_multiplier elan_multiplier[] = {
47 {1000, 0x02, 0x18},
48 {2000, 0x02, 0x10},
49 {4000, 0x02, 0x08},
50 {8000, 0x00, 0x00},
51 {16000, 0x00, 0x02},
52 {33000, 0x00, 0x04},
53 {66000, 0x01, 0x04},
54 {99000, 0x01, 0x05}
55};
56
57static struct cpufreq_frequency_table elanfreq_table[] = {
58 {0, 1000},
59 {1, 2000},
60 {2, 4000},
61 {3, 8000},
62 {4, 16000},
63 {5, 33000},
64 {6, 66000},
65 {7, 99000},
66 {0, CPUFREQ_TABLE_END},
67};
68
69
70/**
71 * elanfreq_get_cpu_frequency: determine current cpu speed
72 *
73 * Finds out at which frequency the CPU of the Elan SOC runs
74 * at the moment. Frequencies from 1 to 33 MHz are generated
75 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
76 * and have the rest of the chip running with 33 MHz.
77 */
78
79static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
80{
81 u8 clockspeed_reg; /* Clock Speed Register */
82
83 local_irq_disable();
84 outb_p(0x80, REG_CSCIR);
85 clockspeed_reg = inb_p(REG_CSCDR);
86 local_irq_enable();
87
88 if ((clockspeed_reg & 0xE0) == 0xE0)
89 return 0;
90
91 /* Are we in CPU clock multiplied mode (66/99 MHz)? */
92 if ((clockspeed_reg & 0xE0) == 0xC0) {
93 if ((clockspeed_reg & 0x01) == 0)
94 return 66000;
95 else
96 return 99000;
97 }
98
99 /* 33 MHz is not 32 MHz... */
100 if ((clockspeed_reg & 0xE0) == 0xA0)
101 return 33000;
102
103 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000;
104}
105
106
107/**
108 * elanfreq_set_cpu_frequency: Change the CPU core frequency
109 * @cpu: cpu number
110 * @freq: frequency in kHz
111 *
112 * This function takes a frequency value and changes the CPU frequency
113 * according to this. Note that the frequency has to be checked by
114 * elanfreq_validatespeed() for correctness!
115 *
116 * There is no return value.
117 */
118
119static void elanfreq_set_cpu_state(unsigned int state)
120{
121 struct cpufreq_freqs freqs;
122
123 freqs.old = elanfreq_get_cpu_frequency(0);
124 freqs.new = elan_multiplier[state].clock;
125 freqs.cpu = 0; /* elanfreq.c is UP only driver */
126
127 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
128
129 printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n",
130 elan_multiplier[state].clock);
131
132
133 /*
134 * Access to the Elan's internal registers is indexed via
135 * 0x22: Chip Setup & Control Register Index Register (CSCI)
136 * 0x23: Chip Setup & Control Register Data Register (CSCD)
137 *
138 */
139
140 /*
141 * 0x40 is the Power Management Unit's Force Mode Register.
142 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency)
143 */
144
145 local_irq_disable();
146 outb_p(0x40, REG_CSCIR); /* Disable hyperspeed mode */
147 outb_p(0x00, REG_CSCDR);
148 local_irq_enable(); /* wait till internal pipelines and */
149 udelay(1000); /* buffers have cleaned up */
150
151 local_irq_disable();
152
153 /* now, set the CPU clock speed register (0x80) */
154 outb_p(0x80, REG_CSCIR);
155 outb_p(elan_multiplier[state].val80h, REG_CSCDR);
156
157 /* now, the hyperspeed bit in PMU Force Mode Register (0x40) */
158 outb_p(0x40, REG_CSCIR);
159 outb_p(elan_multiplier[state].val40h, REG_CSCDR);
160 udelay(10000);
161 local_irq_enable();
162
163 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
164};
165
166
167/**
168 * elanfreq_validatespeed: test if frequency range is valid
169 * @policy: the policy to validate
170 *
171 * This function checks if a given frequency range in kHz is valid
172 * for the hardware supported by the driver.
173 */
174
175static int elanfreq_verify(struct cpufreq_policy *policy)
176{
177 return cpufreq_frequency_table_verify(policy, &elanfreq_table[0]);
178}
179
180static int elanfreq_target(struct cpufreq_policy *policy,
181 unsigned int target_freq,
182 unsigned int relation)
183{
184 unsigned int newstate = 0;
185
186 if (cpufreq_frequency_table_target(policy, &elanfreq_table[0],
187 target_freq, relation, &newstate))
188 return -EINVAL;
189
190 elanfreq_set_cpu_state(newstate);
191
192 return 0;
193}
194
195
196/*
197 * Module init and exit code
198 */
199
200static int elanfreq_cpu_init(struct cpufreq_policy *policy)
201{
202 struct cpuinfo_x86 *c = &cpu_data(0);
203 unsigned int i;
204 int result;
205
206 /* capability check */
207 if ((c->x86_vendor != X86_VENDOR_AMD) ||
208 (c->x86 != 4) || (c->x86_model != 10))
209 return -ENODEV;
210
211 /* max freq */
212 if (!max_freq)
213 max_freq = elanfreq_get_cpu_frequency(0);
214
215 /* table init */
216 for (i = 0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
217 if (elanfreq_table[i].frequency > max_freq)
218 elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
219 }
220
221 /* cpuinfo and default policy values */
222 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
223 policy->cur = elanfreq_get_cpu_frequency(0);
224
225 result = cpufreq_frequency_table_cpuinfo(policy, elanfreq_table);
226 if (result)
227 return result;
228
229 cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu);
230 return 0;
231}
232
233
234static int elanfreq_cpu_exit(struct cpufreq_policy *policy)
235{
236 cpufreq_frequency_table_put_attr(policy->cpu);
237 return 0;
238}
239
240
241#ifndef MODULE
242/**
243 * elanfreq_setup - elanfreq command line parameter parsing
244 *
245 * elanfreq command line parameter. Use:
246 * elanfreq=66000
247 * to set the maximum CPU frequency to 66 MHz. Note that in
248 * case you do not give this boot parameter, the maximum
249 * frequency will fall back to _current_ CPU frequency which
250 * might be lower. If you build this as a module, use the
251 * max_freq module parameter instead.
252 */
253static int __init elanfreq_setup(char *str)
254{
255 max_freq = simple_strtoul(str, &str, 0);
256 printk(KERN_WARNING "You're using the deprecated elanfreq command line option. Use elanfreq.max_freq instead, please!\n");
257 return 1;
258}
259__setup("elanfreq=", elanfreq_setup);
260#endif
261
262
263static struct freq_attr *elanfreq_attr[] = {
264 &cpufreq_freq_attr_scaling_available_freqs,
265 NULL,
266};
267
268
269static struct cpufreq_driver elanfreq_driver = {
270 .get = elanfreq_get_cpu_frequency,
271 .verify = elanfreq_verify,
272 .target = elanfreq_target,
273 .init = elanfreq_cpu_init,
274 .exit = elanfreq_cpu_exit,
275 .name = "elanfreq",
276 .owner = THIS_MODULE,
277 .attr = elanfreq_attr,
278};
279
280
281static int __init elanfreq_init(void)
282{
283 struct cpuinfo_x86 *c = &cpu_data(0);
284
285 /* Test if we have the right hardware */
286 if ((c->x86_vendor != X86_VENDOR_AMD) ||
287 (c->x86 != 4) || (c->x86_model != 10)) {
288 printk(KERN_INFO "elanfreq: error: no Elan processor found!\n");
289 return -ENODEV;
290 }
291 return cpufreq_register_driver(&elanfreq_driver);
292}
293
294
295static void __exit elanfreq_exit(void)
296{
297 cpufreq_unregister_driver(&elanfreq_driver);
298}
299
300
301module_param(max_freq, int, 0444);
302
303MODULE_LICENSE("GPL");
304MODULE_AUTHOR("Robert Schwebel <r.schwebel@pengutronix.de>, "
305 "Sven Geggus <sven@geggus.net>");
306MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
307
308module_init(elanfreq_init);
309module_exit(elanfreq_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c b/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
deleted file mode 100644
index ffe1f2c92ed3..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
+++ /dev/null
@@ -1,514 +0,0 @@
1/*
2 * Cyrix MediaGX and NatSemi Geode Suspend Modulation
3 * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
4 * (C) 2002 Hiroshi Miura <miura@da-cha.org>
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation
10 *
11 * The author(s) of this software shall not be held liable for damages
12 * of any nature resulting due to the use of this software. This
13 * software is provided AS-IS with no warranties.
14 *
15 * Theoretical note:
16 *
17 * (see Geode(tm) CS5530 manual (rev.4.1) page.56)
18 *
19 * CPU frequency control on NatSemi Geode GX1/GXLV processor and CS55x0
20 * are based on Suspend Modulation.
21 *
22 * Suspend Modulation works by asserting and de-asserting the SUSP# pin
23 * to CPU(GX1/GXLV) for configurable durations. When asserting SUSP#
24 * the CPU enters an idle state. GX1 stops its core clock when SUSP# is
25 * asserted then power consumption is reduced.
26 *
27 * Suspend Modulation's OFF/ON duration are configurable
28 * with 'Suspend Modulation OFF Count Register'
29 * and 'Suspend Modulation ON Count Register'.
30 * These registers are 8bit counters that represent the number of
31 * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
32 * to the processor.
33 *
34 * These counters define a ratio which is the effective frequency
35 * of operation of the system.
36 *
37 * OFF Count
38 * F_eff = Fgx * ----------------------
39 * OFF Count + ON Count
40 *
41 * 0 <= On Count, Off Count <= 255
42 *
43 * From these limits, we can get register values
44 *
45 * off_duration + on_duration <= MAX_DURATION
46 * on_duration = off_duration * (stock_freq - freq) / freq
47 *
48 * off_duration = (freq * DURATION) / stock_freq
49 * on_duration = DURATION - off_duration
50 *
51 *
52 *---------------------------------------------------------------------------
53 *
54 * ChangeLog:
55 * Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org>
56 * - fix on/off register mistake
57 * - fix cpu_khz calc when it stops cpu modulation.
58 *
59 * Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org>
60 * - rewrite for Cyrix MediaGX Cx5510/5520 and
61 * NatSemi Geode Cs5530(A).
62 *
63 * Jul. ??, 2002 Zwane Mwaikambo <zwane@commfireservices.com>
64 * - cs5530_mod patch for 2.4.19-rc1.
65 *
66 *---------------------------------------------------------------------------
67 *
68 * Todo
69 * Test on machines with 5510, 5530, 5530A
70 */
71
72/************************************************************************
73 * Suspend Modulation - Definitions *
74 ************************************************************************/
75
76#include <linux/kernel.h>
77#include <linux/module.h>
78#include <linux/init.h>
79#include <linux/smp.h>
80#include <linux/cpufreq.h>
81#include <linux/pci.h>
82#include <linux/errno.h>
83#include <linux/slab.h>
84
85#include <asm/processor-cyrix.h>
86
87/* PCI config registers, all at F0 */
88#define PCI_PMER1 0x80 /* power management enable register 1 */
89#define PCI_PMER2 0x81 /* power management enable register 2 */
90#define PCI_PMER3 0x82 /* power management enable register 3 */
91#define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */
92#define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
93#define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
94#define PCI_MODON 0x95 /* suspend modulation ON counter register */
95#define PCI_SUSCFG 0x96 /* suspend configuration register */
96
97/* PMER1 bits */
98#define GPM (1<<0) /* global power management */
99#define GIT (1<<1) /* globally enable PM device idle timers */
100#define GTR (1<<2) /* globally enable IO traps */
101#define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */
102#define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */
103
104/* SUSCFG bits */
105#define SUSMOD (1<<0) /* enable/disable suspend modulation */
106/* the below is supported only with cs5530 (after rev.1.2)/cs5530A */
107#define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */
108 /* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
109#define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
110/* the below is supported only with cs5530A */
111#define PWRSVE_ISA (1<<3) /* stop ISA clock */
112#define PWRSVE (1<<4) /* active idle */
113
114struct gxfreq_params {
115 u8 on_duration;
116 u8 off_duration;
117 u8 pci_suscfg;
118 u8 pci_pmer1;
119 u8 pci_pmer2;
120 struct pci_dev *cs55x0;
121};
122
123static struct gxfreq_params *gx_params;
124static int stock_freq;
125
126/* PCI bus clock - defaults to 30.000 if cpu_khz is not available */
127static int pci_busclk;
128module_param(pci_busclk, int, 0444);
129
130/* maximum duration for which the cpu may be suspended
131 * (32us * MAX_DURATION). If no parameter is given, this defaults
132 * to 255.
133 * Note that this leads to a maximum of 8 ms(!) where the CPU clock
134 * is suspended -- processing power is just 0.39% of what it used to be,
135 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
136static int max_duration = 255;
137module_param(max_duration, int, 0444);
138
139/* For the default policy, we want at least some processing power
140 * - let's say 5%. (min = maxfreq / POLICY_MIN_DIV)
141 */
142#define POLICY_MIN_DIV 20
143
144
145/**
146 * we can detect a core multipiler from dir0_lsb
147 * from GX1 datasheet p.56,
148 * MULT[3:0]:
149 * 0000 = SYSCLK multiplied by 4 (test only)
150 * 0001 = SYSCLK multiplied by 10
151 * 0010 = SYSCLK multiplied by 4
152 * 0011 = SYSCLK multiplied by 6
153 * 0100 = SYSCLK multiplied by 9
154 * 0101 = SYSCLK multiplied by 5
155 * 0110 = SYSCLK multiplied by 7
156 * 0111 = SYSCLK multiplied by 8
157 * of 33.3MHz
158 **/
159static int gx_freq_mult[16] = {
160 4, 10, 4, 6, 9, 5, 7, 8,
161 0, 0, 0, 0, 0, 0, 0, 0
162};
163
164
165/****************************************************************
166 * Low Level chipset interface *
167 ****************************************************************/
168static struct pci_device_id gx_chipset_tbl[] __initdata = {
169 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY), },
170 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
171 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
172 { 0, },
173};
174
175static void gx_write_byte(int reg, int value)
176{
177 pci_write_config_byte(gx_params->cs55x0, reg, value);
178}
179
180/**
181 * gx_detect_chipset:
182 *
183 **/
184static __init struct pci_dev *gx_detect_chipset(void)
185{
186 struct pci_dev *gx_pci = NULL;
187
188 /* check if CPU is a MediaGX or a Geode. */
189 if ((boot_cpu_data.x86_vendor != X86_VENDOR_NSC) &&
190 (boot_cpu_data.x86_vendor != X86_VENDOR_CYRIX)) {
191 pr_debug("error: no MediaGX/Geode processor found!\n");
192 return NULL;
193 }
194
195 /* detect which companion chip is used */
196 for_each_pci_dev(gx_pci) {
197 if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
198 return gx_pci;
199 }
200
201 pr_debug("error: no supported chipset found!\n");
202 return NULL;
203}
204
205/**
206 * gx_get_cpuspeed:
207 *
208 * Finds out at which efficient frequency the Cyrix MediaGX/NatSemi
209 * Geode CPU runs.
210 */
211static unsigned int gx_get_cpuspeed(unsigned int cpu)
212{
213 if ((gx_params->pci_suscfg & SUSMOD) == 0)
214 return stock_freq;
215
216 return (stock_freq * gx_params->off_duration)
217 / (gx_params->on_duration + gx_params->off_duration);
218}
219
220/**
221 * gx_validate_speed:
222 * determine current cpu speed
223 *
224 **/
225
226static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration,
227 u8 *off_duration)
228{
229 unsigned int i;
230 u8 tmp_on, tmp_off;
231 int old_tmp_freq = stock_freq;
232 int tmp_freq;
233
234 *off_duration = 1;
235 *on_duration = 0;
236
237 for (i = max_duration; i > 0; i--) {
238 tmp_off = ((khz * i) / stock_freq) & 0xff;
239 tmp_on = i - tmp_off;
240 tmp_freq = (stock_freq * tmp_off) / i;
241 /* if this relation is closer to khz, use this. If it's equal,
242 * prefer it, too - lower latency */
243 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) {
244 *on_duration = tmp_on;
245 *off_duration = tmp_off;
246 old_tmp_freq = tmp_freq;
247 }
248 }
249
250 return old_tmp_freq;
251}
252
253
254/**
255 * gx_set_cpuspeed:
256 * set cpu speed in khz.
257 **/
258
259static void gx_set_cpuspeed(unsigned int khz)
260{
261 u8 suscfg, pmer1;
262 unsigned int new_khz;
263 unsigned long flags;
264 struct cpufreq_freqs freqs;
265
266 freqs.cpu = 0;
267 freqs.old = gx_get_cpuspeed(0);
268
269 new_khz = gx_validate_speed(khz, &gx_params->on_duration,
270 &gx_params->off_duration);
271
272 freqs.new = new_khz;
273
274 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
275 local_irq_save(flags);
276
277
278
279 if (new_khz != stock_freq) {
280 /* if new khz == 100% of CPU speed, it is special case */
281 switch (gx_params->cs55x0->device) {
282 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
283 pmer1 = gx_params->pci_pmer1 | IRQ_SPDUP | VID_SPDUP;
284 /* FIXME: need to test other values -- Zwane,Miura */
285 /* typical 2 to 4ms */
286 gx_write_byte(PCI_IRQTC, 4);
287 /* typical 50 to 100ms */
288 gx_write_byte(PCI_VIDTC, 100);
289 gx_write_byte(PCI_PMER1, pmer1);
290
291 if (gx_params->cs55x0->revision < 0x10) {
292 /* CS5530(rev 1.2, 1.3) */
293 suscfg = gx_params->pci_suscfg|SUSMOD;
294 } else {
295 /* CS5530A,B.. */
296 suscfg = gx_params->pci_suscfg|SUSMOD|PWRSVE;
297 }
298 break;
299 case PCI_DEVICE_ID_CYRIX_5520:
300 case PCI_DEVICE_ID_CYRIX_5510:
301 suscfg = gx_params->pci_suscfg | SUSMOD;
302 break;
303 default:
304 local_irq_restore(flags);
305 pr_debug("fatal: try to set unknown chipset.\n");
306 return;
307 }
308 } else {
309 suscfg = gx_params->pci_suscfg & ~(SUSMOD);
310 gx_params->off_duration = 0;
311 gx_params->on_duration = 0;
312 pr_debug("suspend modulation disabled: cpu runs 100%% speed.\n");
313 }
314
315 gx_write_byte(PCI_MODOFF, gx_params->off_duration);
316 gx_write_byte(PCI_MODON, gx_params->on_duration);
317
318 gx_write_byte(PCI_SUSCFG, suscfg);
319 pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);
320
321 local_irq_restore(flags);
322
323 gx_params->pci_suscfg = suscfg;
324
325 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
326
327 pr_debug("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
328 gx_params->on_duration * 32, gx_params->off_duration * 32);
329 pr_debug("suspend modulation w/ clock speed: %d kHz.\n", freqs.new);
330}
331
332/****************************************************************
333 * High level functions *
334 ****************************************************************/
335
336/*
337 * cpufreq_gx_verify: test if frequency range is valid
338 *
339 * This function checks if a given frequency range in kHz is valid
340 * for the hardware supported by the driver.
341 */
342
343static int cpufreq_gx_verify(struct cpufreq_policy *policy)
344{
345 unsigned int tmp_freq = 0;
346 u8 tmp1, tmp2;
347
348 if (!stock_freq || !policy)
349 return -EINVAL;
350
351 policy->cpu = 0;
352 cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
353 stock_freq);
354
355 /* it needs to be assured that at least one supported frequency is
356 * within policy->min and policy->max. If it is not, policy->max
357 * needs to be increased until one freuqency is supported.
358 * policy->min may not be decreased, though. This way we guarantee a
359 * specific processing capacity.
360 */
361 tmp_freq = gx_validate_speed(policy->min, &tmp1, &tmp2);
362 if (tmp_freq < policy->min)
363 tmp_freq += stock_freq / max_duration;
364 policy->min = tmp_freq;
365 if (policy->min > policy->max)
366 policy->max = tmp_freq;
367 tmp_freq = gx_validate_speed(policy->max, &tmp1, &tmp2);
368 if (tmp_freq > policy->max)
369 tmp_freq -= stock_freq / max_duration;
370 policy->max = tmp_freq;
371 if (policy->max < policy->min)
372 policy->max = policy->min;
373 cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
374 stock_freq);
375
376 return 0;
377}
378
379/*
380 * cpufreq_gx_target:
381 *
382 */
383static int cpufreq_gx_target(struct cpufreq_policy *policy,
384 unsigned int target_freq,
385 unsigned int relation)
386{
387 u8 tmp1, tmp2;
388 unsigned int tmp_freq;
389
390 if (!stock_freq || !policy)
391 return -EINVAL;
392
393 policy->cpu = 0;
394
395 tmp_freq = gx_validate_speed(target_freq, &tmp1, &tmp2);
396 while (tmp_freq < policy->min) {
397 tmp_freq += stock_freq / max_duration;
398 tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
399 }
400 while (tmp_freq > policy->max) {
401 tmp_freq -= stock_freq / max_duration;
402 tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
403 }
404
405 gx_set_cpuspeed(tmp_freq);
406
407 return 0;
408}
409
410static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy)
411{
412 unsigned int maxfreq, curfreq;
413
414 if (!policy || policy->cpu != 0)
415 return -ENODEV;
416
417 /* determine maximum frequency */
418 if (pci_busclk)
419 maxfreq = pci_busclk * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
420 else if (cpu_khz)
421 maxfreq = cpu_khz;
422 else
423 maxfreq = 30000 * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
424
425 stock_freq = maxfreq;
426 curfreq = gx_get_cpuspeed(0);
427
428 pr_debug("cpu max frequency is %d.\n", maxfreq);
429 pr_debug("cpu current frequency is %dkHz.\n", curfreq);
430
431 /* setup basic struct for cpufreq API */
432 policy->cpu = 0;
433
434 if (max_duration < POLICY_MIN_DIV)
435 policy->min = maxfreq / max_duration;
436 else
437 policy->min = maxfreq / POLICY_MIN_DIV;
438 policy->max = maxfreq;
439 policy->cur = curfreq;
440 policy->cpuinfo.min_freq = maxfreq / max_duration;
441 policy->cpuinfo.max_freq = maxfreq;
442 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
443
444 return 0;
445}
446
447/*
448 * cpufreq_gx_init:
449 * MediaGX/Geode GX initialize cpufreq driver
450 */
451static struct cpufreq_driver gx_suspmod_driver = {
452 .get = gx_get_cpuspeed,
453 .verify = cpufreq_gx_verify,
454 .target = cpufreq_gx_target,
455 .init = cpufreq_gx_cpu_init,
456 .name = "gx-suspmod",
457 .owner = THIS_MODULE,
458};
459
460static int __init cpufreq_gx_init(void)
461{
462 int ret;
463 struct gxfreq_params *params;
464 struct pci_dev *gx_pci;
465
466 /* Test if we have the right hardware */
467 gx_pci = gx_detect_chipset();
468 if (gx_pci == NULL)
469 return -ENODEV;
470
471 /* check whether module parameters are sane */
472 if (max_duration > 0xff)
473 max_duration = 0xff;
474
475 pr_debug("geode suspend modulation available.\n");
476
477 params = kzalloc(sizeof(struct gxfreq_params), GFP_KERNEL);
478 if (params == NULL)
479 return -ENOMEM;
480
481 params->cs55x0 = gx_pci;
482 gx_params = params;
483
484 /* keep cs55x0 configurations */
485 pci_read_config_byte(params->cs55x0, PCI_SUSCFG, &(params->pci_suscfg));
486 pci_read_config_byte(params->cs55x0, PCI_PMER1, &(params->pci_pmer1));
487 pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));
488 pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));
489 pci_read_config_byte(params->cs55x0, PCI_MODOFF,
490 &(params->off_duration));
491
492 ret = cpufreq_register_driver(&gx_suspmod_driver);
493 if (ret) {
494 kfree(params);
495 return ret; /* register error! */
496 }
497
498 return 0;
499}
500
501static void __exit cpufreq_gx_exit(void)
502{
503 cpufreq_unregister_driver(&gx_suspmod_driver);
504 pci_dev_put(gx_params->cs55x0);
505 kfree(gx_params);
506}
507
508MODULE_AUTHOR("Hiroshi Miura <miura@da-cha.org>");
509MODULE_DESCRIPTION("Cpufreq driver for Cyrix MediaGX and NatSemi Geode");
510MODULE_LICENSE("GPL");
511
512module_init(cpufreq_gx_init);
513module_exit(cpufreq_gx_exit);
514
diff --git a/arch/x86/kernel/cpu/cpufreq/longhaul.c b/arch/x86/kernel/cpu/cpufreq/longhaul.c
deleted file mode 100644
index f47d26e2a135..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/longhaul.c
+++ /dev/null
@@ -1,1024 +0,0 @@
1/*
2 * (C) 2001-2004 Dave Jones. <davej@redhat.com>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
4 *
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
7 *
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is backward compatible with v1, but adds
12 * LONGHAUL MSR for purpose of both frequency and voltage scaling.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14 * Version 3 of longhaul got renamed to Powersaver and redesigned
15 * to use only the POWERSAVER MSR at 0x110a.
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17 * It's pretty much the same feature wise to longhaul v2, though
18 * there is provision for scaling FSB too, but this doesn't work
19 * too well in practice so we don't even try to use this.
20 *
21 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/cpufreq.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/string.h>
32#include <linux/delay.h>
33#include <linux/timex.h>
34#include <linux/io.h>
35#include <linux/acpi.h>
36
37#include <asm/msr.h>
38#include <acpi/processor.h>
39
40#include "longhaul.h"
41
42#define PFX "longhaul: "
43
44#define TYPE_LONGHAUL_V1 1
45#define TYPE_LONGHAUL_V2 2
46#define TYPE_POWERSAVER 3
47
48#define CPU_SAMUEL 1
49#define CPU_SAMUEL2 2
50#define CPU_EZRA 3
51#define CPU_EZRA_T 4
52#define CPU_NEHEMIAH 5
53#define CPU_NEHEMIAH_C 6
54
55/* Flags */
56#define USE_ACPI_C3 (1 << 1)
57#define USE_NORTHBRIDGE (1 << 2)
58
59static int cpu_model;
60static unsigned int numscales = 16;
61static unsigned int fsb;
62
63static const struct mV_pos *vrm_mV_table;
64static const unsigned char *mV_vrm_table;
65
66static unsigned int highest_speed, lowest_speed; /* kHz */
67static unsigned int minmult, maxmult;
68static int can_scale_voltage;
69static struct acpi_processor *pr;
70static struct acpi_processor_cx *cx;
71static u32 acpi_regs_addr;
72static u8 longhaul_flags;
73static unsigned int longhaul_index;
74
75/* Module parameters */
76static int scale_voltage;
77static int disable_acpi_c3;
78static int revid_errata;
79
80
81/* Clock ratios multiplied by 10 */
82static int mults[32];
83static int eblcr[32];
84static int longhaul_version;
85static struct cpufreq_frequency_table *longhaul_table;
86
87static char speedbuffer[8];
88
89static char *print_speed(int speed)
90{
91 if (speed < 1000) {
92 snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed);
93 return speedbuffer;
94 }
95
96 if (speed%1000 == 0)
97 snprintf(speedbuffer, sizeof(speedbuffer),
98 "%dGHz", speed/1000);
99 else
100 snprintf(speedbuffer, sizeof(speedbuffer),
101 "%d.%dGHz", speed/1000, (speed%1000)/100);
102
103 return speedbuffer;
104}
105
106
107static unsigned int calc_speed(int mult)
108{
109 int khz;
110 khz = (mult/10)*fsb;
111 if (mult%10)
112 khz += fsb/2;
113 khz *= 1000;
114 return khz;
115}
116
117
118static int longhaul_get_cpu_mult(void)
119{
120 unsigned long invalue = 0, lo, hi;
121
122 rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
123 invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
124 if (longhaul_version == TYPE_LONGHAUL_V2 ||
125 longhaul_version == TYPE_POWERSAVER) {
126 if (lo & (1<<27))
127 invalue += 16;
128 }
129 return eblcr[invalue];
130}
131
132/* For processor with BCR2 MSR */
133
134static void do_longhaul1(unsigned int mults_index)
135{
136 union msr_bcr2 bcr2;
137
138 rdmsrl(MSR_VIA_BCR2, bcr2.val);
139 /* Enable software clock multiplier */
140 bcr2.bits.ESOFTBF = 1;
141 bcr2.bits.CLOCKMUL = mults_index & 0xff;
142
143 /* Sync to timer tick */
144 safe_halt();
145 /* Change frequency on next halt or sleep */
146 wrmsrl(MSR_VIA_BCR2, bcr2.val);
147 /* Invoke transition */
148 ACPI_FLUSH_CPU_CACHE();
149 halt();
150
151 /* Disable software clock multiplier */
152 local_irq_disable();
153 rdmsrl(MSR_VIA_BCR2, bcr2.val);
154 bcr2.bits.ESOFTBF = 0;
155 wrmsrl(MSR_VIA_BCR2, bcr2.val);
156}
157
158/* For processor with Longhaul MSR */
159
160static void do_powersaver(int cx_address, unsigned int mults_index,
161 unsigned int dir)
162{
163 union msr_longhaul longhaul;
164 u32 t;
165
166 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
167 /* Setup new frequency */
168 if (!revid_errata)
169 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
170 else
171 longhaul.bits.RevisionKey = 0;
172 longhaul.bits.SoftBusRatio = mults_index & 0xf;
173 longhaul.bits.SoftBusRatio4 = (mults_index & 0x10) >> 4;
174 /* Setup new voltage */
175 if (can_scale_voltage)
176 longhaul.bits.SoftVID = (mults_index >> 8) & 0x1f;
177 /* Sync to timer tick */
178 safe_halt();
179 /* Raise voltage if necessary */
180 if (can_scale_voltage && dir) {
181 longhaul.bits.EnableSoftVID = 1;
182 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
183 /* Change voltage */
184 if (!cx_address) {
185 ACPI_FLUSH_CPU_CACHE();
186 halt();
187 } else {
188 ACPI_FLUSH_CPU_CACHE();
189 /* Invoke C3 */
190 inb(cx_address);
191 /* Dummy op - must do something useless after P_LVL3
192 * read */
193 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
194 }
195 longhaul.bits.EnableSoftVID = 0;
196 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
197 }
198
199 /* Change frequency on next halt or sleep */
200 longhaul.bits.EnableSoftBusRatio = 1;
201 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
202 if (!cx_address) {
203 ACPI_FLUSH_CPU_CACHE();
204 halt();
205 } else {
206 ACPI_FLUSH_CPU_CACHE();
207 /* Invoke C3 */
208 inb(cx_address);
209 /* Dummy op - must do something useless after P_LVL3 read */
210 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
211 }
212 /* Disable bus ratio bit */
213 longhaul.bits.EnableSoftBusRatio = 0;
214 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
215
216 /* Reduce voltage if necessary */
217 if (can_scale_voltage && !dir) {
218 longhaul.bits.EnableSoftVID = 1;
219 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
220 /* Change voltage */
221 if (!cx_address) {
222 ACPI_FLUSH_CPU_CACHE();
223 halt();
224 } else {
225 ACPI_FLUSH_CPU_CACHE();
226 /* Invoke C3 */
227 inb(cx_address);
228 /* Dummy op - must do something useless after P_LVL3
229 * read */
230 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
231 }
232 longhaul.bits.EnableSoftVID = 0;
233 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
234 }
235}
236
237/**
238 * longhaul_set_cpu_frequency()
239 * @mults_index : bitpattern of the new multiplier.
240 *
241 * Sets a new clock ratio.
242 */
243
244static void longhaul_setstate(unsigned int table_index)
245{
246 unsigned int mults_index;
247 int speed, mult;
248 struct cpufreq_freqs freqs;
249 unsigned long flags;
250 unsigned int pic1_mask, pic2_mask;
251 u16 bm_status = 0;
252 u32 bm_timeout = 1000;
253 unsigned int dir = 0;
254
255 mults_index = longhaul_table[table_index].index;
256 /* Safety precautions */
257 mult = mults[mults_index & 0x1f];
258 if (mult == -1)
259 return;
260 speed = calc_speed(mult);
261 if ((speed > highest_speed) || (speed < lowest_speed))
262 return;
263 /* Voltage transition before frequency transition? */
264 if (can_scale_voltage && longhaul_index < table_index)
265 dir = 1;
266
267 freqs.old = calc_speed(longhaul_get_cpu_mult());
268 freqs.new = speed;
269 freqs.cpu = 0; /* longhaul.c is UP only driver */
270
271 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
272
273 pr_debug("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
274 fsb, mult/10, mult%10, print_speed(speed/1000));
275retry_loop:
276 preempt_disable();
277 local_irq_save(flags);
278
279 pic2_mask = inb(0xA1);
280 pic1_mask = inb(0x21); /* works on C3. save mask. */
281 outb(0xFF, 0xA1); /* Overkill */
282 outb(0xFE, 0x21); /* TMR0 only */
283
284 /* Wait while PCI bus is busy. */
285 if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
286 || ((pr != NULL) && pr->flags.bm_control))) {
287 bm_status = inw(acpi_regs_addr);
288 bm_status &= 1 << 4;
289 while (bm_status && bm_timeout) {
290 outw(1 << 4, acpi_regs_addr);
291 bm_timeout--;
292 bm_status = inw(acpi_regs_addr);
293 bm_status &= 1 << 4;
294 }
295 }
296
297 if (longhaul_flags & USE_NORTHBRIDGE) {
298 /* Disable AGP and PCI arbiters */
299 outb(3, 0x22);
300 } else if ((pr != NULL) && pr->flags.bm_control) {
301 /* Disable bus master arbitration */
302 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
303 }
304 switch (longhaul_version) {
305
306 /*
307 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
308 * Software controlled multipliers only.
309 */
310 case TYPE_LONGHAUL_V1:
311 do_longhaul1(mults_index);
312 break;
313
314 /*
315 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
316 *
317 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
318 * Nehemiah can do FSB scaling too, but this has never been proven
319 * to work in practice.
320 */
321 case TYPE_LONGHAUL_V2:
322 case TYPE_POWERSAVER:
323 if (longhaul_flags & USE_ACPI_C3) {
324 /* Don't allow wakeup */
325 acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
326 do_powersaver(cx->address, mults_index, dir);
327 } else {
328 do_powersaver(0, mults_index, dir);
329 }
330 break;
331 }
332
333 if (longhaul_flags & USE_NORTHBRIDGE) {
334 /* Enable arbiters */
335 outb(0, 0x22);
336 } else if ((pr != NULL) && pr->flags.bm_control) {
337 /* Enable bus master arbitration */
338 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
339 }
340 outb(pic2_mask, 0xA1); /* restore mask */
341 outb(pic1_mask, 0x21);
342
343 local_irq_restore(flags);
344 preempt_enable();
345
346 freqs.new = calc_speed(longhaul_get_cpu_mult());
347 /* Check if requested frequency is set. */
348 if (unlikely(freqs.new != speed)) {
349 printk(KERN_INFO PFX "Failed to set requested frequency!\n");
350 /* Revision ID = 1 but processor is expecting revision key
351 * equal to 0. Jumpers at the bottom of processor will change
352 * multiplier and FSB, but will not change bits in Longhaul
353 * MSR nor enable voltage scaling. */
354 if (!revid_errata) {
355 printk(KERN_INFO PFX "Enabling \"Ignore Revision ID\" "
356 "option.\n");
357 revid_errata = 1;
358 msleep(200);
359 goto retry_loop;
360 }
361 /* Why ACPI C3 sometimes doesn't work is a mystery for me.
362 * But it does happen. Processor is entering ACPI C3 state,
363 * but it doesn't change frequency. I tried poking various
364 * bits in northbridge registers, but without success. */
365 if (longhaul_flags & USE_ACPI_C3) {
366 printk(KERN_INFO PFX "Disabling ACPI C3 support.\n");
367 longhaul_flags &= ~USE_ACPI_C3;
368 if (revid_errata) {
369 printk(KERN_INFO PFX "Disabling \"Ignore "
370 "Revision ID\" option.\n");
371 revid_errata = 0;
372 }
373 msleep(200);
374 goto retry_loop;
375 }
376 /* This shouldn't happen. Longhaul ver. 2 was reported not
377 * working on processors without voltage scaling, but with
378 * RevID = 1. RevID errata will make things right. Just
379 * to be 100% sure. */
380 if (longhaul_version == TYPE_LONGHAUL_V2) {
381 printk(KERN_INFO PFX "Switching to Longhaul ver. 1\n");
382 longhaul_version = TYPE_LONGHAUL_V1;
383 msleep(200);
384 goto retry_loop;
385 }
386 }
387 /* Report true CPU frequency */
388 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
389
390 if (!bm_timeout)
391 printk(KERN_INFO PFX "Warning: Timeout while waiting for "
392 "idle PCI bus.\n");
393}
394
395/*
396 * Centaur decided to make life a little more tricky.
397 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
398 * Samuel2 and above have to try and guess what the FSB is.
399 * We do this by assuming we booted at maximum multiplier, and interpolate
400 * between that value multiplied by possible FSBs and cpu_mhz which
401 * was calculated at boot time. Really ugly, but no other way to do this.
402 */
403
404#define ROUNDING 0xf
405
406static int guess_fsb(int mult)
407{
408 int speed = cpu_khz / 1000;
409 int i;
410 int speeds[] = { 666, 1000, 1333, 2000 };
411 int f_max, f_min;
412
413 for (i = 0; i < 4; i++) {
414 f_max = ((speeds[i] * mult) + 50) / 100;
415 f_max += (ROUNDING / 2);
416 f_min = f_max - ROUNDING;
417 if ((speed <= f_max) && (speed >= f_min))
418 return speeds[i] / 10;
419 }
420 return 0;
421}
422
423
424static int __cpuinit longhaul_get_ranges(void)
425{
426 unsigned int i, j, k = 0;
427 unsigned int ratio;
428 int mult;
429
430 /* Get current frequency */
431 mult = longhaul_get_cpu_mult();
432 if (mult == -1) {
433 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
434 return -EINVAL;
435 }
436 fsb = guess_fsb(mult);
437 if (fsb == 0) {
438 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
439 return -EINVAL;
440 }
441 /* Get max multiplier - as we always did.
442 * Longhaul MSR is useful only when voltage scaling is enabled.
443 * C3 is booting at max anyway. */
444 maxmult = mult;
445 /* Get min multiplier */
446 switch (cpu_model) {
447 case CPU_NEHEMIAH:
448 minmult = 50;
449 break;
450 case CPU_NEHEMIAH_C:
451 minmult = 40;
452 break;
453 default:
454 minmult = 30;
455 break;
456 }
457
458 pr_debug("MinMult:%d.%dx MaxMult:%d.%dx\n",
459 minmult/10, minmult%10, maxmult/10, maxmult%10);
460
461 highest_speed = calc_speed(maxmult);
462 lowest_speed = calc_speed(minmult);
463 pr_debug("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
464 print_speed(lowest_speed/1000),
465 print_speed(highest_speed/1000));
466
467 if (lowest_speed == highest_speed) {
468 printk(KERN_INFO PFX "highestspeed == lowest, aborting.\n");
469 return -EINVAL;
470 }
471 if (lowest_speed > highest_speed) {
472 printk(KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
473 lowest_speed, highest_speed);
474 return -EINVAL;
475 }
476
477 longhaul_table = kmalloc((numscales + 1) * sizeof(*longhaul_table),
478 GFP_KERNEL);
479 if (!longhaul_table)
480 return -ENOMEM;
481
482 for (j = 0; j < numscales; j++) {
483 ratio = mults[j];
484 if (ratio == -1)
485 continue;
486 if (ratio > maxmult || ratio < minmult)
487 continue;
488 longhaul_table[k].frequency = calc_speed(ratio);
489 longhaul_table[k].index = j;
490 k++;
491 }
492 if (k <= 1) {
493 kfree(longhaul_table);
494 return -ENODEV;
495 }
496 /* Sort */
497 for (j = 0; j < k - 1; j++) {
498 unsigned int min_f, min_i;
499 min_f = longhaul_table[j].frequency;
500 min_i = j;
501 for (i = j + 1; i < k; i++) {
502 if (longhaul_table[i].frequency < min_f) {
503 min_f = longhaul_table[i].frequency;
504 min_i = i;
505 }
506 }
507 if (min_i != j) {
508 swap(longhaul_table[j].frequency,
509 longhaul_table[min_i].frequency);
510 swap(longhaul_table[j].index,
511 longhaul_table[min_i].index);
512 }
513 }
514
515 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
516
517 /* Find index we are running on */
518 for (j = 0; j < k; j++) {
519 if (mults[longhaul_table[j].index & 0x1f] == mult) {
520 longhaul_index = j;
521 break;
522 }
523 }
524 return 0;
525}
526
527
528static void __cpuinit longhaul_setup_voltagescaling(void)
529{
530 union msr_longhaul longhaul;
531 struct mV_pos minvid, maxvid, vid;
532 unsigned int j, speed, pos, kHz_step, numvscales;
533 int min_vid_speed;
534
535 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
536 if (!(longhaul.bits.RevisionID & 1)) {
537 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
538 return;
539 }
540
541 if (!longhaul.bits.VRMRev) {
542 printk(KERN_INFO PFX "VRM 8.5\n");
543 vrm_mV_table = &vrm85_mV[0];
544 mV_vrm_table = &mV_vrm85[0];
545 } else {
546 printk(KERN_INFO PFX "Mobile VRM\n");
547 if (cpu_model < CPU_NEHEMIAH)
548 return;
549 vrm_mV_table = &mobilevrm_mV[0];
550 mV_vrm_table = &mV_mobilevrm[0];
551 }
552
553 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
554 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
555
556 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
557 printk(KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
558 "Voltage scaling disabled.\n",
559 minvid.mV/1000, minvid.mV%1000,
560 maxvid.mV/1000, maxvid.mV%1000);
561 return;
562 }
563
564 if (minvid.mV == maxvid.mV) {
565 printk(KERN_INFO PFX "Claims to support voltage scaling but "
566 "min & max are both %d.%03d. "
567 "Voltage scaling disabled\n",
568 maxvid.mV/1000, maxvid.mV%1000);
569 return;
570 }
571
572 /* How many voltage steps*/
573 numvscales = maxvid.pos - minvid.pos + 1;
574 printk(KERN_INFO PFX
575 "Max VID=%d.%03d "
576 "Min VID=%d.%03d, "
577 "%d possible voltage scales\n",
578 maxvid.mV/1000, maxvid.mV%1000,
579 minvid.mV/1000, minvid.mV%1000,
580 numvscales);
581
582 /* Calculate max frequency at min voltage */
583 j = longhaul.bits.MinMHzBR;
584 if (longhaul.bits.MinMHzBR4)
585 j += 16;
586 min_vid_speed = eblcr[j];
587 if (min_vid_speed == -1)
588 return;
589 switch (longhaul.bits.MinMHzFSB) {
590 case 0:
591 min_vid_speed *= 13333;
592 break;
593 case 1:
594 min_vid_speed *= 10000;
595 break;
596 case 3:
597 min_vid_speed *= 6666;
598 break;
599 default:
600 return;
601 break;
602 }
603 if (min_vid_speed >= highest_speed)
604 return;
605 /* Calculate kHz for one voltage step */
606 kHz_step = (highest_speed - min_vid_speed) / numvscales;
607
608 j = 0;
609 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
610 speed = longhaul_table[j].frequency;
611 if (speed > min_vid_speed)
612 pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
613 else
614 pos = minvid.pos;
615 longhaul_table[j].index |= mV_vrm_table[pos] << 8;
616 vid = vrm_mV_table[mV_vrm_table[pos]];
617 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n",
618 speed, j, vid.mV);
619 j++;
620 }
621
622 can_scale_voltage = 1;
623 printk(KERN_INFO PFX "Voltage scaling enabled.\n");
624}
625
626
627static int longhaul_verify(struct cpufreq_policy *policy)
628{
629 return cpufreq_frequency_table_verify(policy, longhaul_table);
630}
631
632
633static int longhaul_target(struct cpufreq_policy *policy,
634 unsigned int target_freq, unsigned int relation)
635{
636 unsigned int table_index = 0;
637 unsigned int i;
638 unsigned int dir = 0;
639 u8 vid, current_vid;
640
641 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq,
642 relation, &table_index))
643 return -EINVAL;
644
645 /* Don't set same frequency again */
646 if (longhaul_index == table_index)
647 return 0;
648
649 if (!can_scale_voltage)
650 longhaul_setstate(table_index);
651 else {
652 /* On test system voltage transitions exceeding single
653 * step up or down were turning motherboard off. Both
654 * "ondemand" and "userspace" are unsafe. C7 is doing
655 * this in hardware, C3 is old and we need to do this
656 * in software. */
657 i = longhaul_index;
658 current_vid = (longhaul_table[longhaul_index].index >> 8);
659 current_vid &= 0x1f;
660 if (table_index > longhaul_index)
661 dir = 1;
662 while (i != table_index) {
663 vid = (longhaul_table[i].index >> 8) & 0x1f;
664 if (vid != current_vid) {
665 longhaul_setstate(i);
666 current_vid = vid;
667 msleep(200);
668 }
669 if (dir)
670 i++;
671 else
672 i--;
673 }
674 longhaul_setstate(table_index);
675 }
676 longhaul_index = table_index;
677 return 0;
678}
679
680
681static unsigned int longhaul_get(unsigned int cpu)
682{
683 if (cpu)
684 return 0;
685 return calc_speed(longhaul_get_cpu_mult());
686}
687
688static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
689 u32 nesting_level,
690 void *context, void **return_value)
691{
692 struct acpi_device *d;
693
694 if (acpi_bus_get_device(obj_handle, &d))
695 return 0;
696
697 *return_value = acpi_driver_data(d);
698 return 1;
699}
700
701/* VIA don't support PM2 reg, but have something similar */
702static int enable_arbiter_disable(void)
703{
704 struct pci_dev *dev;
705 int status = 1;
706 int reg;
707 u8 pci_cmd;
708
709 /* Find PLE133 host bridge */
710 reg = 0x78;
711 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
712 NULL);
713 /* Find PM133/VT8605 host bridge */
714 if (dev == NULL)
715 dev = pci_get_device(PCI_VENDOR_ID_VIA,
716 PCI_DEVICE_ID_VIA_8605_0, NULL);
717 /* Find CLE266 host bridge */
718 if (dev == NULL) {
719 reg = 0x76;
720 dev = pci_get_device(PCI_VENDOR_ID_VIA,
721 PCI_DEVICE_ID_VIA_862X_0, NULL);
722 /* Find CN400 V-Link host bridge */
723 if (dev == NULL)
724 dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
725 }
726 if (dev != NULL) {
727 /* Enable access to port 0x22 */
728 pci_read_config_byte(dev, reg, &pci_cmd);
729 if (!(pci_cmd & 1<<7)) {
730 pci_cmd |= 1<<7;
731 pci_write_config_byte(dev, reg, pci_cmd);
732 pci_read_config_byte(dev, reg, &pci_cmd);
733 if (!(pci_cmd & 1<<7)) {
734 printk(KERN_ERR PFX
735 "Can't enable access to port 0x22.\n");
736 status = 0;
737 }
738 }
739 pci_dev_put(dev);
740 return status;
741 }
742 return 0;
743}
744
745static int longhaul_setup_southbridge(void)
746{
747 struct pci_dev *dev;
748 u8 pci_cmd;
749
750 /* Find VT8235 southbridge */
751 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
752 if (dev == NULL)
753 /* Find VT8237 southbridge */
754 dev = pci_get_device(PCI_VENDOR_ID_VIA,
755 PCI_DEVICE_ID_VIA_8237, NULL);
756 if (dev != NULL) {
757 /* Set transition time to max */
758 pci_read_config_byte(dev, 0xec, &pci_cmd);
759 pci_cmd &= ~(1 << 2);
760 pci_write_config_byte(dev, 0xec, pci_cmd);
761 pci_read_config_byte(dev, 0xe4, &pci_cmd);
762 pci_cmd &= ~(1 << 7);
763 pci_write_config_byte(dev, 0xe4, pci_cmd);
764 pci_read_config_byte(dev, 0xe5, &pci_cmd);
765 pci_cmd |= 1 << 7;
766 pci_write_config_byte(dev, 0xe5, pci_cmd);
767 /* Get address of ACPI registers block*/
768 pci_read_config_byte(dev, 0x81, &pci_cmd);
769 if (pci_cmd & 1 << 7) {
770 pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
771 acpi_regs_addr &= 0xff00;
772 printk(KERN_INFO PFX "ACPI I/O at 0x%x\n",
773 acpi_regs_addr);
774 }
775
776 pci_dev_put(dev);
777 return 1;
778 }
779 return 0;
780}
781
782static int __cpuinit longhaul_cpu_init(struct cpufreq_policy *policy)
783{
784 struct cpuinfo_x86 *c = &cpu_data(0);
785 char *cpuname = NULL;
786 int ret;
787 u32 lo, hi;
788
789 /* Check what we have on this motherboard */
790 switch (c->x86_model) {
791 case 6:
792 cpu_model = CPU_SAMUEL;
793 cpuname = "C3 'Samuel' [C5A]";
794 longhaul_version = TYPE_LONGHAUL_V1;
795 memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
796 memcpy(eblcr, samuel1_eblcr, sizeof(samuel1_eblcr));
797 break;
798
799 case 7:
800 switch (c->x86_mask) {
801 case 0:
802 longhaul_version = TYPE_LONGHAUL_V1;
803 cpu_model = CPU_SAMUEL2;
804 cpuname = "C3 'Samuel 2' [C5B]";
805 /* Note, this is not a typo, early Samuel2's had
806 * Samuel1 ratios. */
807 memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
808 memcpy(eblcr, samuel2_eblcr, sizeof(samuel2_eblcr));
809 break;
810 case 1 ... 15:
811 longhaul_version = TYPE_LONGHAUL_V2;
812 if (c->x86_mask < 8) {
813 cpu_model = CPU_SAMUEL2;
814 cpuname = "C3 'Samuel 2' [C5B]";
815 } else {
816 cpu_model = CPU_EZRA;
817 cpuname = "C3 'Ezra' [C5C]";
818 }
819 memcpy(mults, ezra_mults, sizeof(ezra_mults));
820 memcpy(eblcr, ezra_eblcr, sizeof(ezra_eblcr));
821 break;
822 }
823 break;
824
825 case 8:
826 cpu_model = CPU_EZRA_T;
827 cpuname = "C3 'Ezra-T' [C5M]";
828 longhaul_version = TYPE_POWERSAVER;
829 numscales = 32;
830 memcpy(mults, ezrat_mults, sizeof(ezrat_mults));
831 memcpy(eblcr, ezrat_eblcr, sizeof(ezrat_eblcr));
832 break;
833
834 case 9:
835 longhaul_version = TYPE_POWERSAVER;
836 numscales = 32;
837 memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
838 memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
839 switch (c->x86_mask) {
840 case 0 ... 1:
841 cpu_model = CPU_NEHEMIAH;
842 cpuname = "C3 'Nehemiah A' [C5XLOE]";
843 break;
844 case 2 ... 4:
845 cpu_model = CPU_NEHEMIAH;
846 cpuname = "C3 'Nehemiah B' [C5XLOH]";
847 break;
848 case 5 ... 15:
849 cpu_model = CPU_NEHEMIAH_C;
850 cpuname = "C3 'Nehemiah C' [C5P]";
851 break;
852 }
853 break;
854
855 default:
856 cpuname = "Unknown";
857 break;
858 }
859 /* Check Longhaul ver. 2 */
860 if (longhaul_version == TYPE_LONGHAUL_V2) {
861 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
862 if (lo == 0 && hi == 0)
863 /* Looks like MSR isn't present */
864 longhaul_version = TYPE_LONGHAUL_V1;
865 }
866
867 printk(KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
868 switch (longhaul_version) {
869 case TYPE_LONGHAUL_V1:
870 case TYPE_LONGHAUL_V2:
871 printk(KERN_CONT "Longhaul v%d supported.\n", longhaul_version);
872 break;
873 case TYPE_POWERSAVER:
874 printk(KERN_CONT "Powersaver supported.\n");
875 break;
876 };
877
878 /* Doesn't hurt */
879 longhaul_setup_southbridge();
880
881 /* Find ACPI data for processor */
882 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
883 ACPI_UINT32_MAX, &longhaul_walk_callback, NULL,
884 NULL, (void *)&pr);
885
886 /* Check ACPI support for C3 state */
887 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
888 cx = &pr->power.states[ACPI_STATE_C3];
889 if (cx->address > 0 && cx->latency <= 1000)
890 longhaul_flags |= USE_ACPI_C3;
891 }
892 /* Disable if it isn't working */
893 if (disable_acpi_c3)
894 longhaul_flags &= ~USE_ACPI_C3;
895 /* Check if northbridge is friendly */
896 if (enable_arbiter_disable())
897 longhaul_flags |= USE_NORTHBRIDGE;
898
899 /* Check ACPI support for bus master arbiter disable */
900 if (!(longhaul_flags & USE_ACPI_C3
901 || longhaul_flags & USE_NORTHBRIDGE)
902 && ((pr == NULL) || !(pr->flags.bm_control))) {
903 printk(KERN_ERR PFX
904 "No ACPI support. Unsupported northbridge.\n");
905 return -ENODEV;
906 }
907
908 if (longhaul_flags & USE_NORTHBRIDGE)
909 printk(KERN_INFO PFX "Using northbridge support.\n");
910 if (longhaul_flags & USE_ACPI_C3)
911 printk(KERN_INFO PFX "Using ACPI support.\n");
912
913 ret = longhaul_get_ranges();
914 if (ret != 0)
915 return ret;
916
917 if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
918 longhaul_setup_voltagescaling();
919
920 policy->cpuinfo.transition_latency = 200000; /* nsec */
921 policy->cur = calc_speed(longhaul_get_cpu_mult());
922
923 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
924 if (ret)
925 return ret;
926
927 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
928
929 return 0;
930}
931
932static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
933{
934 cpufreq_frequency_table_put_attr(policy->cpu);
935 return 0;
936}
937
938static struct freq_attr *longhaul_attr[] = {
939 &cpufreq_freq_attr_scaling_available_freqs,
940 NULL,
941};
942
943static struct cpufreq_driver longhaul_driver = {
944 .verify = longhaul_verify,
945 .target = longhaul_target,
946 .get = longhaul_get,
947 .init = longhaul_cpu_init,
948 .exit = __devexit_p(longhaul_cpu_exit),
949 .name = "longhaul",
950 .owner = THIS_MODULE,
951 .attr = longhaul_attr,
952};
953
954
955static int __init longhaul_init(void)
956{
957 struct cpuinfo_x86 *c = &cpu_data(0);
958
959 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
960 return -ENODEV;
961
962#ifdef CONFIG_SMP
963 if (num_online_cpus() > 1) {
964 printk(KERN_ERR PFX "More than 1 CPU detected, "
965 "longhaul disabled.\n");
966 return -ENODEV;
967 }
968#endif
969#ifdef CONFIG_X86_IO_APIC
970 if (cpu_has_apic) {
971 printk(KERN_ERR PFX "APIC detected. Longhaul is currently "
972 "broken in this configuration.\n");
973 return -ENODEV;
974 }
975#endif
976 switch (c->x86_model) {
977 case 6 ... 9:
978 return cpufreq_register_driver(&longhaul_driver);
979 case 10:
980 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
981 default:
982 ;
983 }
984
985 return -ENODEV;
986}
987
988
989static void __exit longhaul_exit(void)
990{
991 int i;
992
993 for (i = 0; i < numscales; i++) {
994 if (mults[i] == maxmult) {
995 longhaul_setstate(i);
996 break;
997 }
998 }
999
1000 cpufreq_unregister_driver(&longhaul_driver);
1001 kfree(longhaul_table);
1002}
1003
1004/* Even if BIOS is exporting ACPI C3 state, and it is used
1005 * with success when CPU is idle, this state doesn't
1006 * trigger frequency transition in some cases. */
1007module_param(disable_acpi_c3, int, 0644);
1008MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
1009/* Change CPU voltage with frequency. Very useful to save
1010 * power, but most VIA C3 processors aren't supporting it. */
1011module_param(scale_voltage, int, 0644);
1012MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
1013/* Force revision key to 0 for processors which doesn't
1014 * support voltage scaling, but are introducing itself as
1015 * such. */
1016module_param(revid_errata, int, 0644);
1017MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
1018
1019MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1020MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors.");
1021MODULE_LICENSE("GPL");
1022
1023late_initcall(longhaul_init);
1024module_exit(longhaul_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/longhaul.h b/arch/x86/kernel/cpu/cpufreq/longhaul.h
deleted file mode 100644
index cbf48fbca881..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/longhaul.h
+++ /dev/null
@@ -1,353 +0,0 @@
1/*
2 * longhaul.h
3 * (C) 2003 Dave Jones.
4 *
5 * Licensed under the terms of the GNU GPL License version 2.
6 *
7 * VIA-specific information
8 */
9
10union msr_bcr2 {
11 struct {
12 unsigned Reseved:19, // 18:0
13 ESOFTBF:1, // 19
14 Reserved2:3, // 22:20
15 CLOCKMUL:4, // 26:23
16 Reserved3:5; // 31:27
17 } bits;
18 unsigned long val;
19};
20
21union msr_longhaul {
22 struct {
23 unsigned RevisionID:4, // 3:0
24 RevisionKey:4, // 7:4
25 EnableSoftBusRatio:1, // 8
26 EnableSoftVID:1, // 9
27 EnableSoftBSEL:1, // 10
28 Reserved:3, // 11:13
29 SoftBusRatio4:1, // 14
30 VRMRev:1, // 15
31 SoftBusRatio:4, // 19:16
32 SoftVID:5, // 24:20
33 Reserved2:3, // 27:25
34 SoftBSEL:2, // 29:28
35 Reserved3:2, // 31:30
36 MaxMHzBR:4, // 35:32
37 MaximumVID:5, // 40:36
38 MaxMHzFSB:2, // 42:41
39 MaxMHzBR4:1, // 43
40 Reserved4:4, // 47:44
41 MinMHzBR:4, // 51:48
42 MinimumVID:5, // 56:52
43 MinMHzFSB:2, // 58:57
44 MinMHzBR4:1, // 59
45 Reserved5:4; // 63:60
46 } bits;
47 unsigned long long val;
48};
49
50/*
51 * Clock ratio tables. Div/Mod by 10 to get ratio.
52 * The eblcr values specify the ratio read from the CPU.
53 * The mults values specify what to write to the CPU.
54 */
55
56/*
57 * VIA C3 Samuel 1 & Samuel 2 (stepping 0)
58 */
59static const int __cpuinitdata samuel1_mults[16] = {
60 -1, /* 0000 -> RESERVED */
61 30, /* 0001 -> 3.0x */
62 40, /* 0010 -> 4.0x */
63 -1, /* 0011 -> RESERVED */
64 -1, /* 0100 -> RESERVED */
65 35, /* 0101 -> 3.5x */
66 45, /* 0110 -> 4.5x */
67 55, /* 0111 -> 5.5x */
68 60, /* 1000 -> 6.0x */
69 70, /* 1001 -> 7.0x */
70 80, /* 1010 -> 8.0x */
71 50, /* 1011 -> 5.0x */
72 65, /* 1100 -> 6.5x */
73 75, /* 1101 -> 7.5x */
74 -1, /* 1110 -> RESERVED */
75 -1, /* 1111 -> RESERVED */
76};
77
78static const int __cpuinitdata samuel1_eblcr[16] = {
79 50, /* 0000 -> RESERVED */
80 30, /* 0001 -> 3.0x */
81 40, /* 0010 -> 4.0x */
82 -1, /* 0011 -> RESERVED */
83 55, /* 0100 -> 5.5x */
84 35, /* 0101 -> 3.5x */
85 45, /* 0110 -> 4.5x */
86 -1, /* 0111 -> RESERVED */
87 -1, /* 1000 -> RESERVED */
88 70, /* 1001 -> 7.0x */
89 80, /* 1010 -> 8.0x */
90 60, /* 1011 -> 6.0x */
91 -1, /* 1100 -> RESERVED */
92 75, /* 1101 -> 7.5x */
93 -1, /* 1110 -> RESERVED */
94 65, /* 1111 -> 6.5x */
95};
96
97/*
98 * VIA C3 Samuel2 Stepping 1->15
99 */
100static const int __cpuinitdata samuel2_eblcr[16] = {
101 50, /* 0000 -> 5.0x */
102 30, /* 0001 -> 3.0x */
103 40, /* 0010 -> 4.0x */
104 100, /* 0011 -> 10.0x */
105 55, /* 0100 -> 5.5x */
106 35, /* 0101 -> 3.5x */
107 45, /* 0110 -> 4.5x */
108 110, /* 0111 -> 11.0x */
109 90, /* 1000 -> 9.0x */
110 70, /* 1001 -> 7.0x */
111 80, /* 1010 -> 8.0x */
112 60, /* 1011 -> 6.0x */
113 120, /* 1100 -> 12.0x */
114 75, /* 1101 -> 7.5x */
115 130, /* 1110 -> 13.0x */
116 65, /* 1111 -> 6.5x */
117};
118
119/*
120 * VIA C3 Ezra
121 */
122static const int __cpuinitdata ezra_mults[16] = {
123 100, /* 0000 -> 10.0x */
124 30, /* 0001 -> 3.0x */
125 40, /* 0010 -> 4.0x */
126 90, /* 0011 -> 9.0x */
127 95, /* 0100 -> 9.5x */
128 35, /* 0101 -> 3.5x */
129 45, /* 0110 -> 4.5x */
130 55, /* 0111 -> 5.5x */
131 60, /* 1000 -> 6.0x */
132 70, /* 1001 -> 7.0x */
133 80, /* 1010 -> 8.0x */
134 50, /* 1011 -> 5.0x */
135 65, /* 1100 -> 6.5x */
136 75, /* 1101 -> 7.5x */
137 85, /* 1110 -> 8.5x */
138 120, /* 1111 -> 12.0x */
139};
140
141static const int __cpuinitdata ezra_eblcr[16] = {
142 50, /* 0000 -> 5.0x */
143 30, /* 0001 -> 3.0x */
144 40, /* 0010 -> 4.0x */
145 100, /* 0011 -> 10.0x */
146 55, /* 0100 -> 5.5x */
147 35, /* 0101 -> 3.5x */
148 45, /* 0110 -> 4.5x */
149 95, /* 0111 -> 9.5x */
150 90, /* 1000 -> 9.0x */
151 70, /* 1001 -> 7.0x */
152 80, /* 1010 -> 8.0x */
153 60, /* 1011 -> 6.0x */
154 120, /* 1100 -> 12.0x */
155 75, /* 1101 -> 7.5x */
156 85, /* 1110 -> 8.5x */
157 65, /* 1111 -> 6.5x */
158};
159
160/*
161 * VIA C3 (Ezra-T) [C5M].
162 */
163static const int __cpuinitdata ezrat_mults[32] = {
164 100, /* 0000 -> 10.0x */
165 30, /* 0001 -> 3.0x */
166 40, /* 0010 -> 4.0x */
167 90, /* 0011 -> 9.0x */
168 95, /* 0100 -> 9.5x */
169 35, /* 0101 -> 3.5x */
170 45, /* 0110 -> 4.5x */
171 55, /* 0111 -> 5.5x */
172 60, /* 1000 -> 6.0x */
173 70, /* 1001 -> 7.0x */
174 80, /* 1010 -> 8.0x */
175 50, /* 1011 -> 5.0x */
176 65, /* 1100 -> 6.5x */
177 75, /* 1101 -> 7.5x */
178 85, /* 1110 -> 8.5x */
179 120, /* 1111 -> 12.0x */
180
181 -1, /* 0000 -> RESERVED (10.0x) */
182 110, /* 0001 -> 11.0x */
183 -1, /* 0010 -> 12.0x */
184 -1, /* 0011 -> RESERVED (9.0x)*/
185 105, /* 0100 -> 10.5x */
186 115, /* 0101 -> 11.5x */
187 125, /* 0110 -> 12.5x */
188 135, /* 0111 -> 13.5x */
189 140, /* 1000 -> 14.0x */
190 150, /* 1001 -> 15.0x */
191 160, /* 1010 -> 16.0x */
192 130, /* 1011 -> 13.0x */
193 145, /* 1100 -> 14.5x */
194 155, /* 1101 -> 15.5x */
195 -1, /* 1110 -> RESERVED (13.0x) */
196 -1, /* 1111 -> RESERVED (12.0x) */
197};
198
199static const int __cpuinitdata ezrat_eblcr[32] = {
200 50, /* 0000 -> 5.0x */
201 30, /* 0001 -> 3.0x */
202 40, /* 0010 -> 4.0x */
203 100, /* 0011 -> 10.0x */
204 55, /* 0100 -> 5.5x */
205 35, /* 0101 -> 3.5x */
206 45, /* 0110 -> 4.5x */
207 95, /* 0111 -> 9.5x */
208 90, /* 1000 -> 9.0x */
209 70, /* 1001 -> 7.0x */
210 80, /* 1010 -> 8.0x */
211 60, /* 1011 -> 6.0x */
212 120, /* 1100 -> 12.0x */
213 75, /* 1101 -> 7.5x */
214 85, /* 1110 -> 8.5x */
215 65, /* 1111 -> 6.5x */
216
217 -1, /* 0000 -> RESERVED (9.0x) */
218 110, /* 0001 -> 11.0x */
219 120, /* 0010 -> 12.0x */
220 -1, /* 0011 -> RESERVED (10.0x)*/
221 135, /* 0100 -> 13.5x */
222 115, /* 0101 -> 11.5x */
223 125, /* 0110 -> 12.5x */
224 105, /* 0111 -> 10.5x */
225 130, /* 1000 -> 13.0x */
226 150, /* 1001 -> 15.0x */
227 160, /* 1010 -> 16.0x */
228 140, /* 1011 -> 14.0x */
229 -1, /* 1100 -> RESERVED (12.0x) */
230 155, /* 1101 -> 15.5x */
231 -1, /* 1110 -> RESERVED (13.0x) */
232 145, /* 1111 -> 14.5x */
233};
234
235/*
236 * VIA C3 Nehemiah */
237
238static const int __cpuinitdata nehemiah_mults[32] = {
239 100, /* 0000 -> 10.0x */
240 -1, /* 0001 -> 16.0x */
241 40, /* 0010 -> 4.0x */
242 90, /* 0011 -> 9.0x */
243 95, /* 0100 -> 9.5x */
244 -1, /* 0101 -> RESERVED */
245 45, /* 0110 -> 4.5x */
246 55, /* 0111 -> 5.5x */
247 60, /* 1000 -> 6.0x */
248 70, /* 1001 -> 7.0x */
249 80, /* 1010 -> 8.0x */
250 50, /* 1011 -> 5.0x */
251 65, /* 1100 -> 6.5x */
252 75, /* 1101 -> 7.5x */
253 85, /* 1110 -> 8.5x */
254 120, /* 1111 -> 12.0x */
255 -1, /* 0000 -> 10.0x */
256 110, /* 0001 -> 11.0x */
257 -1, /* 0010 -> 12.0x */
258 -1, /* 0011 -> 9.0x */
259 105, /* 0100 -> 10.5x */
260 115, /* 0101 -> 11.5x */
261 125, /* 0110 -> 12.5x */
262 135, /* 0111 -> 13.5x */
263 140, /* 1000 -> 14.0x */
264 150, /* 1001 -> 15.0x */
265 160, /* 1010 -> 16.0x */
266 130, /* 1011 -> 13.0x */
267 145, /* 1100 -> 14.5x */
268 155, /* 1101 -> 15.5x */
269 -1, /* 1110 -> RESERVED (13.0x) */
270 -1, /* 1111 -> 12.0x */
271};
272
273static const int __cpuinitdata nehemiah_eblcr[32] = {
274 50, /* 0000 -> 5.0x */
275 160, /* 0001 -> 16.0x */
276 40, /* 0010 -> 4.0x */
277 100, /* 0011 -> 10.0x */
278 55, /* 0100 -> 5.5x */
279 -1, /* 0101 -> RESERVED */
280 45, /* 0110 -> 4.5x */
281 95, /* 0111 -> 9.5x */
282 90, /* 1000 -> 9.0x */
283 70, /* 1001 -> 7.0x */
284 80, /* 1010 -> 8.0x */
285 60, /* 1011 -> 6.0x */
286 120, /* 1100 -> 12.0x */
287 75, /* 1101 -> 7.5x */
288 85, /* 1110 -> 8.5x */
289 65, /* 1111 -> 6.5x */
290 90, /* 0000 -> 9.0x */
291 110, /* 0001 -> 11.0x */
292 120, /* 0010 -> 12.0x */
293 100, /* 0011 -> 10.0x */
294 135, /* 0100 -> 13.5x */
295 115, /* 0101 -> 11.5x */
296 125, /* 0110 -> 12.5x */
297 105, /* 0111 -> 10.5x */
298 130, /* 1000 -> 13.0x */
299 150, /* 1001 -> 15.0x */
300 160, /* 1010 -> 16.0x */
301 140, /* 1011 -> 14.0x */
302 120, /* 1100 -> 12.0x */
303 155, /* 1101 -> 15.5x */
304 -1, /* 1110 -> RESERVED (13.0x) */
305 145 /* 1111 -> 14.5x */
306};
307
308/*
309 * Voltage scales. Div/Mod by 1000 to get actual voltage.
310 * Which scale to use depends on the VRM type in use.
311 */
312
313struct mV_pos {
314 unsigned short mV;
315 unsigned short pos;
316};
317
318static const struct mV_pos __cpuinitdata vrm85_mV[32] = {
319 {1250, 8}, {1200, 6}, {1150, 4}, {1100, 2},
320 {1050, 0}, {1800, 30}, {1750, 28}, {1700, 26},
321 {1650, 24}, {1600, 22}, {1550, 20}, {1500, 18},
322 {1450, 16}, {1400, 14}, {1350, 12}, {1300, 10},
323 {1275, 9}, {1225, 7}, {1175, 5}, {1125, 3},
324 {1075, 1}, {1825, 31}, {1775, 29}, {1725, 27},
325 {1675, 25}, {1625, 23}, {1575, 21}, {1525, 19},
326 {1475, 17}, {1425, 15}, {1375, 13}, {1325, 11}
327};
328
329static const unsigned char __cpuinitdata mV_vrm85[32] = {
330 0x04, 0x14, 0x03, 0x13, 0x02, 0x12, 0x01, 0x11,
331 0x00, 0x10, 0x0f, 0x1f, 0x0e, 0x1e, 0x0d, 0x1d,
332 0x0c, 0x1c, 0x0b, 0x1b, 0x0a, 0x1a, 0x09, 0x19,
333 0x08, 0x18, 0x07, 0x17, 0x06, 0x16, 0x05, 0x15
334};
335
336static const struct mV_pos __cpuinitdata mobilevrm_mV[32] = {
337 {1750, 31}, {1700, 30}, {1650, 29}, {1600, 28},
338 {1550, 27}, {1500, 26}, {1450, 25}, {1400, 24},
339 {1350, 23}, {1300, 22}, {1250, 21}, {1200, 20},
340 {1150, 19}, {1100, 18}, {1050, 17}, {1000, 16},
341 {975, 15}, {950, 14}, {925, 13}, {900, 12},
342 {875, 11}, {850, 10}, {825, 9}, {800, 8},
343 {775, 7}, {750, 6}, {725, 5}, {700, 4},
344 {675, 3}, {650, 2}, {625, 1}, {600, 0}
345};
346
347static const unsigned char __cpuinitdata mV_mobilevrm[32] = {
348 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
349 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
350 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
351 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
352};
353
diff --git a/arch/x86/kernel/cpu/cpufreq/longrun.c b/arch/x86/kernel/cpu/cpufreq/longrun.c
deleted file mode 100644
index 34ea359b370e..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/longrun.c
+++ /dev/null
@@ -1,324 +0,0 @@
1/*
2 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
3 *
4 * Licensed under the terms of the GNU GPL License version 2.
5 *
6 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/cpufreq.h>
13#include <linux/timex.h>
14
15#include <asm/msr.h>
16#include <asm/processor.h>
17
18static struct cpufreq_driver longrun_driver;
19
20/**
21 * longrun_{low,high}_freq is needed for the conversion of cpufreq kHz
22 * values into per cent values. In TMTA microcode, the following is valid:
23 * performance_pctg = (current_freq - low_freq)/(high_freq - low_freq)
24 */
25static unsigned int longrun_low_freq, longrun_high_freq;
26
27
28/**
29 * longrun_get_policy - get the current LongRun policy
30 * @policy: struct cpufreq_policy where current policy is written into
31 *
32 * Reads the current LongRun policy by access to MSR_TMTA_LONGRUN_FLAGS
33 * and MSR_TMTA_LONGRUN_CTRL
34 */
35static void __cpuinit longrun_get_policy(struct cpufreq_policy *policy)
36{
37 u32 msr_lo, msr_hi;
38
39 rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
40 pr_debug("longrun flags are %x - %x\n", msr_lo, msr_hi);
41 if (msr_lo & 0x01)
42 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
43 else
44 policy->policy = CPUFREQ_POLICY_POWERSAVE;
45
46 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
47 pr_debug("longrun ctrl is %x - %x\n", msr_lo, msr_hi);
48 msr_lo &= 0x0000007F;
49 msr_hi &= 0x0000007F;
50
51 if (longrun_high_freq <= longrun_low_freq) {
52 /* Assume degenerate Longrun table */
53 policy->min = policy->max = longrun_high_freq;
54 } else {
55 policy->min = longrun_low_freq + msr_lo *
56 ((longrun_high_freq - longrun_low_freq) / 100);
57 policy->max = longrun_low_freq + msr_hi *
58 ((longrun_high_freq - longrun_low_freq) / 100);
59 }
60 policy->cpu = 0;
61}
62
63
64/**
65 * longrun_set_policy - sets a new CPUFreq policy
66 * @policy: new policy
67 *
68 * Sets a new CPUFreq policy on LongRun-capable processors. This function
69 * has to be called with cpufreq_driver locked.
70 */
71static int longrun_set_policy(struct cpufreq_policy *policy)
72{
73 u32 msr_lo, msr_hi;
74 u32 pctg_lo, pctg_hi;
75
76 if (!policy)
77 return -EINVAL;
78
79 if (longrun_high_freq <= longrun_low_freq) {
80 /* Assume degenerate Longrun table */
81 pctg_lo = pctg_hi = 100;
82 } else {
83 pctg_lo = (policy->min - longrun_low_freq) /
84 ((longrun_high_freq - longrun_low_freq) / 100);
85 pctg_hi = (policy->max - longrun_low_freq) /
86 ((longrun_high_freq - longrun_low_freq) / 100);
87 }
88
89 if (pctg_hi > 100)
90 pctg_hi = 100;
91 if (pctg_lo > pctg_hi)
92 pctg_lo = pctg_hi;
93
94 /* performance or economy mode */
95 rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
96 msr_lo &= 0xFFFFFFFE;
97 switch (policy->policy) {
98 case CPUFREQ_POLICY_PERFORMANCE:
99 msr_lo |= 0x00000001;
100 break;
101 case CPUFREQ_POLICY_POWERSAVE:
102 break;
103 }
104 wrmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
105
106 /* lower and upper boundary */
107 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
108 msr_lo &= 0xFFFFFF80;
109 msr_hi &= 0xFFFFFF80;
110 msr_lo |= pctg_lo;
111 msr_hi |= pctg_hi;
112 wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
113
114 return 0;
115}
116
117
118/**
119 * longrun_verify_poliy - verifies a new CPUFreq policy
120 * @policy: the policy to verify
121 *
122 * Validates a new CPUFreq policy. This function has to be called with
123 * cpufreq_driver locked.
124 */
125static int longrun_verify_policy(struct cpufreq_policy *policy)
126{
127 if (!policy)
128 return -EINVAL;
129
130 policy->cpu = 0;
131 cpufreq_verify_within_limits(policy,
132 policy->cpuinfo.min_freq,
133 policy->cpuinfo.max_freq);
134
135 if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&
136 (policy->policy != CPUFREQ_POLICY_PERFORMANCE))
137 return -EINVAL;
138
139 return 0;
140}
141
142static unsigned int longrun_get(unsigned int cpu)
143{
144 u32 eax, ebx, ecx, edx;
145
146 if (cpu)
147 return 0;
148
149 cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
150 pr_debug("cpuid eax is %u\n", eax);
151
152 return eax * 1000;
153}
154
155/**
156 * longrun_determine_freqs - determines the lowest and highest possible core frequency
157 * @low_freq: an int to put the lowest frequency into
158 * @high_freq: an int to put the highest frequency into
159 *
160 * Determines the lowest and highest possible core frequencies on this CPU.
161 * This is necessary to calculate the performance percentage according to
162 * TMTA rules:
163 * performance_pctg = (target_freq - low_freq)/(high_freq - low_freq)
164 */
165static int __cpuinit longrun_determine_freqs(unsigned int *low_freq,
166 unsigned int *high_freq)
167{
168 u32 msr_lo, msr_hi;
169 u32 save_lo, save_hi;
170 u32 eax, ebx, ecx, edx;
171 u32 try_hi;
172 struct cpuinfo_x86 *c = &cpu_data(0);
173
174 if (!low_freq || !high_freq)
175 return -EINVAL;
176
177 if (cpu_has(c, X86_FEATURE_LRTI)) {
178 /* if the LongRun Table Interface is present, the
179 * detection is a bit easier:
180 * For minimum frequency, read out the maximum
181 * level (msr_hi), write that into "currently
182 * selected level", and read out the frequency.
183 * For maximum frequency, read out level zero.
184 */
185 /* minimum */
186 rdmsr(MSR_TMTA_LRTI_READOUT, msr_lo, msr_hi);
187 wrmsr(MSR_TMTA_LRTI_READOUT, msr_hi, msr_hi);
188 rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
189 *low_freq = msr_lo * 1000; /* to kHz */
190
191 /* maximum */
192 wrmsr(MSR_TMTA_LRTI_READOUT, 0, msr_hi);
193 rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
194 *high_freq = msr_lo * 1000; /* to kHz */
195
196 pr_debug("longrun table interface told %u - %u kHz\n",
197 *low_freq, *high_freq);
198
199 if (*low_freq > *high_freq)
200 *low_freq = *high_freq;
201 return 0;
202 }
203
204 /* set the upper border to the value determined during TSC init */
205 *high_freq = (cpu_khz / 1000);
206 *high_freq = *high_freq * 1000;
207 pr_debug("high frequency is %u kHz\n", *high_freq);
208
209 /* get current borders */
210 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
211 save_lo = msr_lo & 0x0000007F;
212 save_hi = msr_hi & 0x0000007F;
213
214 /* if current perf_pctg is larger than 90%, we need to decrease the
215 * upper limit to make the calculation more accurate.
216 */
217 cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
218 /* try decreasing in 10% steps, some processors react only
219 * on some barrier values */
220 for (try_hi = 80; try_hi > 0 && ecx > 90; try_hi -= 10) {
221 /* set to 0 to try_hi perf_pctg */
222 msr_lo &= 0xFFFFFF80;
223 msr_hi &= 0xFFFFFF80;
224 msr_hi |= try_hi;
225 wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
226
227 /* read out current core MHz and current perf_pctg */
228 cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
229
230 /* restore values */
231 wrmsr(MSR_TMTA_LONGRUN_CTRL, save_lo, save_hi);
232 }
233 pr_debug("percentage is %u %%, freq is %u MHz\n", ecx, eax);
234
235 /* performance_pctg = (current_freq - low_freq)/(high_freq - low_freq)
236 * eqals
237 * low_freq * (1 - perf_pctg) = (cur_freq - high_freq * perf_pctg)
238 *
239 * high_freq * perf_pctg is stored tempoarily into "ebx".
240 */
241 ebx = (((cpu_khz / 1000) * ecx) / 100); /* to MHz */
242
243 if ((ecx > 95) || (ecx == 0) || (eax < ebx))
244 return -EIO;
245
246 edx = ((eax - ebx) * 100) / (100 - ecx);
247 *low_freq = edx * 1000; /* back to kHz */
248
249 pr_debug("low frequency is %u kHz\n", *low_freq);
250
251 if (*low_freq > *high_freq)
252 *low_freq = *high_freq;
253
254 return 0;
255}
256
257
258static int __cpuinit longrun_cpu_init(struct cpufreq_policy *policy)
259{
260 int result = 0;
261
262 /* capability check */
263 if (policy->cpu != 0)
264 return -ENODEV;
265
266 /* detect low and high frequency */
267 result = longrun_determine_freqs(&longrun_low_freq, &longrun_high_freq);
268 if (result)
269 return result;
270
271 /* cpuinfo and default policy values */
272 policy->cpuinfo.min_freq = longrun_low_freq;
273 policy->cpuinfo.max_freq = longrun_high_freq;
274 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
275 longrun_get_policy(policy);
276
277 return 0;
278}
279
280
281static struct cpufreq_driver longrun_driver = {
282 .flags = CPUFREQ_CONST_LOOPS,
283 .verify = longrun_verify_policy,
284 .setpolicy = longrun_set_policy,
285 .get = longrun_get,
286 .init = longrun_cpu_init,
287 .name = "longrun",
288 .owner = THIS_MODULE,
289};
290
291
292/**
293 * longrun_init - initializes the Transmeta Crusoe LongRun CPUFreq driver
294 *
295 * Initializes the LongRun support.
296 */
297static int __init longrun_init(void)
298{
299 struct cpuinfo_x86 *c = &cpu_data(0);
300
301 if (c->x86_vendor != X86_VENDOR_TRANSMETA ||
302 !cpu_has(c, X86_FEATURE_LONGRUN))
303 return -ENODEV;
304
305 return cpufreq_register_driver(&longrun_driver);
306}
307
308
309/**
310 * longrun_exit - unregisters LongRun support
311 */
312static void __exit longrun_exit(void)
313{
314 cpufreq_unregister_driver(&longrun_driver);
315}
316
317
318MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
319MODULE_DESCRIPTION("LongRun driver for Transmeta Crusoe and "
320 "Efficeon processors.");
321MODULE_LICENSE("GPL");
322
323module_init(longrun_init);
324module_exit(longrun_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/mperf.c b/arch/x86/kernel/cpu/cpufreq/mperf.c
deleted file mode 100644
index 911e193018ae..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/mperf.c
+++ /dev/null
@@ -1,51 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/smp.h>
3#include <linux/module.h>
4#include <linux/init.h>
5#include <linux/cpufreq.h>
6#include <linux/slab.h>
7
8#include "mperf.h"
9
10static DEFINE_PER_CPU(struct aperfmperf, acfreq_old_perf);
11
12/* Called via smp_call_function_single(), on the target CPU */
13static void read_measured_perf_ctrs(void *_cur)
14{
15 struct aperfmperf *am = _cur;
16
17 get_aperfmperf(am);
18}
19
20/*
21 * Return the measured active (C0) frequency on this CPU since last call
22 * to this function.
23 * Input: cpu number
24 * Return: Average CPU frequency in terms of max frequency (zero on error)
25 *
26 * We use IA32_MPERF and IA32_APERF MSRs to get the measured performance
27 * over a period of time, while CPU is in C0 state.
28 * IA32_MPERF counts at the rate of max advertised frequency
29 * IA32_APERF counts at the rate of actual CPU frequency
30 * Only IA32_APERF/IA32_MPERF ratio is architecturally defined and
31 * no meaning should be associated with absolute values of these MSRs.
32 */
33unsigned int cpufreq_get_measured_perf(struct cpufreq_policy *policy,
34 unsigned int cpu)
35{
36 struct aperfmperf perf;
37 unsigned long ratio;
38 unsigned int retval;
39
40 if (smp_call_function_single(cpu, read_measured_perf_ctrs, &perf, 1))
41 return 0;
42
43 ratio = calc_aperfmperf_ratio(&per_cpu(acfreq_old_perf, cpu), &perf);
44 per_cpu(acfreq_old_perf, cpu) = perf;
45
46 retval = (policy->cpuinfo.max_freq * ratio) >> APERFMPERF_SHIFT;
47
48 return retval;
49}
50EXPORT_SYMBOL_GPL(cpufreq_get_measured_perf);
51MODULE_LICENSE("GPL");
diff --git a/arch/x86/kernel/cpu/cpufreq/mperf.h b/arch/x86/kernel/cpu/cpufreq/mperf.h
deleted file mode 100644
index 5dbf2950dc22..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/mperf.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * (c) 2010 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 */
7
8unsigned int cpufreq_get_measured_perf(struct cpufreq_policy *policy,
9 unsigned int cpu);
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
deleted file mode 100644
index 6be3e0760c26..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * Pentium 4/Xeon CPU on demand clock modulation/speed scaling
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
5 * (C) 2002 Arjan van de Ven <arjanv@redhat.com>
6 * (C) 2002 Tora T. Engstad
7 * All Rights Reserved
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * The author(s) of this software shall not be held liable for damages
15 * of any nature resulting due to the use of this software. This
16 * software is provided AS-IS with no warranties.
17 *
18 * Date Errata Description
19 * 20020525 N44, O17 12.5% or 25% DC causes lockup
20 *
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/smp.h>
27#include <linux/cpufreq.h>
28#include <linux/cpumask.h>
29#include <linux/timex.h>
30
31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/timer.h>
34
35#include "speedstep-lib.h"
36
37#define PFX "p4-clockmod: "
38
39/*
40 * Duty Cycle (3bits), note DC_DISABLE is not specified in
41 * intel docs i just use it to mean disable
42 */
43enum {
44 DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
45 DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
46};
47
48#define DC_ENTRIES 8
49
50
51static int has_N44_O17_errata[NR_CPUS];
52static unsigned int stock_freq;
53static struct cpufreq_driver p4clockmod_driver;
54static unsigned int cpufreq_p4_get(unsigned int cpu);
55
56static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
57{
58 u32 l, h;
59
60 if (!cpu_online(cpu) ||
61 (newstate > DC_DISABLE) || (newstate == DC_RESV))
62 return -EINVAL;
63
64 rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);
65
66 if (l & 0x01)
67 pr_debug("CPU#%d currently thermal throttled\n", cpu);
68
69 if (has_N44_O17_errata[cpu] &&
70 (newstate == DC_25PT || newstate == DC_DFLT))
71 newstate = DC_38PT;
72
73 rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
74 if (newstate == DC_DISABLE) {
75 pr_debug("CPU#%d disabling modulation\n", cpu);
76 wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
77 } else {
78 pr_debug("CPU#%d setting duty cycle to %d%%\n",
79 cpu, ((125 * newstate) / 10));
80 /* bits 63 - 5 : reserved
81 * bit 4 : enable/disable
82 * bits 3-1 : duty cycle
83 * bit 0 : reserved
84 */
85 l = (l & ~14);
86 l = l | (1<<4) | ((newstate & 0x7)<<1);
87 wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
88 }
89
90 return 0;
91}
92
93
94static struct cpufreq_frequency_table p4clockmod_table[] = {
95 {DC_RESV, CPUFREQ_ENTRY_INVALID},
96 {DC_DFLT, 0},
97 {DC_25PT, 0},
98 {DC_38PT, 0},
99 {DC_50PT, 0},
100 {DC_64PT, 0},
101 {DC_75PT, 0},
102 {DC_88PT, 0},
103 {DC_DISABLE, 0},
104 {DC_RESV, CPUFREQ_TABLE_END},
105};
106
107
108static int cpufreq_p4_target(struct cpufreq_policy *policy,
109 unsigned int target_freq,
110 unsigned int relation)
111{
112 unsigned int newstate = DC_RESV;
113 struct cpufreq_freqs freqs;
114 int i;
115
116 if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0],
117 target_freq, relation, &newstate))
118 return -EINVAL;
119
120 freqs.old = cpufreq_p4_get(policy->cpu);
121 freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;
122
123 if (freqs.new == freqs.old)
124 return 0;
125
126 /* notifiers */
127 for_each_cpu(i, policy->cpus) {
128 freqs.cpu = i;
129 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
130 }
131
132 /* run on each logical CPU,
133 * see section 13.15.3 of IA32 Intel Architecture Software
134 * Developer's Manual, Volume 3
135 */
136 for_each_cpu(i, policy->cpus)
137 cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
138
139 /* notifiers */
140 for_each_cpu(i, policy->cpus) {
141 freqs.cpu = i;
142 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
143 }
144
145 return 0;
146}
147
148
149static int cpufreq_p4_verify(struct cpufreq_policy *policy)
150{
151 return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
152}
153
154
155static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
156{
157 if (c->x86 == 0x06) {
158 if (cpu_has(c, X86_FEATURE_EST))
159 printk_once(KERN_WARNING PFX "Warning: EST-capable "
160 "CPU detected. The acpi-cpufreq module offers "
161 "voltage scaling in addition to frequency "
162 "scaling. You should use that instead of "
163 "p4-clockmod, if possible.\n");
164 switch (c->x86_model) {
165 case 0x0E: /* Core */
166 case 0x0F: /* Core Duo */
167 case 0x16: /* Celeron Core */
168 case 0x1C: /* Atom */
169 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
170 return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);
171 case 0x0D: /* Pentium M (Dothan) */
172 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
173 /* fall through */
174 case 0x09: /* Pentium M (Banias) */
175 return speedstep_get_frequency(SPEEDSTEP_CPU_PM);
176 }
177 }
178
179 if (c->x86 != 0xF)
180 return 0;
181
182 /* on P-4s, the TSC runs with constant frequency independent whether
183 * throttling is active or not. */
184 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
185
186 if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) {
187 printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
188 "The speedstep-ich or acpi cpufreq modules offer "
189 "voltage scaling in addition of frequency scaling. "
190 "You should use either one instead of p4-clockmod, "
191 "if possible.\n");
192 return speedstep_get_frequency(SPEEDSTEP_CPU_P4M);
193 }
194
195 return speedstep_get_frequency(SPEEDSTEP_CPU_P4D);
196}
197
198
199
200static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
201{
202 struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
203 int cpuid = 0;
204 unsigned int i;
205
206#ifdef CONFIG_SMP
207 cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
208#endif
209
210 /* Errata workaround */
211 cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
212 switch (cpuid) {
213 case 0x0f07:
214 case 0x0f0a:
215 case 0x0f11:
216 case 0x0f12:
217 has_N44_O17_errata[policy->cpu] = 1;
218 pr_debug("has errata -- disabling low frequencies\n");
219 }
220
221 if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D &&
222 c->x86_model < 2) {
223 /* switch to maximum frequency and measure result */
224 cpufreq_p4_setdc(policy->cpu, DC_DISABLE);
225 recalibrate_cpu_khz();
226 }
227 /* get max frequency */
228 stock_freq = cpufreq_p4_get_frequency(c);
229 if (!stock_freq)
230 return -EINVAL;
231
232 /* table init */
233 for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
234 if ((i < 2) && (has_N44_O17_errata[policy->cpu]))
235 p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
236 else
237 p4clockmod_table[i].frequency = (stock_freq * i)/8;
238 }
239 cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
240
241 /* cpuinfo and default policy values */
242
243 /* the transition latency is set to be 1 higher than the maximum
244 * transition latency of the ondemand governor */
245 policy->cpuinfo.transition_latency = 10000001;
246 policy->cur = stock_freq;
247
248 return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
249}
250
251
252static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
253{
254 cpufreq_frequency_table_put_attr(policy->cpu);
255 return 0;
256}
257
258static unsigned int cpufreq_p4_get(unsigned int cpu)
259{
260 u32 l, h;
261
262 rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
263
264 if (l & 0x10) {
265 l = l >> 1;
266 l &= 0x7;
267 } else
268 l = DC_DISABLE;
269
270 if (l != DC_DISABLE)
271 return stock_freq * l / 8;
272
273 return stock_freq;
274}
275
276static struct freq_attr *p4clockmod_attr[] = {
277 &cpufreq_freq_attr_scaling_available_freqs,
278 NULL,
279};
280
281static struct cpufreq_driver p4clockmod_driver = {
282 .verify = cpufreq_p4_verify,
283 .target = cpufreq_p4_target,
284 .init = cpufreq_p4_cpu_init,
285 .exit = cpufreq_p4_cpu_exit,
286 .get = cpufreq_p4_get,
287 .name = "p4-clockmod",
288 .owner = THIS_MODULE,
289 .attr = p4clockmod_attr,
290};
291
292
293static int __init cpufreq_p4_init(void)
294{
295 struct cpuinfo_x86 *c = &cpu_data(0);
296 int ret;
297
298 /*
299 * THERM_CONTROL is architectural for IA32 now, so
300 * we can rely on the capability checks
301 */
302 if (c->x86_vendor != X86_VENDOR_INTEL)
303 return -ENODEV;
304
305 if (!test_cpu_cap(c, X86_FEATURE_ACPI) ||
306 !test_cpu_cap(c, X86_FEATURE_ACC))
307 return -ENODEV;
308
309 ret = cpufreq_register_driver(&p4clockmod_driver);
310 if (!ret)
311 printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock "
312 "Modulation available\n");
313
314 return ret;
315}
316
317
318static void __exit cpufreq_p4_exit(void)
319{
320 cpufreq_unregister_driver(&p4clockmod_driver);
321}
322
323
324MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>");
325MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
326MODULE_LICENSE("GPL");
327
328late_initcall(cpufreq_p4_init);
329module_exit(cpufreq_p4_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
deleted file mode 100644
index 7b0603eb0129..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
+++ /dev/null
@@ -1,621 +0,0 @@
1/*
2 * pcc-cpufreq.c - Processor Clocking Control firmware cpufreq interface
3 *
4 * Copyright (C) 2009 Red Hat, Matthew Garrett <mjg@redhat.com>
5 * Copyright (C) 2009 Hewlett-Packard Development Company, L.P.
6 * Nagananda Chumbalkar <nagananda.chumbalkar@hp.com>
7 *
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or NON
17 * INFRINGEMENT. See the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/smp.h>
30#include <linux/sched.h>
31#include <linux/cpufreq.h>
32#include <linux/compiler.h>
33#include <linux/slab.h>
34
35#include <linux/acpi.h>
36#include <linux/io.h>
37#include <linux/spinlock.h>
38#include <linux/uaccess.h>
39
40#include <acpi/processor.h>
41
42#define PCC_VERSION "1.10.00"
43#define POLL_LOOPS 300
44
45#define CMD_COMPLETE 0x1
46#define CMD_GET_FREQ 0x0
47#define CMD_SET_FREQ 0x1
48
49#define BUF_SZ 4
50
51struct pcc_register_resource {
52 u8 descriptor;
53 u16 length;
54 u8 space_id;
55 u8 bit_width;
56 u8 bit_offset;
57 u8 access_size;
58 u64 address;
59} __attribute__ ((packed));
60
61struct pcc_memory_resource {
62 u8 descriptor;
63 u16 length;
64 u8 space_id;
65 u8 resource_usage;
66 u8 type_specific;
67 u64 granularity;
68 u64 minimum;
69 u64 maximum;
70 u64 translation_offset;
71 u64 address_length;
72} __attribute__ ((packed));
73
74static struct cpufreq_driver pcc_cpufreq_driver;
75
76struct pcc_header {
77 u32 signature;
78 u16 length;
79 u8 major;
80 u8 minor;
81 u32 features;
82 u16 command;
83 u16 status;
84 u32 latency;
85 u32 minimum_time;
86 u32 maximum_time;
87 u32 nominal;
88 u32 throttled_frequency;
89 u32 minimum_frequency;
90};
91
92static void __iomem *pcch_virt_addr;
93static struct pcc_header __iomem *pcch_hdr;
94
95static DEFINE_SPINLOCK(pcc_lock);
96
97static struct acpi_generic_address doorbell;
98
99static u64 doorbell_preserve;
100static u64 doorbell_write;
101
102static u8 OSC_UUID[16] = {0x9F, 0x2C, 0x9B, 0x63, 0x91, 0x70, 0x1f, 0x49,
103 0xBB, 0x4F, 0xA5, 0x98, 0x2F, 0xA1, 0xB5, 0x46};
104
105struct pcc_cpu {
106 u32 input_offset;
107 u32 output_offset;
108};
109
110static struct pcc_cpu __percpu *pcc_cpu_info;
111
112static int pcc_cpufreq_verify(struct cpufreq_policy *policy)
113{
114 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
115 policy->cpuinfo.max_freq);
116 return 0;
117}
118
119static inline void pcc_cmd(void)
120{
121 u64 doorbell_value;
122 int i;
123
124 acpi_read(&doorbell_value, &doorbell);
125 acpi_write((doorbell_value & doorbell_preserve) | doorbell_write,
126 &doorbell);
127
128 for (i = 0; i < POLL_LOOPS; i++) {
129 if (ioread16(&pcch_hdr->status) & CMD_COMPLETE)
130 break;
131 }
132}
133
134static inline void pcc_clear_mapping(void)
135{
136 if (pcch_virt_addr)
137 iounmap(pcch_virt_addr);
138 pcch_virt_addr = NULL;
139}
140
141static unsigned int pcc_get_freq(unsigned int cpu)
142{
143 struct pcc_cpu *pcc_cpu_data;
144 unsigned int curr_freq;
145 unsigned int freq_limit;
146 u16 status;
147 u32 input_buffer;
148 u32 output_buffer;
149
150 spin_lock(&pcc_lock);
151
152 pr_debug("get: get_freq for CPU %d\n", cpu);
153 pcc_cpu_data = per_cpu_ptr(pcc_cpu_info, cpu);
154
155 input_buffer = 0x1;
156 iowrite32(input_buffer,
157 (pcch_virt_addr + pcc_cpu_data->input_offset));
158 iowrite16(CMD_GET_FREQ, &pcch_hdr->command);
159
160 pcc_cmd();
161
162 output_buffer =
163 ioread32(pcch_virt_addr + pcc_cpu_data->output_offset);
164
165 /* Clear the input buffer - we are done with the current command */
166 memset_io((pcch_virt_addr + pcc_cpu_data->input_offset), 0, BUF_SZ);
167
168 status = ioread16(&pcch_hdr->status);
169 if (status != CMD_COMPLETE) {
170 pr_debug("get: FAILED: for CPU %d, status is %d\n",
171 cpu, status);
172 goto cmd_incomplete;
173 }
174 iowrite16(0, &pcch_hdr->status);
175 curr_freq = (((ioread32(&pcch_hdr->nominal) * (output_buffer & 0xff))
176 / 100) * 1000);
177
178 pr_debug("get: SUCCESS: (virtual) output_offset for cpu %d is "
179 "0x%p, contains a value of: 0x%x. Speed is: %d MHz\n",
180 cpu, (pcch_virt_addr + pcc_cpu_data->output_offset),
181 output_buffer, curr_freq);
182
183 freq_limit = (output_buffer >> 8) & 0xff;
184 if (freq_limit != 0xff) {
185 pr_debug("get: frequency for cpu %d is being temporarily"
186 " capped at %d\n", cpu, curr_freq);
187 }
188
189 spin_unlock(&pcc_lock);
190 return curr_freq;
191
192cmd_incomplete:
193 iowrite16(0, &pcch_hdr->status);
194 spin_unlock(&pcc_lock);
195 return 0;
196}
197
198static int pcc_cpufreq_target(struct cpufreq_policy *policy,
199 unsigned int target_freq,
200 unsigned int relation)
201{
202 struct pcc_cpu *pcc_cpu_data;
203 struct cpufreq_freqs freqs;
204 u16 status;
205 u32 input_buffer;
206 int cpu;
207
208 spin_lock(&pcc_lock);
209 cpu = policy->cpu;
210 pcc_cpu_data = per_cpu_ptr(pcc_cpu_info, cpu);
211
212 pr_debug("target: CPU %d should go to target freq: %d "
213 "(virtual) input_offset is 0x%p\n",
214 cpu, target_freq,
215 (pcch_virt_addr + pcc_cpu_data->input_offset));
216
217 freqs.new = target_freq;
218 freqs.cpu = cpu;
219 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
220
221 input_buffer = 0x1 | (((target_freq * 100)
222 / (ioread32(&pcch_hdr->nominal) * 1000)) << 8);
223 iowrite32(input_buffer,
224 (pcch_virt_addr + pcc_cpu_data->input_offset));
225 iowrite16(CMD_SET_FREQ, &pcch_hdr->command);
226
227 pcc_cmd();
228
229 /* Clear the input buffer - we are done with the current command */
230 memset_io((pcch_virt_addr + pcc_cpu_data->input_offset), 0, BUF_SZ);
231
232 status = ioread16(&pcch_hdr->status);
233 if (status != CMD_COMPLETE) {
234 pr_debug("target: FAILED for cpu %d, with status: 0x%x\n",
235 cpu, status);
236 goto cmd_incomplete;
237 }
238 iowrite16(0, &pcch_hdr->status);
239
240 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
241 pr_debug("target: was SUCCESSFUL for cpu %d\n", cpu);
242 spin_unlock(&pcc_lock);
243
244 return 0;
245
246cmd_incomplete:
247 iowrite16(0, &pcch_hdr->status);
248 spin_unlock(&pcc_lock);
249 return -EINVAL;
250}
251
252static int pcc_get_offset(int cpu)
253{
254 acpi_status status;
255 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
256 union acpi_object *pccp, *offset;
257 struct pcc_cpu *pcc_cpu_data;
258 struct acpi_processor *pr;
259 int ret = 0;
260
261 pr = per_cpu(processors, cpu);
262 pcc_cpu_data = per_cpu_ptr(pcc_cpu_info, cpu);
263
264 status = acpi_evaluate_object(pr->handle, "PCCP", NULL, &buffer);
265 if (ACPI_FAILURE(status))
266 return -ENODEV;
267
268 pccp = buffer.pointer;
269 if (!pccp || pccp->type != ACPI_TYPE_PACKAGE) {
270 ret = -ENODEV;
271 goto out_free;
272 };
273
274 offset = &(pccp->package.elements[0]);
275 if (!offset || offset->type != ACPI_TYPE_INTEGER) {
276 ret = -ENODEV;
277 goto out_free;
278 }
279
280 pcc_cpu_data->input_offset = offset->integer.value;
281
282 offset = &(pccp->package.elements[1]);
283 if (!offset || offset->type != ACPI_TYPE_INTEGER) {
284 ret = -ENODEV;
285 goto out_free;
286 }
287
288 pcc_cpu_data->output_offset = offset->integer.value;
289
290 memset_io((pcch_virt_addr + pcc_cpu_data->input_offset), 0, BUF_SZ);
291 memset_io((pcch_virt_addr + pcc_cpu_data->output_offset), 0, BUF_SZ);
292
293 pr_debug("pcc_get_offset: for CPU %d: pcc_cpu_data "
294 "input_offset: 0x%x, pcc_cpu_data output_offset: 0x%x\n",
295 cpu, pcc_cpu_data->input_offset, pcc_cpu_data->output_offset);
296out_free:
297 kfree(buffer.pointer);
298 return ret;
299}
300
301static int __init pcc_cpufreq_do_osc(acpi_handle *handle)
302{
303 acpi_status status;
304 struct acpi_object_list input;
305 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
306 union acpi_object in_params[4];
307 union acpi_object *out_obj;
308 u32 capabilities[2];
309 u32 errors;
310 u32 supported;
311 int ret = 0;
312
313 input.count = 4;
314 input.pointer = in_params;
315 in_params[0].type = ACPI_TYPE_BUFFER;
316 in_params[0].buffer.length = 16;
317 in_params[0].buffer.pointer = OSC_UUID;
318 in_params[1].type = ACPI_TYPE_INTEGER;
319 in_params[1].integer.value = 1;
320 in_params[2].type = ACPI_TYPE_INTEGER;
321 in_params[2].integer.value = 2;
322 in_params[3].type = ACPI_TYPE_BUFFER;
323 in_params[3].buffer.length = 8;
324 in_params[3].buffer.pointer = (u8 *)&capabilities;
325
326 capabilities[0] = OSC_QUERY_ENABLE;
327 capabilities[1] = 0x1;
328
329 status = acpi_evaluate_object(*handle, "_OSC", &input, &output);
330 if (ACPI_FAILURE(status))
331 return -ENODEV;
332
333 if (!output.length)
334 return -ENODEV;
335
336 out_obj = output.pointer;
337 if (out_obj->type != ACPI_TYPE_BUFFER) {
338 ret = -ENODEV;
339 goto out_free;
340 }
341
342 errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0);
343 if (errors) {
344 ret = -ENODEV;
345 goto out_free;
346 }
347
348 supported = *((u32 *)(out_obj->buffer.pointer + 4));
349 if (!(supported & 0x1)) {
350 ret = -ENODEV;
351 goto out_free;
352 }
353
354 kfree(output.pointer);
355 capabilities[0] = 0x0;
356 capabilities[1] = 0x1;
357
358 status = acpi_evaluate_object(*handle, "_OSC", &input, &output);
359 if (ACPI_FAILURE(status))
360 return -ENODEV;
361
362 if (!output.length)
363 return -ENODEV;
364
365 out_obj = output.pointer;
366 if (out_obj->type != ACPI_TYPE_BUFFER) {
367 ret = -ENODEV;
368 goto out_free;
369 }
370
371 errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0);
372 if (errors) {
373 ret = -ENODEV;
374 goto out_free;
375 }
376
377 supported = *((u32 *)(out_obj->buffer.pointer + 4));
378 if (!(supported & 0x1)) {
379 ret = -ENODEV;
380 goto out_free;
381 }
382
383out_free:
384 kfree(output.pointer);
385 return ret;
386}
387
388static int __init pcc_cpufreq_probe(void)
389{
390 acpi_status status;
391 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
392 struct pcc_memory_resource *mem_resource;
393 struct pcc_register_resource *reg_resource;
394 union acpi_object *out_obj, *member;
395 acpi_handle handle, osc_handle, pcch_handle;
396 int ret = 0;
397
398 status = acpi_get_handle(NULL, "\\_SB", &handle);
399 if (ACPI_FAILURE(status))
400 return -ENODEV;
401
402 status = acpi_get_handle(handle, "PCCH", &pcch_handle);
403 if (ACPI_FAILURE(status))
404 return -ENODEV;
405
406 status = acpi_get_handle(handle, "_OSC", &osc_handle);
407 if (ACPI_SUCCESS(status)) {
408 ret = pcc_cpufreq_do_osc(&osc_handle);
409 if (ret)
410 pr_debug("probe: _OSC evaluation did not succeed\n");
411 /* Firmware's use of _OSC is optional */
412 ret = 0;
413 }
414
415 status = acpi_evaluate_object(handle, "PCCH", NULL, &output);
416 if (ACPI_FAILURE(status))
417 return -ENODEV;
418
419 out_obj = output.pointer;
420 if (out_obj->type != ACPI_TYPE_PACKAGE) {
421 ret = -ENODEV;
422 goto out_free;
423 }
424
425 member = &out_obj->package.elements[0];
426 if (member->type != ACPI_TYPE_BUFFER) {
427 ret = -ENODEV;
428 goto out_free;
429 }
430
431 mem_resource = (struct pcc_memory_resource *)member->buffer.pointer;
432
433 pr_debug("probe: mem_resource descriptor: 0x%x,"
434 " length: %d, space_id: %d, resource_usage: %d,"
435 " type_specific: %d, granularity: 0x%llx,"
436 " minimum: 0x%llx, maximum: 0x%llx,"
437 " translation_offset: 0x%llx, address_length: 0x%llx\n",
438 mem_resource->descriptor, mem_resource->length,
439 mem_resource->space_id, mem_resource->resource_usage,
440 mem_resource->type_specific, mem_resource->granularity,
441 mem_resource->minimum, mem_resource->maximum,
442 mem_resource->translation_offset,
443 mem_resource->address_length);
444
445 if (mem_resource->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) {
446 ret = -ENODEV;
447 goto out_free;
448 }
449
450 pcch_virt_addr = ioremap_nocache(mem_resource->minimum,
451 mem_resource->address_length);
452 if (pcch_virt_addr == NULL) {
453 pr_debug("probe: could not map shared mem region\n");
454 goto out_free;
455 }
456 pcch_hdr = pcch_virt_addr;
457
458 pr_debug("probe: PCCH header (virtual) addr: 0x%p\n", pcch_hdr);
459 pr_debug("probe: PCCH header is at physical address: 0x%llx,"
460 " signature: 0x%x, length: %d bytes, major: %d, minor: %d,"
461 " supported features: 0x%x, command field: 0x%x,"
462 " status field: 0x%x, nominal latency: %d us\n",
463 mem_resource->minimum, ioread32(&pcch_hdr->signature),
464 ioread16(&pcch_hdr->length), ioread8(&pcch_hdr->major),
465 ioread8(&pcch_hdr->minor), ioread32(&pcch_hdr->features),
466 ioread16(&pcch_hdr->command), ioread16(&pcch_hdr->status),
467 ioread32(&pcch_hdr->latency));
468
469 pr_debug("probe: min time between commands: %d us,"
470 " max time between commands: %d us,"
471 " nominal CPU frequency: %d MHz,"
472 " minimum CPU frequency: %d MHz,"
473 " minimum CPU frequency without throttling: %d MHz\n",
474 ioread32(&pcch_hdr->minimum_time),
475 ioread32(&pcch_hdr->maximum_time),
476 ioread32(&pcch_hdr->nominal),
477 ioread32(&pcch_hdr->throttled_frequency),
478 ioread32(&pcch_hdr->minimum_frequency));
479
480 member = &out_obj->package.elements[1];
481 if (member->type != ACPI_TYPE_BUFFER) {
482 ret = -ENODEV;
483 goto pcch_free;
484 }
485
486 reg_resource = (struct pcc_register_resource *)member->buffer.pointer;
487
488 doorbell.space_id = reg_resource->space_id;
489 doorbell.bit_width = reg_resource->bit_width;
490 doorbell.bit_offset = reg_resource->bit_offset;
491 doorbell.access_width = 64;
492 doorbell.address = reg_resource->address;
493
494 pr_debug("probe: doorbell: space_id is %d, bit_width is %d, "
495 "bit_offset is %d, access_width is %d, address is 0x%llx\n",
496 doorbell.space_id, doorbell.bit_width, doorbell.bit_offset,
497 doorbell.access_width, reg_resource->address);
498
499 member = &out_obj->package.elements[2];
500 if (member->type != ACPI_TYPE_INTEGER) {
501 ret = -ENODEV;
502 goto pcch_free;
503 }
504
505 doorbell_preserve = member->integer.value;
506
507 member = &out_obj->package.elements[3];
508 if (member->type != ACPI_TYPE_INTEGER) {
509 ret = -ENODEV;
510 goto pcch_free;
511 }
512
513 doorbell_write = member->integer.value;
514
515 pr_debug("probe: doorbell_preserve: 0x%llx,"
516 " doorbell_write: 0x%llx\n",
517 doorbell_preserve, doorbell_write);
518
519 pcc_cpu_info = alloc_percpu(struct pcc_cpu);
520 if (!pcc_cpu_info) {
521 ret = -ENOMEM;
522 goto pcch_free;
523 }
524
525 printk(KERN_DEBUG "pcc-cpufreq: (v%s) driver loaded with frequency"
526 " limits: %d MHz, %d MHz\n", PCC_VERSION,
527 ioread32(&pcch_hdr->minimum_frequency),
528 ioread32(&pcch_hdr->nominal));
529 kfree(output.pointer);
530 return ret;
531pcch_free:
532 pcc_clear_mapping();
533out_free:
534 kfree(output.pointer);
535 return ret;
536}
537
538static int pcc_cpufreq_cpu_init(struct cpufreq_policy *policy)
539{
540 unsigned int cpu = policy->cpu;
541 unsigned int result = 0;
542
543 if (!pcch_virt_addr) {
544 result = -1;
545 goto out;
546 }
547
548 result = pcc_get_offset(cpu);
549 if (result) {
550 pr_debug("init: PCCP evaluation failed\n");
551 goto out;
552 }
553
554 policy->max = policy->cpuinfo.max_freq =
555 ioread32(&pcch_hdr->nominal) * 1000;
556 policy->min = policy->cpuinfo.min_freq =
557 ioread32(&pcch_hdr->minimum_frequency) * 1000;
558 policy->cur = pcc_get_freq(cpu);
559
560 if (!policy->cur) {
561 pr_debug("init: Unable to get current CPU frequency\n");
562 result = -EINVAL;
563 goto out;
564 }
565
566 pr_debug("init: policy->max is %d, policy->min is %d\n",
567 policy->max, policy->min);
568out:
569 return result;
570}
571
572static int pcc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
573{
574 return 0;
575}
576
577static struct cpufreq_driver pcc_cpufreq_driver = {
578 .flags = CPUFREQ_CONST_LOOPS,
579 .get = pcc_get_freq,
580 .verify = pcc_cpufreq_verify,
581 .target = pcc_cpufreq_target,
582 .init = pcc_cpufreq_cpu_init,
583 .exit = pcc_cpufreq_cpu_exit,
584 .name = "pcc-cpufreq",
585 .owner = THIS_MODULE,
586};
587
588static int __init pcc_cpufreq_init(void)
589{
590 int ret;
591
592 if (acpi_disabled)
593 return 0;
594
595 ret = pcc_cpufreq_probe();
596 if (ret) {
597 pr_debug("pcc_cpufreq_init: PCCH evaluation failed\n");
598 return ret;
599 }
600
601 ret = cpufreq_register_driver(&pcc_cpufreq_driver);
602
603 return ret;
604}
605
606static void __exit pcc_cpufreq_exit(void)
607{
608 cpufreq_unregister_driver(&pcc_cpufreq_driver);
609
610 pcc_clear_mapping();
611
612 free_percpu(pcc_cpu_info);
613}
614
615MODULE_AUTHOR("Matthew Garrett, Naga Chumbalkar");
616MODULE_VERSION(PCC_VERSION);
617MODULE_DESCRIPTION("Processor Clocking Control interface driver");
618MODULE_LICENSE("GPL");
619
620late_initcall(pcc_cpufreq_init);
621module_exit(pcc_cpufreq_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c b/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
deleted file mode 100644
index b3379d6a5c57..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
+++ /dev/null
@@ -1,261 +0,0 @@
1/*
2 * This file was based upon code in Powertweak Linux (http://powertweak.sf.net)
3 * (C) 2000-2003 Dave Jones, Arjan van de Ven, Janne Pänkälä,
4 * Dominik Brodowski.
5 *
6 * Licensed under the terms of the GNU GPL License version 2.
7 *
8 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/cpufreq.h>
15#include <linux/ioport.h>
16#include <linux/timex.h>
17#include <linux/io.h>
18
19#include <asm/msr.h>
20
21#define POWERNOW_IOPORT 0xfff0 /* it doesn't matter where, as long
22 as it is unused */
23
24#define PFX "powernow-k6: "
25static unsigned int busfreq; /* FSB, in 10 kHz */
26static unsigned int max_multiplier;
27
28
29/* Clock ratio multiplied by 10 - see table 27 in AMD#23446 */
30static struct cpufreq_frequency_table clock_ratio[] = {
31 {45, /* 000 -> 4.5x */ 0},
32 {50, /* 001 -> 5.0x */ 0},
33 {40, /* 010 -> 4.0x */ 0},
34 {55, /* 011 -> 5.5x */ 0},
35 {20, /* 100 -> 2.0x */ 0},
36 {30, /* 101 -> 3.0x */ 0},
37 {60, /* 110 -> 6.0x */ 0},
38 {35, /* 111 -> 3.5x */ 0},
39 {0, CPUFREQ_TABLE_END}
40};
41
42
43/**
44 * powernow_k6_get_cpu_multiplier - returns the current FSB multiplier
45 *
46 * Returns the current setting of the frequency multiplier. Core clock
47 * speed is frequency of the Front-Side Bus multiplied with this value.
48 */
49static int powernow_k6_get_cpu_multiplier(void)
50{
51 u64 invalue = 0;
52 u32 msrval;
53
54 msrval = POWERNOW_IOPORT + 0x1;
55 wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
56 invalue = inl(POWERNOW_IOPORT + 0x8);
57 msrval = POWERNOW_IOPORT + 0x0;
58 wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
59
60 return clock_ratio[(invalue >> 5)&7].index;
61}
62
63
64/**
65 * powernow_k6_set_state - set the PowerNow! multiplier
66 * @best_i: clock_ratio[best_i] is the target multiplier
67 *
68 * Tries to change the PowerNow! multiplier
69 */
70static void powernow_k6_set_state(unsigned int best_i)
71{
72 unsigned long outvalue = 0, invalue = 0;
73 unsigned long msrval;
74 struct cpufreq_freqs freqs;
75
76 if (clock_ratio[best_i].index > max_multiplier) {
77 printk(KERN_ERR PFX "invalid target frequency\n");
78 return;
79 }
80
81 freqs.old = busfreq * powernow_k6_get_cpu_multiplier();
82 freqs.new = busfreq * clock_ratio[best_i].index;
83 freqs.cpu = 0; /* powernow-k6.c is UP only driver */
84
85 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
86
87 /* we now need to transform best_i to the BVC format, see AMD#23446 */
88
89 outvalue = (1<<12) | (1<<10) | (1<<9) | (best_i<<5);
90
91 msrval = POWERNOW_IOPORT + 0x1;
92 wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
93 invalue = inl(POWERNOW_IOPORT + 0x8);
94 invalue = invalue & 0xf;
95 outvalue = outvalue | invalue;
96 outl(outvalue , (POWERNOW_IOPORT + 0x8));
97 msrval = POWERNOW_IOPORT + 0x0;
98 wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
99
100 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101
102 return;
103}
104
105
106/**
107 * powernow_k6_verify - verifies a new CPUfreq policy
108 * @policy: new policy
109 *
110 * Policy must be within lowest and highest possible CPU Frequency,
111 * and at least one possible state must be within min and max.
112 */
113static int powernow_k6_verify(struct cpufreq_policy *policy)
114{
115 return cpufreq_frequency_table_verify(policy, &clock_ratio[0]);
116}
117
118
119/**
120 * powernow_k6_setpolicy - sets a new CPUFreq policy
121 * @policy: new policy
122 * @target_freq: the target frequency
123 * @relation: how that frequency relates to achieved frequency
124 * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
125 *
126 * sets a new CPUFreq policy
127 */
128static int powernow_k6_target(struct cpufreq_policy *policy,
129 unsigned int target_freq,
130 unsigned int relation)
131{
132 unsigned int newstate = 0;
133
134 if (cpufreq_frequency_table_target(policy, &clock_ratio[0],
135 target_freq, relation, &newstate))
136 return -EINVAL;
137
138 powernow_k6_set_state(newstate);
139
140 return 0;
141}
142
143
144static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
145{
146 unsigned int i, f;
147 int result;
148
149 if (policy->cpu != 0)
150 return -ENODEV;
151
152 /* get frequencies */
153 max_multiplier = powernow_k6_get_cpu_multiplier();
154 busfreq = cpu_khz / max_multiplier;
155
156 /* table init */
157 for (i = 0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) {
158 f = clock_ratio[i].index;
159 if (f > max_multiplier)
160 clock_ratio[i].frequency = CPUFREQ_ENTRY_INVALID;
161 else
162 clock_ratio[i].frequency = busfreq * f;
163 }
164
165 /* cpuinfo and default policy values */
166 policy->cpuinfo.transition_latency = 200000;
167 policy->cur = busfreq * max_multiplier;
168
169 result = cpufreq_frequency_table_cpuinfo(policy, clock_ratio);
170 if (result)
171 return result;
172
173 cpufreq_frequency_table_get_attr(clock_ratio, policy->cpu);
174
175 return 0;
176}
177
178
179static int powernow_k6_cpu_exit(struct cpufreq_policy *policy)
180{
181 unsigned int i;
182 for (i = 0; i < 8; i++) {
183 if (i == max_multiplier)
184 powernow_k6_set_state(i);
185 }
186 cpufreq_frequency_table_put_attr(policy->cpu);
187 return 0;
188}
189
190static unsigned int powernow_k6_get(unsigned int cpu)
191{
192 unsigned int ret;
193 ret = (busfreq * powernow_k6_get_cpu_multiplier());
194 return ret;
195}
196
197static struct freq_attr *powernow_k6_attr[] = {
198 &cpufreq_freq_attr_scaling_available_freqs,
199 NULL,
200};
201
202static struct cpufreq_driver powernow_k6_driver = {
203 .verify = powernow_k6_verify,
204 .target = powernow_k6_target,
205 .init = powernow_k6_cpu_init,
206 .exit = powernow_k6_cpu_exit,
207 .get = powernow_k6_get,
208 .name = "powernow-k6",
209 .owner = THIS_MODULE,
210 .attr = powernow_k6_attr,
211};
212
213
214/**
215 * powernow_k6_init - initializes the k6 PowerNow! CPUFreq driver
216 *
217 * Initializes the K6 PowerNow! support. Returns -ENODEV on unsupported
218 * devices, -EINVAL or -ENOMEM on problems during initiatization, and zero
219 * on success.
220 */
221static int __init powernow_k6_init(void)
222{
223 struct cpuinfo_x86 *c = &cpu_data(0);
224
225 if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 5) ||
226 ((c->x86_model != 12) && (c->x86_model != 13)))
227 return -ENODEV;
228
229 if (!request_region(POWERNOW_IOPORT, 16, "PowerNow!")) {
230 printk(KERN_INFO PFX "PowerNow IOPORT region already used.\n");
231 return -EIO;
232 }
233
234 if (cpufreq_register_driver(&powernow_k6_driver)) {
235 release_region(POWERNOW_IOPORT, 16);
236 return -EINVAL;
237 }
238
239 return 0;
240}
241
242
243/**
244 * powernow_k6_exit - unregisters AMD K6-2+/3+ PowerNow! support
245 *
246 * Unregisters AMD K6-2+ / K6-3+ PowerNow! support.
247 */
248static void __exit powernow_k6_exit(void)
249{
250 cpufreq_unregister_driver(&powernow_k6_driver);
251 release_region(POWERNOW_IOPORT, 16);
252}
253
254
255MODULE_AUTHOR("Arjan van de Ven, Dave Jones <davej@redhat.com>, "
256 "Dominik Brodowski <linux@brodo.de>");
257MODULE_DESCRIPTION("PowerNow! driver for AMD K6-2+ / K6-3+ processors.");
258MODULE_LICENSE("GPL");
259
260module_init(powernow_k6_init);
261module_exit(powernow_k6_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
deleted file mode 100644
index d71d9f372359..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
+++ /dev/null
@@ -1,747 +0,0 @@
1/*
2 * AMD K7 Powernow driver.
3 * (C) 2003 Dave Jones on behalf of SuSE Labs.
4 * (C) 2003-2004 Dave Jones <davej@redhat.com>
5 *
6 * Licensed under the terms of the GNU GPL License version 2.
7 * Based upon datasheets & sample CPUs kindly provided by AMD.
8 *
9 * Errata 5:
10 * CPU may fail to execute a FID/VID change in presence of interrupt.
11 * - We cli/sti on stepping A0 CPUs around the FID/VID transition.
12 * Errata 15:
13 * CPU with half frequency multipliers may hang upon wakeup from disconnect.
14 * - We disable half multipliers if ACPI is used on A0 stepping CPUs.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
21#include <linux/cpufreq.h>
22#include <linux/slab.h>
23#include <linux/string.h>
24#include <linux/dmi.h>
25#include <linux/timex.h>
26#include <linux/io.h>
27
28#include <asm/timer.h> /* Needed for recalibrate_cpu_khz() */
29#include <asm/msr.h>
30#include <asm/system.h>
31
32#ifdef CONFIG_X86_POWERNOW_K7_ACPI
33#include <linux/acpi.h>
34#include <acpi/processor.h>
35#endif
36
37#include "powernow-k7.h"
38
39#define PFX "powernow: "
40
41
42struct psb_s {
43 u8 signature[10];
44 u8 tableversion;
45 u8 flags;
46 u16 settlingtime;
47 u8 reserved1;
48 u8 numpst;
49};
50
51struct pst_s {
52 u32 cpuid;
53 u8 fsbspeed;
54 u8 maxfid;
55 u8 startvid;
56 u8 numpstates;
57};
58
59#ifdef CONFIG_X86_POWERNOW_K7_ACPI
60union powernow_acpi_control_t {
61 struct {
62 unsigned long fid:5,
63 vid:5,
64 sgtc:20,
65 res1:2;
66 } bits;
67 unsigned long val;
68};
69#endif
70
71/* divide by 1000 to get VCore voltage in V. */
72static const int mobile_vid_table[32] = {
73 2000, 1950, 1900, 1850, 1800, 1750, 1700, 1650,
74 1600, 1550, 1500, 1450, 1400, 1350, 1300, 0,
75 1275, 1250, 1225, 1200, 1175, 1150, 1125, 1100,
76 1075, 1050, 1025, 1000, 975, 950, 925, 0,
77};
78
79/* divide by 10 to get FID. */
80static const int fid_codes[32] = {
81 110, 115, 120, 125, 50, 55, 60, 65,
82 70, 75, 80, 85, 90, 95, 100, 105,
83 30, 190, 40, 200, 130, 135, 140, 210,
84 150, 225, 160, 165, 170, 180, -1, -1,
85};
86
87/* This parameter is used in order to force ACPI instead of legacy method for
88 * configuration purpose.
89 */
90
91static int acpi_force;
92
93static struct cpufreq_frequency_table *powernow_table;
94
95static unsigned int can_scale_bus;
96static unsigned int can_scale_vid;
97static unsigned int minimum_speed = -1;
98static unsigned int maximum_speed;
99static unsigned int number_scales;
100static unsigned int fsb;
101static unsigned int latency;
102static char have_a0;
103
104static int check_fsb(unsigned int fsbspeed)
105{
106 int delta;
107 unsigned int f = fsb / 1000;
108
109 delta = (fsbspeed > f) ? fsbspeed - f : f - fsbspeed;
110 return delta < 5;
111}
112
113static int check_powernow(void)
114{
115 struct cpuinfo_x86 *c = &cpu_data(0);
116 unsigned int maxei, eax, ebx, ecx, edx;
117
118 if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 6)) {
119#ifdef MODULE
120 printk(KERN_INFO PFX "This module only works with "
121 "AMD K7 CPUs\n");
122#endif
123 return 0;
124 }
125
126 /* Get maximum capabilities */
127 maxei = cpuid_eax(0x80000000);
128 if (maxei < 0x80000007) { /* Any powernow info ? */
129#ifdef MODULE
130 printk(KERN_INFO PFX "No powernow capabilities detected\n");
131#endif
132 return 0;
133 }
134
135 if ((c->x86_model == 6) && (c->x86_mask == 0)) {
136 printk(KERN_INFO PFX "K7 660[A0] core detected, "
137 "enabling errata workarounds\n");
138 have_a0 = 1;
139 }
140
141 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
142
143 /* Check we can actually do something before we say anything.*/
144 if (!(edx & (1 << 1 | 1 << 2)))
145 return 0;
146
147 printk(KERN_INFO PFX "PowerNOW! Technology present. Can scale: ");
148
149 if (edx & 1 << 1) {
150 printk("frequency");
151 can_scale_bus = 1;
152 }
153
154 if ((edx & (1 << 1 | 1 << 2)) == 0x6)
155 printk(" and ");
156
157 if (edx & 1 << 2) {
158 printk("voltage");
159 can_scale_vid = 1;
160 }
161
162 printk(".\n");
163 return 1;
164}
165
166#ifdef CONFIG_X86_POWERNOW_K7_ACPI
167static void invalidate_entry(unsigned int entry)
168{
169 powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID;
170}
171#endif
172
173static int get_ranges(unsigned char *pst)
174{
175 unsigned int j;
176 unsigned int speed;
177 u8 fid, vid;
178
179 powernow_table = kzalloc((sizeof(struct cpufreq_frequency_table) *
180 (number_scales + 1)), GFP_KERNEL);
181 if (!powernow_table)
182 return -ENOMEM;
183
184 for (j = 0 ; j < number_scales; j++) {
185 fid = *pst++;
186
187 powernow_table[j].frequency = (fsb * fid_codes[fid]) / 10;
188 powernow_table[j].index = fid; /* lower 8 bits */
189
190 speed = powernow_table[j].frequency;
191
192 if ((fid_codes[fid] % 10) == 5) {
193#ifdef CONFIG_X86_POWERNOW_K7_ACPI
194 if (have_a0 == 1)
195 invalidate_entry(j);
196#endif
197 }
198
199 if (speed < minimum_speed)
200 minimum_speed = speed;
201 if (speed > maximum_speed)
202 maximum_speed = speed;
203
204 vid = *pst++;
205 powernow_table[j].index |= (vid << 8); /* upper 8 bits */
206
207 pr_debug(" FID: 0x%x (%d.%dx [%dMHz]) "
208 "VID: 0x%x (%d.%03dV)\n", fid, fid_codes[fid] / 10,
209 fid_codes[fid] % 10, speed/1000, vid,
210 mobile_vid_table[vid]/1000,
211 mobile_vid_table[vid]%1000);
212 }
213 powernow_table[number_scales].frequency = CPUFREQ_TABLE_END;
214 powernow_table[number_scales].index = 0;
215
216 return 0;
217}
218
219
220static void change_FID(int fid)
221{
222 union msr_fidvidctl fidvidctl;
223
224 rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val);
225 if (fidvidctl.bits.FID != fid) {
226 fidvidctl.bits.SGTC = latency;
227 fidvidctl.bits.FID = fid;
228 fidvidctl.bits.VIDC = 0;
229 fidvidctl.bits.FIDC = 1;
230 wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val);
231 }
232}
233
234
235static void change_VID(int vid)
236{
237 union msr_fidvidctl fidvidctl;
238
239 rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val);
240 if (fidvidctl.bits.VID != vid) {
241 fidvidctl.bits.SGTC = latency;
242 fidvidctl.bits.VID = vid;
243 fidvidctl.bits.FIDC = 0;
244 fidvidctl.bits.VIDC = 1;
245 wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val);
246 }
247}
248
249
250static void change_speed(unsigned int index)
251{
252 u8 fid, vid;
253 struct cpufreq_freqs freqs;
254 union msr_fidvidstatus fidvidstatus;
255 int cfid;
256
257 /* fid are the lower 8 bits of the index we stored into
258 * the cpufreq frequency table in powernow_decode_bios,
259 * vid are the upper 8 bits.
260 */
261
262 fid = powernow_table[index].index & 0xFF;
263 vid = (powernow_table[index].index & 0xFF00) >> 8;
264
265 freqs.cpu = 0;
266
267 rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
268 cfid = fidvidstatus.bits.CFID;
269 freqs.old = fsb * fid_codes[cfid] / 10;
270
271 freqs.new = powernow_table[index].frequency;
272
273 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
274
275 /* Now do the magic poking into the MSRs. */
276
277 if (have_a0 == 1) /* A0 errata 5 */
278 local_irq_disable();
279
280 if (freqs.old > freqs.new) {
281 /* Going down, so change FID first */
282 change_FID(fid);
283 change_VID(vid);
284 } else {
285 /* Going up, so change VID first */
286 change_VID(vid);
287 change_FID(fid);
288 }
289
290
291 if (have_a0 == 1)
292 local_irq_enable();
293
294 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
295}
296
297
298#ifdef CONFIG_X86_POWERNOW_K7_ACPI
299
300static struct acpi_processor_performance *acpi_processor_perf;
301
302static int powernow_acpi_init(void)
303{
304 int i;
305 int retval = 0;
306 union powernow_acpi_control_t pc;
307
308 if (acpi_processor_perf != NULL && powernow_table != NULL) {
309 retval = -EINVAL;
310 goto err0;
311 }
312
313 acpi_processor_perf = kzalloc(sizeof(struct acpi_processor_performance),
314 GFP_KERNEL);
315 if (!acpi_processor_perf) {
316 retval = -ENOMEM;
317 goto err0;
318 }
319
320 if (!zalloc_cpumask_var(&acpi_processor_perf->shared_cpu_map,
321 GFP_KERNEL)) {
322 retval = -ENOMEM;
323 goto err05;
324 }
325
326 if (acpi_processor_register_performance(acpi_processor_perf, 0)) {
327 retval = -EIO;
328 goto err1;
329 }
330
331 if (acpi_processor_perf->control_register.space_id !=
332 ACPI_ADR_SPACE_FIXED_HARDWARE) {
333 retval = -ENODEV;
334 goto err2;
335 }
336
337 if (acpi_processor_perf->status_register.space_id !=
338 ACPI_ADR_SPACE_FIXED_HARDWARE) {
339 retval = -ENODEV;
340 goto err2;
341 }
342
343 number_scales = acpi_processor_perf->state_count;
344
345 if (number_scales < 2) {
346 retval = -ENODEV;
347 goto err2;
348 }
349
350 powernow_table = kzalloc((sizeof(struct cpufreq_frequency_table) *
351 (number_scales + 1)), GFP_KERNEL);
352 if (!powernow_table) {
353 retval = -ENOMEM;
354 goto err2;
355 }
356
357 pc.val = (unsigned long) acpi_processor_perf->states[0].control;
358 for (i = 0; i < number_scales; i++) {
359 u8 fid, vid;
360 struct acpi_processor_px *state =
361 &acpi_processor_perf->states[i];
362 unsigned int speed, speed_mhz;
363
364 pc.val = (unsigned long) state->control;
365 pr_debug("acpi: P%d: %d MHz %d mW %d uS control %08x SGTC %d\n",
366 i,
367 (u32) state->core_frequency,
368 (u32) state->power,
369 (u32) state->transition_latency,
370 (u32) state->control,
371 pc.bits.sgtc);
372
373 vid = pc.bits.vid;
374 fid = pc.bits.fid;
375
376 powernow_table[i].frequency = fsb * fid_codes[fid] / 10;
377 powernow_table[i].index = fid; /* lower 8 bits */
378 powernow_table[i].index |= (vid << 8); /* upper 8 bits */
379
380 speed = powernow_table[i].frequency;
381 speed_mhz = speed / 1000;
382
383 /* processor_perflib will multiply the MHz value by 1000 to
384 * get a KHz value (e.g. 1266000). However, powernow-k7 works
385 * with true KHz values (e.g. 1266768). To ensure that all
386 * powernow frequencies are available, we must ensure that
387 * ACPI doesn't restrict them, so we round up the MHz value
388 * to ensure that perflib's computed KHz value is greater than
389 * or equal to powernow's KHz value.
390 */
391 if (speed % 1000 > 0)
392 speed_mhz++;
393
394 if ((fid_codes[fid] % 10) == 5) {
395 if (have_a0 == 1)
396 invalidate_entry(i);
397 }
398
399 pr_debug(" FID: 0x%x (%d.%dx [%dMHz]) "
400 "VID: 0x%x (%d.%03dV)\n", fid, fid_codes[fid] / 10,
401 fid_codes[fid] % 10, speed_mhz, vid,
402 mobile_vid_table[vid]/1000,
403 mobile_vid_table[vid]%1000);
404
405 if (state->core_frequency != speed_mhz) {
406 state->core_frequency = speed_mhz;
407 pr_debug(" Corrected ACPI frequency to %d\n",
408 speed_mhz);
409 }
410
411 if (latency < pc.bits.sgtc)
412 latency = pc.bits.sgtc;
413
414 if (speed < minimum_speed)
415 minimum_speed = speed;
416 if (speed > maximum_speed)
417 maximum_speed = speed;
418 }
419
420 powernow_table[i].frequency = CPUFREQ_TABLE_END;
421 powernow_table[i].index = 0;
422
423 /* notify BIOS that we exist */
424 acpi_processor_notify_smm(THIS_MODULE);
425
426 return 0;
427
428err2:
429 acpi_processor_unregister_performance(acpi_processor_perf, 0);
430err1:
431 free_cpumask_var(acpi_processor_perf->shared_cpu_map);
432err05:
433 kfree(acpi_processor_perf);
434err0:
435 printk(KERN_WARNING PFX "ACPI perflib can not be used on "
436 "this platform\n");
437 acpi_processor_perf = NULL;
438 return retval;
439}
440#else
441static int powernow_acpi_init(void)
442{
443 printk(KERN_INFO PFX "no support for ACPI processor found."
444 " Please recompile your kernel with ACPI processor\n");
445 return -EINVAL;
446}
447#endif
448
449static void print_pst_entry(struct pst_s *pst, unsigned int j)
450{
451 pr_debug("PST:%d (@%p)\n", j, pst);
452 pr_debug(" cpuid: 0x%x fsb: %d maxFID: 0x%x startvid: 0x%x\n",
453 pst->cpuid, pst->fsbspeed, pst->maxfid, pst->startvid);
454}
455
456static int powernow_decode_bios(int maxfid, int startvid)
457{
458 struct psb_s *psb;
459 struct pst_s *pst;
460 unsigned int i, j;
461 unsigned char *p;
462 unsigned int etuple;
463 unsigned int ret;
464
465 etuple = cpuid_eax(0x80000001);
466
467 for (i = 0xC0000; i < 0xffff0 ; i += 16) {
468
469 p = phys_to_virt(i);
470
471 if (memcmp(p, "AMDK7PNOW!", 10) == 0) {
472 pr_debug("Found PSB header at %p\n", p);
473 psb = (struct psb_s *) p;
474 pr_debug("Table version: 0x%x\n", psb->tableversion);
475 if (psb->tableversion != 0x12) {
476 printk(KERN_INFO PFX "Sorry, only v1.2 tables"
477 " supported right now\n");
478 return -ENODEV;
479 }
480
481 pr_debug("Flags: 0x%x\n", psb->flags);
482 if ((psb->flags & 1) == 0)
483 pr_debug("Mobile voltage regulator\n");
484 else
485 pr_debug("Desktop voltage regulator\n");
486
487 latency = psb->settlingtime;
488 if (latency < 100) {
489 printk(KERN_INFO PFX "BIOS set settling time "
490 "to %d microseconds. "
491 "Should be at least 100. "
492 "Correcting.\n", latency);
493 latency = 100;
494 }
495 pr_debug("Settling Time: %d microseconds.\n",
496 psb->settlingtime);
497 pr_debug("Has %d PST tables. (Only dumping ones "
498 "relevant to this CPU).\n",
499 psb->numpst);
500
501 p += sizeof(struct psb_s);
502
503 pst = (struct pst_s *) p;
504
505 for (j = 0; j < psb->numpst; j++) {
506 pst = (struct pst_s *) p;
507 number_scales = pst->numpstates;
508
509 if ((etuple == pst->cpuid) &&
510 check_fsb(pst->fsbspeed) &&
511 (maxfid == pst->maxfid) &&
512 (startvid == pst->startvid)) {
513 print_pst_entry(pst, j);
514 p = (char *)pst + sizeof(struct pst_s);
515 ret = get_ranges(p);
516 return ret;
517 } else {
518 unsigned int k;
519 p = (char *)pst + sizeof(struct pst_s);
520 for (k = 0; k < number_scales; k++)
521 p += 2;
522 }
523 }
524 printk(KERN_INFO PFX "No PST tables match this cpuid "
525 "(0x%x)\n", etuple);
526 printk(KERN_INFO PFX "This is indicative of a broken "
527 "BIOS.\n");
528
529 return -EINVAL;
530 }
531 p++;
532 }
533
534 return -ENODEV;
535}
536
537
538static int powernow_target(struct cpufreq_policy *policy,
539 unsigned int target_freq,
540 unsigned int relation)
541{
542 unsigned int newstate;
543
544 if (cpufreq_frequency_table_target(policy, powernow_table, target_freq,
545 relation, &newstate))
546 return -EINVAL;
547
548 change_speed(newstate);
549
550 return 0;
551}
552
553
554static int powernow_verify(struct cpufreq_policy *policy)
555{
556 return cpufreq_frequency_table_verify(policy, powernow_table);
557}
558
559/*
560 * We use the fact that the bus frequency is somehow
561 * a multiple of 100000/3 khz, then we compute sgtc according
562 * to this multiple.
563 * That way, we match more how AMD thinks all of that work.
564 * We will then get the same kind of behaviour already tested under
565 * the "well-known" other OS.
566 */
567static int __cpuinit fixup_sgtc(void)
568{
569 unsigned int sgtc;
570 unsigned int m;
571
572 m = fsb / 3333;
573 if ((m % 10) >= 5)
574 m += 5;
575
576 m /= 10;
577
578 sgtc = 100 * m * latency;
579 sgtc = sgtc / 3;
580 if (sgtc > 0xfffff) {
581 printk(KERN_WARNING PFX "SGTC too large %d\n", sgtc);
582 sgtc = 0xfffff;
583 }
584 return sgtc;
585}
586
587static unsigned int powernow_get(unsigned int cpu)
588{
589 union msr_fidvidstatus fidvidstatus;
590 unsigned int cfid;
591
592 if (cpu)
593 return 0;
594 rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
595 cfid = fidvidstatus.bits.CFID;
596
597 return fsb * fid_codes[cfid] / 10;
598}
599
600
601static int __cpuinit acer_cpufreq_pst(const struct dmi_system_id *d)
602{
603 printk(KERN_WARNING PFX
604 "%s laptop with broken PST tables in BIOS detected.\n",
605 d->ident);
606 printk(KERN_WARNING PFX
607 "You need to downgrade to 3A21 (09/09/2002), or try a newer "
608 "BIOS than 3A71 (01/20/2003)\n");
609 printk(KERN_WARNING PFX
610 "cpufreq scaling has been disabled as a result of this.\n");
611 return 0;
612}
613
614/*
615 * Some Athlon laptops have really fucked PST tables.
616 * A BIOS update is all that can save them.
617 * Mention this, and disable cpufreq.
618 */
619static struct dmi_system_id __cpuinitdata powernow_dmi_table[] = {
620 {
621 .callback = acer_cpufreq_pst,
622 .ident = "Acer Aspire",
623 .matches = {
624 DMI_MATCH(DMI_SYS_VENDOR, "Insyde Software"),
625 DMI_MATCH(DMI_BIOS_VERSION, "3A71"),
626 },
627 },
628 { }
629};
630
631static int __cpuinit powernow_cpu_init(struct cpufreq_policy *policy)
632{
633 union msr_fidvidstatus fidvidstatus;
634 int result;
635
636 if (policy->cpu != 0)
637 return -ENODEV;
638
639 rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
640
641 recalibrate_cpu_khz();
642
643 fsb = (10 * cpu_khz) / fid_codes[fidvidstatus.bits.CFID];
644 if (!fsb) {
645 printk(KERN_WARNING PFX "can not determine bus frequency\n");
646 return -EINVAL;
647 }
648 pr_debug("FSB: %3dMHz\n", fsb/1000);
649
650 if (dmi_check_system(powernow_dmi_table) || acpi_force) {
651 printk(KERN_INFO PFX "PSB/PST known to be broken. "
652 "Trying ACPI instead\n");
653 result = powernow_acpi_init();
654 } else {
655 result = powernow_decode_bios(fidvidstatus.bits.MFID,
656 fidvidstatus.bits.SVID);
657 if (result) {
658 printk(KERN_INFO PFX "Trying ACPI perflib\n");
659 maximum_speed = 0;
660 minimum_speed = -1;
661 latency = 0;
662 result = powernow_acpi_init();
663 if (result) {
664 printk(KERN_INFO PFX
665 "ACPI and legacy methods failed\n");
666 }
667 } else {
668 /* SGTC use the bus clock as timer */
669 latency = fixup_sgtc();
670 printk(KERN_INFO PFX "SGTC: %d\n", latency);
671 }
672 }
673
674 if (result)
675 return result;
676
677 printk(KERN_INFO PFX "Minimum speed %d MHz. Maximum speed %d MHz.\n",
678 minimum_speed/1000, maximum_speed/1000);
679
680 policy->cpuinfo.transition_latency =
681 cpufreq_scale(2000000UL, fsb, latency);
682
683 policy->cur = powernow_get(0);
684
685 cpufreq_frequency_table_get_attr(powernow_table, policy->cpu);
686
687 return cpufreq_frequency_table_cpuinfo(policy, powernow_table);
688}
689
690static int powernow_cpu_exit(struct cpufreq_policy *policy)
691{
692 cpufreq_frequency_table_put_attr(policy->cpu);
693
694#ifdef CONFIG_X86_POWERNOW_K7_ACPI
695 if (acpi_processor_perf) {
696 acpi_processor_unregister_performance(acpi_processor_perf, 0);
697 free_cpumask_var(acpi_processor_perf->shared_cpu_map);
698 kfree(acpi_processor_perf);
699 }
700#endif
701
702 kfree(powernow_table);
703 return 0;
704}
705
706static struct freq_attr *powernow_table_attr[] = {
707 &cpufreq_freq_attr_scaling_available_freqs,
708 NULL,
709};
710
711static struct cpufreq_driver powernow_driver = {
712 .verify = powernow_verify,
713 .target = powernow_target,
714 .get = powernow_get,
715#ifdef CONFIG_X86_POWERNOW_K7_ACPI
716 .bios_limit = acpi_processor_get_bios_limit,
717#endif
718 .init = powernow_cpu_init,
719 .exit = powernow_cpu_exit,
720 .name = "powernow-k7",
721 .owner = THIS_MODULE,
722 .attr = powernow_table_attr,
723};
724
725static int __init powernow_init(void)
726{
727 if (check_powernow() == 0)
728 return -ENODEV;
729 return cpufreq_register_driver(&powernow_driver);
730}
731
732
733static void __exit powernow_exit(void)
734{
735 cpufreq_unregister_driver(&powernow_driver);
736}
737
738module_param(acpi_force, int, 0444);
739MODULE_PARM_DESC(acpi_force, "Force ACPI to be used.");
740
741MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
742MODULE_DESCRIPTION("Powernow driver for AMD K7 processors.");
743MODULE_LICENSE("GPL");
744
745late_initcall(powernow_init);
746module_exit(powernow_exit);
747
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.h b/arch/x86/kernel/cpu/cpufreq/powernow-k7.h
deleted file mode 100644
index 35fb4eaf6e1c..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * (C) 2003 Dave Jones.
3 *
4 * Licensed under the terms of the GNU GPL License version 2.
5 *
6 * AMD-specific information
7 *
8 */
9
10union msr_fidvidctl {
11 struct {
12 unsigned FID:5, // 4:0
13 reserved1:3, // 7:5
14 VID:5, // 12:8
15 reserved2:3, // 15:13
16 FIDC:1, // 16
17 VIDC:1, // 17
18 reserved3:2, // 19:18
19 FIDCHGRATIO:1, // 20
20 reserved4:11, // 31-21
21 SGTC:20, // 32:51
22 reserved5:12; // 63:52
23 } bits;
24 unsigned long long val;
25};
26
27union msr_fidvidstatus {
28 struct {
29 unsigned CFID:5, // 4:0
30 reserved1:3, // 7:5
31 SFID:5, // 12:8
32 reserved2:3, // 15:13
33 MFID:5, // 20:16
34 reserved3:11, // 31:21
35 CVID:5, // 36:32
36 reserved4:3, // 39:37
37 SVID:5, // 44:40
38 reserved5:3, // 47:45
39 MVID:5, // 52:48
40 reserved6:11; // 63:53
41 } bits;
42 unsigned long long val;
43};
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
deleted file mode 100644
index 83479b6fb9a1..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ /dev/null
@@ -1,1607 +0,0 @@
1/*
2 * (c) 2003-2010 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 *
7 * Support : mark.langsdorf@amd.com
8 *
9 * Based on the powernow-k7.c module written by Dave Jones.
10 * (C) 2003 Dave Jones on behalf of SuSE Labs
11 * (C) 2004 Dominik Brodowski <linux@brodo.de>
12 * (C) 2004 Pavel Machek <pavel@ucw.cz>
13 * Licensed under the terms of the GNU GPL License version 2.
14 * Based upon datasheets & sample CPUs kindly provided by AMD.
15 *
16 * Valuable input gratefully received from Dave Jones, Pavel Machek,
17 * Dominik Brodowski, Jacob Shin, and others.
18 * Originally developed by Paul Devriendt.
19 * Processor information obtained from Chapter 9 (Power and Thermal Management)
20 * of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
21 * Opteron Processors" available for download from www.amd.com
22 *
23 * Tables for specific CPUs can be inferred from
24 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf
25 */
26
27#include <linux/kernel.h>
28#include <linux/smp.h>
29#include <linux/module.h>
30#include <linux/init.h>
31#include <linux/cpufreq.h>
32#include <linux/slab.h>
33#include <linux/string.h>
34#include <linux/cpumask.h>
35#include <linux/sched.h> /* for current / set_cpus_allowed() */
36#include <linux/io.h>
37#include <linux/delay.h>
38
39#include <asm/msr.h>
40
41#include <linux/acpi.h>
42#include <linux/mutex.h>
43#include <acpi/processor.h>
44
45#define PFX "powernow-k8: "
46#define VERSION "version 2.20.00"
47#include "powernow-k8.h"
48#include "mperf.h"
49
50/* serialize freq changes */
51static DEFINE_MUTEX(fidvid_mutex);
52
53static DEFINE_PER_CPU(struct powernow_k8_data *, powernow_data);
54
55static int cpu_family = CPU_OPTERON;
56
57/* core performance boost */
58static bool cpb_capable, cpb_enabled;
59static struct msr __percpu *msrs;
60
61static struct cpufreq_driver cpufreq_amd64_driver;
62
63#ifndef CONFIG_SMP
64static inline const struct cpumask *cpu_core_mask(int cpu)
65{
66 return cpumask_of(0);
67}
68#endif
69
70/* Return a frequency in MHz, given an input fid */
71static u32 find_freq_from_fid(u32 fid)
72{
73 return 800 + (fid * 100);
74}
75
76/* Return a frequency in KHz, given an input fid */
77static u32 find_khz_freq_from_fid(u32 fid)
78{
79 return 1000 * find_freq_from_fid(fid);
80}
81
82static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data,
83 u32 pstate)
84{
85 return data[pstate].frequency;
86}
87
88/* Return the vco fid for an input fid
89 *
90 * Each "low" fid has corresponding "high" fid, and you can get to "low" fids
91 * only from corresponding high fids. This returns "high" fid corresponding to
92 * "low" one.
93 */
94static u32 convert_fid_to_vco_fid(u32 fid)
95{
96 if (fid < HI_FID_TABLE_BOTTOM)
97 return 8 + (2 * fid);
98 else
99 return fid;
100}
101
102/*
103 * Return 1 if the pending bit is set. Unless we just instructed the processor
104 * to transition to a new state, seeing this bit set is really bad news.
105 */
106static int pending_bit_stuck(void)
107{
108 u32 lo, hi;
109
110 if (cpu_family == CPU_HW_PSTATE)
111 return 0;
112
113 rdmsr(MSR_FIDVID_STATUS, lo, hi);
114 return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
115}
116
117/*
118 * Update the global current fid / vid values from the status msr.
119 * Returns 1 on error.
120 */
121static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
122{
123 u32 lo, hi;
124 u32 i = 0;
125
126 if (cpu_family == CPU_HW_PSTATE) {
127 rdmsr(MSR_PSTATE_STATUS, lo, hi);
128 i = lo & HW_PSTATE_MASK;
129 data->currpstate = i;
130
131 /*
132 * a workaround for family 11h erratum 311 might cause
133 * an "out-of-range Pstate if the core is in Pstate-0
134 */
135 if ((boot_cpu_data.x86 == 0x11) && (i >= data->numps))
136 data->currpstate = HW_PSTATE_0;
137
138 return 0;
139 }
140 do {
141 if (i++ > 10000) {
142 pr_debug("detected change pending stuck\n");
143 return 1;
144 }
145 rdmsr(MSR_FIDVID_STATUS, lo, hi);
146 } while (lo & MSR_S_LO_CHANGE_PENDING);
147
148 data->currvid = hi & MSR_S_HI_CURRENT_VID;
149 data->currfid = lo & MSR_S_LO_CURRENT_FID;
150
151 return 0;
152}
153
154/* the isochronous relief time */
155static void count_off_irt(struct powernow_k8_data *data)
156{
157 udelay((1 << data->irt) * 10);
158 return;
159}
160
161/* the voltage stabilization time */
162static void count_off_vst(struct powernow_k8_data *data)
163{
164 udelay(data->vstable * VST_UNITS_20US);
165 return;
166}
167
168/* need to init the control msr to a safe value (for each cpu) */
169static void fidvid_msr_init(void)
170{
171 u32 lo, hi;
172 u8 fid, vid;
173
174 rdmsr(MSR_FIDVID_STATUS, lo, hi);
175 vid = hi & MSR_S_HI_CURRENT_VID;
176 fid = lo & MSR_S_LO_CURRENT_FID;
177 lo = fid | (vid << MSR_C_LO_VID_SHIFT);
178 hi = MSR_C_HI_STP_GNT_BENIGN;
179 pr_debug("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), lo, hi);
180 wrmsr(MSR_FIDVID_CTL, lo, hi);
181}
182
183/* write the new fid value along with the other control fields to the msr */
184static int write_new_fid(struct powernow_k8_data *data, u32 fid)
185{
186 u32 lo;
187 u32 savevid = data->currvid;
188 u32 i = 0;
189
190 if ((fid & INVALID_FID_MASK) || (data->currvid & INVALID_VID_MASK)) {
191 printk(KERN_ERR PFX "internal error - overflow on fid write\n");
192 return 1;
193 }
194
195 lo = fid;
196 lo |= (data->currvid << MSR_C_LO_VID_SHIFT);
197 lo |= MSR_C_LO_INIT_FID_VID;
198
199 pr_debug("writing fid 0x%x, lo 0x%x, hi 0x%x\n",
200 fid, lo, data->plllock * PLL_LOCK_CONVERSION);
201
202 do {
203 wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION);
204 if (i++ > 100) {
205 printk(KERN_ERR PFX
206 "Hardware error - pending bit very stuck - "
207 "no further pstate changes possible\n");
208 return 1;
209 }
210 } while (query_current_values_with_pending_wait(data));
211
212 count_off_irt(data);
213
214 if (savevid != data->currvid) {
215 printk(KERN_ERR PFX
216 "vid change on fid trans, old 0x%x, new 0x%x\n",
217 savevid, data->currvid);
218 return 1;
219 }
220
221 if (fid != data->currfid) {
222 printk(KERN_ERR PFX
223 "fid trans failed, fid 0x%x, curr 0x%x\n", fid,
224 data->currfid);
225 return 1;
226 }
227
228 return 0;
229}
230
231/* Write a new vid to the hardware */
232static int write_new_vid(struct powernow_k8_data *data, u32 vid)
233{
234 u32 lo;
235 u32 savefid = data->currfid;
236 int i = 0;
237
238 if ((data->currfid & INVALID_FID_MASK) || (vid & INVALID_VID_MASK)) {
239 printk(KERN_ERR PFX "internal error - overflow on vid write\n");
240 return 1;
241 }
242
243 lo = data->currfid;
244 lo |= (vid << MSR_C_LO_VID_SHIFT);
245 lo |= MSR_C_LO_INIT_FID_VID;
246
247 pr_debug("writing vid 0x%x, lo 0x%x, hi 0x%x\n",
248 vid, lo, STOP_GRANT_5NS);
249
250 do {
251 wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS);
252 if (i++ > 100) {
253 printk(KERN_ERR PFX "internal error - pending bit "
254 "very stuck - no further pstate "
255 "changes possible\n");
256 return 1;
257 }
258 } while (query_current_values_with_pending_wait(data));
259
260 if (savefid != data->currfid) {
261 printk(KERN_ERR PFX "fid changed on vid trans, old "
262 "0x%x new 0x%x\n",
263 savefid, data->currfid);
264 return 1;
265 }
266
267 if (vid != data->currvid) {
268 printk(KERN_ERR PFX "vid trans failed, vid 0x%x, "
269 "curr 0x%x\n",
270 vid, data->currvid);
271 return 1;
272 }
273
274 return 0;
275}
276
277/*
278 * Reduce the vid by the max of step or reqvid.
279 * Decreasing vid codes represent increasing voltages:
280 * vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of VID_OFF is off.
281 */
282static int decrease_vid_code_by_step(struct powernow_k8_data *data,
283 u32 reqvid, u32 step)
284{
285 if ((data->currvid - reqvid) > step)
286 reqvid = data->currvid - step;
287
288 if (write_new_vid(data, reqvid))
289 return 1;
290
291 count_off_vst(data);
292
293 return 0;
294}
295
296/* Change hardware pstate by single MSR write */
297static int transition_pstate(struct powernow_k8_data *data, u32 pstate)
298{
299 wrmsr(MSR_PSTATE_CTRL, pstate, 0);
300 data->currpstate = pstate;
301 return 0;
302}
303
304/* Change Opteron/Athlon64 fid and vid, by the 3 phases. */
305static int transition_fid_vid(struct powernow_k8_data *data,
306 u32 reqfid, u32 reqvid)
307{
308 if (core_voltage_pre_transition(data, reqvid, reqfid))
309 return 1;
310
311 if (core_frequency_transition(data, reqfid))
312 return 1;
313
314 if (core_voltage_post_transition(data, reqvid))
315 return 1;
316
317 if (query_current_values_with_pending_wait(data))
318 return 1;
319
320 if ((reqfid != data->currfid) || (reqvid != data->currvid)) {
321 printk(KERN_ERR PFX "failed (cpu%d): req 0x%x 0x%x, "
322 "curr 0x%x 0x%x\n",
323 smp_processor_id(),
324 reqfid, reqvid, data->currfid, data->currvid);
325 return 1;
326 }
327
328 pr_debug("transitioned (cpu%d): new fid 0x%x, vid 0x%x\n",
329 smp_processor_id(), data->currfid, data->currvid);
330
331 return 0;
332}
333
334/* Phase 1 - core voltage transition ... setup voltage */
335static int core_voltage_pre_transition(struct powernow_k8_data *data,
336 u32 reqvid, u32 reqfid)
337{
338 u32 rvosteps = data->rvo;
339 u32 savefid = data->currfid;
340 u32 maxvid, lo, rvomult = 1;
341
342 pr_debug("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, "
343 "reqvid 0x%x, rvo 0x%x\n",
344 smp_processor_id(),
345 data->currfid, data->currvid, reqvid, data->rvo);
346
347 if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP))
348 rvomult = 2;
349 rvosteps *= rvomult;
350 rdmsr(MSR_FIDVID_STATUS, lo, maxvid);
351 maxvid = 0x1f & (maxvid >> 16);
352 pr_debug("ph1 maxvid=0x%x\n", maxvid);
353 if (reqvid < maxvid) /* lower numbers are higher voltages */
354 reqvid = maxvid;
355
356 while (data->currvid > reqvid) {
357 pr_debug("ph1: curr 0x%x, req vid 0x%x\n",
358 data->currvid, reqvid);
359 if (decrease_vid_code_by_step(data, reqvid, data->vidmvs))
360 return 1;
361 }
362
363 while ((rvosteps > 0) &&
364 ((rvomult * data->rvo + data->currvid) > reqvid)) {
365 if (data->currvid == maxvid) {
366 rvosteps = 0;
367 } else {
368 pr_debug("ph1: changing vid for rvo, req 0x%x\n",
369 data->currvid - 1);
370 if (decrease_vid_code_by_step(data, data->currvid-1, 1))
371 return 1;
372 rvosteps--;
373 }
374 }
375
376 if (query_current_values_with_pending_wait(data))
377 return 1;
378
379 if (savefid != data->currfid) {
380 printk(KERN_ERR PFX "ph1 err, currfid changed 0x%x\n",
381 data->currfid);
382 return 1;
383 }
384
385 pr_debug("ph1 complete, currfid 0x%x, currvid 0x%x\n",
386 data->currfid, data->currvid);
387
388 return 0;
389}
390
391/* Phase 2 - core frequency transition */
392static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid)
393{
394 u32 vcoreqfid, vcocurrfid, vcofiddiff;
395 u32 fid_interval, savevid = data->currvid;
396
397 if (data->currfid == reqfid) {
398 printk(KERN_ERR PFX "ph2 null fid transition 0x%x\n",
399 data->currfid);
400 return 0;
401 }
402
403 pr_debug("ph2 (cpu%d): starting, currfid 0x%x, currvid 0x%x, "
404 "reqfid 0x%x\n",
405 smp_processor_id(),
406 data->currfid, data->currvid, reqfid);
407
408 vcoreqfid = convert_fid_to_vco_fid(reqfid);
409 vcocurrfid = convert_fid_to_vco_fid(data->currfid);
410 vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid
411 : vcoreqfid - vcocurrfid;
412
413 if ((reqfid <= LO_FID_TABLE_TOP) && (data->currfid <= LO_FID_TABLE_TOP))
414 vcofiddiff = 0;
415
416 while (vcofiddiff > 2) {
417 (data->currfid & 1) ? (fid_interval = 1) : (fid_interval = 2);
418
419 if (reqfid > data->currfid) {
420 if (data->currfid > LO_FID_TABLE_TOP) {
421 if (write_new_fid(data,
422 data->currfid + fid_interval))
423 return 1;
424 } else {
425 if (write_new_fid
426 (data,
427 2 + convert_fid_to_vco_fid(data->currfid)))
428 return 1;
429 }
430 } else {
431 if (write_new_fid(data, data->currfid - fid_interval))
432 return 1;
433 }
434
435 vcocurrfid = convert_fid_to_vco_fid(data->currfid);
436 vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid
437 : vcoreqfid - vcocurrfid;
438 }
439
440 if (write_new_fid(data, reqfid))
441 return 1;
442
443 if (query_current_values_with_pending_wait(data))
444 return 1;
445
446 if (data->currfid != reqfid) {
447 printk(KERN_ERR PFX
448 "ph2: mismatch, failed fid transition, "
449 "curr 0x%x, req 0x%x\n",
450 data->currfid, reqfid);
451 return 1;
452 }
453
454 if (savevid != data->currvid) {
455 printk(KERN_ERR PFX "ph2: vid changed, save 0x%x, curr 0x%x\n",
456 savevid, data->currvid);
457 return 1;
458 }
459
460 pr_debug("ph2 complete, currfid 0x%x, currvid 0x%x\n",
461 data->currfid, data->currvid);
462
463 return 0;
464}
465
466/* Phase 3 - core voltage transition flow ... jump to the final vid. */
467static int core_voltage_post_transition(struct powernow_k8_data *data,
468 u32 reqvid)
469{
470 u32 savefid = data->currfid;
471 u32 savereqvid = reqvid;
472
473 pr_debug("ph3 (cpu%d): starting, currfid 0x%x, currvid 0x%x\n",
474 smp_processor_id(),
475 data->currfid, data->currvid);
476
477 if (reqvid != data->currvid) {
478 if (write_new_vid(data, reqvid))
479 return 1;
480
481 if (savefid != data->currfid) {
482 printk(KERN_ERR PFX
483 "ph3: bad fid change, save 0x%x, curr 0x%x\n",
484 savefid, data->currfid);
485 return 1;
486 }
487
488 if (data->currvid != reqvid) {
489 printk(KERN_ERR PFX
490 "ph3: failed vid transition\n, "
491 "req 0x%x, curr 0x%x",
492 reqvid, data->currvid);
493 return 1;
494 }
495 }
496
497 if (query_current_values_with_pending_wait(data))
498 return 1;
499
500 if (savereqvid != data->currvid) {
501 pr_debug("ph3 failed, currvid 0x%x\n", data->currvid);
502 return 1;
503 }
504
505 if (savefid != data->currfid) {
506 pr_debug("ph3 failed, currfid changed 0x%x\n",
507 data->currfid);
508 return 1;
509 }
510
511 pr_debug("ph3 complete, currfid 0x%x, currvid 0x%x\n",
512 data->currfid, data->currvid);
513
514 return 0;
515}
516
517static void check_supported_cpu(void *_rc)
518{
519 u32 eax, ebx, ecx, edx;
520 int *rc = _rc;
521
522 *rc = -ENODEV;
523
524 if (__this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_AMD)
525 return;
526
527 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
528 if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) &&
529 ((eax & CPUID_XFAM) < CPUID_XFAM_10H))
530 return;
531
532 if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) {
533 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
534 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_MASK)) {
535 printk(KERN_INFO PFX
536 "Processor cpuid %x not supported\n", eax);
537 return;
538 }
539
540 eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
541 if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
542 printk(KERN_INFO PFX
543 "No frequency change capabilities detected\n");
544 return;
545 }
546
547 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
548 if ((edx & P_STATE_TRANSITION_CAPABLE)
549 != P_STATE_TRANSITION_CAPABLE) {
550 printk(KERN_INFO PFX
551 "Power state transitions not supported\n");
552 return;
553 }
554 } else { /* must be a HW Pstate capable processor */
555 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
556 if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
557 cpu_family = CPU_HW_PSTATE;
558 else
559 return;
560 }
561
562 *rc = 0;
563}
564
565static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst,
566 u8 maxvid)
567{
568 unsigned int j;
569 u8 lastfid = 0xff;
570
571 for (j = 0; j < data->numps; j++) {
572 if (pst[j].vid > LEAST_VID) {
573 printk(KERN_ERR FW_BUG PFX "vid %d invalid : 0x%x\n",
574 j, pst[j].vid);
575 return -EINVAL;
576 }
577 if (pst[j].vid < data->rvo) {
578 /* vid + rvo >= 0 */
579 printk(KERN_ERR FW_BUG PFX "0 vid exceeded with pstate"
580 " %d\n", j);
581 return -ENODEV;
582 }
583 if (pst[j].vid < maxvid + data->rvo) {
584 /* vid + rvo >= maxvid */
585 printk(KERN_ERR FW_BUG PFX "maxvid exceeded with pstate"
586 " %d\n", j);
587 return -ENODEV;
588 }
589 if (pst[j].fid > MAX_FID) {
590 printk(KERN_ERR FW_BUG PFX "maxfid exceeded with pstate"
591 " %d\n", j);
592 return -ENODEV;
593 }
594 if (j && (pst[j].fid < HI_FID_TABLE_BOTTOM)) {
595 /* Only first fid is allowed to be in "low" range */
596 printk(KERN_ERR FW_BUG PFX "two low fids - %d : "
597 "0x%x\n", j, pst[j].fid);
598 return -EINVAL;
599 }
600 if (pst[j].fid < lastfid)
601 lastfid = pst[j].fid;
602 }
603 if (lastfid & 1) {
604 printk(KERN_ERR FW_BUG PFX "lastfid invalid\n");
605 return -EINVAL;
606 }
607 if (lastfid > LO_FID_TABLE_TOP)
608 printk(KERN_INFO FW_BUG PFX
609 "first fid not from lo freq table\n");
610
611 return 0;
612}
613
614static void invalidate_entry(struct cpufreq_frequency_table *powernow_table,
615 unsigned int entry)
616{
617 powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID;
618}
619
620static void print_basics(struct powernow_k8_data *data)
621{
622 int j;
623 for (j = 0; j < data->numps; j++) {
624 if (data->powernow_table[j].frequency !=
625 CPUFREQ_ENTRY_INVALID) {
626 if (cpu_family == CPU_HW_PSTATE) {
627 printk(KERN_INFO PFX
628 " %d : pstate %d (%d MHz)\n", j,
629 data->powernow_table[j].index,
630 data->powernow_table[j].frequency/1000);
631 } else {
632 printk(KERN_INFO PFX
633 "fid 0x%x (%d MHz), vid 0x%x\n",
634 data->powernow_table[j].index & 0xff,
635 data->powernow_table[j].frequency/1000,
636 data->powernow_table[j].index >> 8);
637 }
638 }
639 }
640 if (data->batps)
641 printk(KERN_INFO PFX "Only %d pstates on battery\n",
642 data->batps);
643}
644
645static u32 freq_from_fid_did(u32 fid, u32 did)
646{
647 u32 mhz = 0;
648
649 if (boot_cpu_data.x86 == 0x10)
650 mhz = (100 * (fid + 0x10)) >> did;
651 else if (boot_cpu_data.x86 == 0x11)
652 mhz = (100 * (fid + 8)) >> did;
653 else
654 BUG();
655
656 return mhz * 1000;
657}
658
659static int fill_powernow_table(struct powernow_k8_data *data,
660 struct pst_s *pst, u8 maxvid)
661{
662 struct cpufreq_frequency_table *powernow_table;
663 unsigned int j;
664
665 if (data->batps) {
666 /* use ACPI support to get full speed on mains power */
667 printk(KERN_WARNING PFX
668 "Only %d pstates usable (use ACPI driver for full "
669 "range\n", data->batps);
670 data->numps = data->batps;
671 }
672
673 for (j = 1; j < data->numps; j++) {
674 if (pst[j-1].fid >= pst[j].fid) {
675 printk(KERN_ERR PFX "PST out of sequence\n");
676 return -EINVAL;
677 }
678 }
679
680 if (data->numps < 2) {
681 printk(KERN_ERR PFX "no p states to transition\n");
682 return -ENODEV;
683 }
684
685 if (check_pst_table(data, pst, maxvid))
686 return -EINVAL;
687
688 powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table)
689 * (data->numps + 1)), GFP_KERNEL);
690 if (!powernow_table) {
691 printk(KERN_ERR PFX "powernow_table memory alloc failure\n");
692 return -ENOMEM;
693 }
694
695 for (j = 0; j < data->numps; j++) {
696 int freq;
697 powernow_table[j].index = pst[j].fid; /* lower 8 bits */
698 powernow_table[j].index |= (pst[j].vid << 8); /* upper 8 bits */
699 freq = find_khz_freq_from_fid(pst[j].fid);
700 powernow_table[j].frequency = freq;
701 }
702 powernow_table[data->numps].frequency = CPUFREQ_TABLE_END;
703 powernow_table[data->numps].index = 0;
704
705 if (query_current_values_with_pending_wait(data)) {
706 kfree(powernow_table);
707 return -EIO;
708 }
709
710 pr_debug("cfid 0x%x, cvid 0x%x\n", data->currfid, data->currvid);
711 data->powernow_table = powernow_table;
712 if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu)
713 print_basics(data);
714
715 for (j = 0; j < data->numps; j++)
716 if ((pst[j].fid == data->currfid) &&
717 (pst[j].vid == data->currvid))
718 return 0;
719
720 pr_debug("currfid/vid do not match PST, ignoring\n");
721 return 0;
722}
723
724/* Find and validate the PSB/PST table in BIOS. */
725static int find_psb_table(struct powernow_k8_data *data)
726{
727 struct psb_s *psb;
728 unsigned int i;
729 u32 mvs;
730 u8 maxvid;
731 u32 cpst = 0;
732 u32 thiscpuid;
733
734 for (i = 0xc0000; i < 0xffff0; i += 0x10) {
735 /* Scan BIOS looking for the signature. */
736 /* It can not be at ffff0 - it is too big. */
737
738 psb = phys_to_virt(i);
739 if (memcmp(psb, PSB_ID_STRING, PSB_ID_STRING_LEN) != 0)
740 continue;
741
742 pr_debug("found PSB header at 0x%p\n", psb);
743
744 pr_debug("table vers: 0x%x\n", psb->tableversion);
745 if (psb->tableversion != PSB_VERSION_1_4) {
746 printk(KERN_ERR FW_BUG PFX "PSB table is not v1.4\n");
747 return -ENODEV;
748 }
749
750 pr_debug("flags: 0x%x\n", psb->flags1);
751 if (psb->flags1) {
752 printk(KERN_ERR FW_BUG PFX "unknown flags\n");
753 return -ENODEV;
754 }
755
756 data->vstable = psb->vstable;
757 pr_debug("voltage stabilization time: %d(*20us)\n",
758 data->vstable);
759
760 pr_debug("flags2: 0x%x\n", psb->flags2);
761 data->rvo = psb->flags2 & 3;
762 data->irt = ((psb->flags2) >> 2) & 3;
763 mvs = ((psb->flags2) >> 4) & 3;
764 data->vidmvs = 1 << mvs;
765 data->batps = ((psb->flags2) >> 6) & 3;
766
767 pr_debug("ramp voltage offset: %d\n", data->rvo);
768 pr_debug("isochronous relief time: %d\n", data->irt);
769 pr_debug("maximum voltage step: %d - 0x%x\n", mvs, data->vidmvs);
770
771 pr_debug("numpst: 0x%x\n", psb->num_tables);
772 cpst = psb->num_tables;
773 if ((psb->cpuid == 0x00000fc0) ||
774 (psb->cpuid == 0x00000fe0)) {
775 thiscpuid = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
776 if ((thiscpuid == 0x00000fc0) ||
777 (thiscpuid == 0x00000fe0))
778 cpst = 1;
779 }
780 if (cpst != 1) {
781 printk(KERN_ERR FW_BUG PFX "numpst must be 1\n");
782 return -ENODEV;
783 }
784
785 data->plllock = psb->plllocktime;
786 pr_debug("plllocktime: 0x%x (units 1us)\n", psb->plllocktime);
787 pr_debug("maxfid: 0x%x\n", psb->maxfid);
788 pr_debug("maxvid: 0x%x\n", psb->maxvid);
789 maxvid = psb->maxvid;
790
791 data->numps = psb->numps;
792 pr_debug("numpstates: 0x%x\n", data->numps);
793 return fill_powernow_table(data,
794 (struct pst_s *)(psb+1), maxvid);
795 }
796 /*
797 * If you see this message, complain to BIOS manufacturer. If
798 * he tells you "we do not support Linux" or some similar
799 * nonsense, remember that Windows 2000 uses the same legacy
800 * mechanism that the old Linux PSB driver uses. Tell them it
801 * is broken with Windows 2000.
802 *
803 * The reference to the AMD documentation is chapter 9 in the
804 * BIOS and Kernel Developer's Guide, which is available on
805 * www.amd.com
806 */
807 printk(KERN_ERR FW_BUG PFX "No PSB or ACPI _PSS objects\n");
808 printk(KERN_ERR PFX "Make sure that your BIOS is up to date"
809 " and Cool'N'Quiet support is enabled in BIOS setup\n");
810 return -ENODEV;
811}
812
813static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data,
814 unsigned int index)
815{
816 u64 control;
817
818 if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE))
819 return;
820
821 control = data->acpi_data.states[index].control;
822 data->irt = (control >> IRT_SHIFT) & IRT_MASK;
823 data->rvo = (control >> RVO_SHIFT) & RVO_MASK;
824 data->exttype = (control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK;
825 data->plllock = (control >> PLL_L_SHIFT) & PLL_L_MASK;
826 data->vidmvs = 1 << ((control >> MVS_SHIFT) & MVS_MASK);
827 data->vstable = (control >> VST_SHIFT) & VST_MASK;
828}
829
830static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
831{
832 struct cpufreq_frequency_table *powernow_table;
833 int ret_val = -ENODEV;
834 u64 control, status;
835
836 if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) {
837 pr_debug("register performance failed: bad ACPI data\n");
838 return -EIO;
839 }
840
841 /* verify the data contained in the ACPI structures */
842 if (data->acpi_data.state_count <= 1) {
843 pr_debug("No ACPI P-States\n");
844 goto err_out;
845 }
846
847 control = data->acpi_data.control_register.space_id;
848 status = data->acpi_data.status_register.space_id;
849
850 if ((control != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
851 (status != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
852 pr_debug("Invalid control/status registers (%llx - %llx)\n",
853 control, status);
854 goto err_out;
855 }
856
857 /* fill in data->powernow_table */
858 powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table)
859 * (data->acpi_data.state_count + 1)), GFP_KERNEL);
860 if (!powernow_table) {
861 pr_debug("powernow_table memory alloc failure\n");
862 goto err_out;
863 }
864
865 /* fill in data */
866 data->numps = data->acpi_data.state_count;
867 powernow_k8_acpi_pst_values(data, 0);
868
869 if (cpu_family == CPU_HW_PSTATE)
870 ret_val = fill_powernow_table_pstate(data, powernow_table);
871 else
872 ret_val = fill_powernow_table_fidvid(data, powernow_table);
873 if (ret_val)
874 goto err_out_mem;
875
876 powernow_table[data->acpi_data.state_count].frequency =
877 CPUFREQ_TABLE_END;
878 powernow_table[data->acpi_data.state_count].index = 0;
879 data->powernow_table = powernow_table;
880
881 if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu)
882 print_basics(data);
883
884 /* notify BIOS that we exist */
885 acpi_processor_notify_smm(THIS_MODULE);
886
887 if (!zalloc_cpumask_var(&data->acpi_data.shared_cpu_map, GFP_KERNEL)) {
888 printk(KERN_ERR PFX
889 "unable to alloc powernow_k8_data cpumask\n");
890 ret_val = -ENOMEM;
891 goto err_out_mem;
892 }
893
894 return 0;
895
896err_out_mem:
897 kfree(powernow_table);
898
899err_out:
900 acpi_processor_unregister_performance(&data->acpi_data, data->cpu);
901
902 /* data->acpi_data.state_count informs us at ->exit()
903 * whether ACPI was used */
904 data->acpi_data.state_count = 0;
905
906 return ret_val;
907}
908
909static int fill_powernow_table_pstate(struct powernow_k8_data *data,
910 struct cpufreq_frequency_table *powernow_table)
911{
912 int i;
913 u32 hi = 0, lo = 0;
914 rdmsr(MSR_PSTATE_CUR_LIMIT, lo, hi);
915 data->max_hw_pstate = (lo & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT;
916
917 for (i = 0; i < data->acpi_data.state_count; i++) {
918 u32 index;
919
920 index = data->acpi_data.states[i].control & HW_PSTATE_MASK;
921 if (index > data->max_hw_pstate) {
922 printk(KERN_ERR PFX "invalid pstate %d - "
923 "bad value %d.\n", i, index);
924 printk(KERN_ERR PFX "Please report to BIOS "
925 "manufacturer\n");
926 invalidate_entry(powernow_table, i);
927 continue;
928 }
929 rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi);
930 if (!(hi & HW_PSTATE_VALID_MASK)) {
931 pr_debug("invalid pstate %d, ignoring\n", index);
932 invalidate_entry(powernow_table, i);
933 continue;
934 }
935
936 powernow_table[i].index = index;
937
938 /* Frequency may be rounded for these */
939 if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10)
940 || boot_cpu_data.x86 == 0x11) {
941 powernow_table[i].frequency =
942 freq_from_fid_did(lo & 0x3f, (lo >> 6) & 7);
943 } else
944 powernow_table[i].frequency =
945 data->acpi_data.states[i].core_frequency * 1000;
946 }
947 return 0;
948}
949
950static int fill_powernow_table_fidvid(struct powernow_k8_data *data,
951 struct cpufreq_frequency_table *powernow_table)
952{
953 int i;
954
955 for (i = 0; i < data->acpi_data.state_count; i++) {
956 u32 fid;
957 u32 vid;
958 u32 freq, index;
959 u64 status, control;
960
961 if (data->exttype) {
962 status = data->acpi_data.states[i].status;
963 fid = status & EXT_FID_MASK;
964 vid = (status >> VID_SHIFT) & EXT_VID_MASK;
965 } else {
966 control = data->acpi_data.states[i].control;
967 fid = control & FID_MASK;
968 vid = (control >> VID_SHIFT) & VID_MASK;
969 }
970
971 pr_debug(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid);
972
973 index = fid | (vid<<8);
974 powernow_table[i].index = index;
975
976 freq = find_khz_freq_from_fid(fid);
977 powernow_table[i].frequency = freq;
978
979 /* verify frequency is OK */
980 if ((freq > (MAX_FREQ * 1000)) || (freq < (MIN_FREQ * 1000))) {
981 pr_debug("invalid freq %u kHz, ignoring\n", freq);
982 invalidate_entry(powernow_table, i);
983 continue;
984 }
985
986 /* verify voltage is OK -
987 * BIOSs are using "off" to indicate invalid */
988 if (vid == VID_OFF) {
989 pr_debug("invalid vid %u, ignoring\n", vid);
990 invalidate_entry(powernow_table, i);
991 continue;
992 }
993
994 if (freq != (data->acpi_data.states[i].core_frequency * 1000)) {
995 printk(KERN_INFO PFX "invalid freq entries "
996 "%u kHz vs. %u kHz\n", freq,
997 (unsigned int)
998 (data->acpi_data.states[i].core_frequency
999 * 1000));
1000 invalidate_entry(powernow_table, i);
1001 continue;
1002 }
1003 }
1004 return 0;
1005}
1006
1007static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data)
1008{
1009 if (data->acpi_data.state_count)
1010 acpi_processor_unregister_performance(&data->acpi_data,
1011 data->cpu);
1012 free_cpumask_var(data->acpi_data.shared_cpu_map);
1013}
1014
1015static int get_transition_latency(struct powernow_k8_data *data)
1016{
1017 int max_latency = 0;
1018 int i;
1019 for (i = 0; i < data->acpi_data.state_count; i++) {
1020 int cur_latency = data->acpi_data.states[i].transition_latency
1021 + data->acpi_data.states[i].bus_master_latency;
1022 if (cur_latency > max_latency)
1023 max_latency = cur_latency;
1024 }
1025 if (max_latency == 0) {
1026 /*
1027 * Fam 11h and later may return 0 as transition latency. This
1028 * is intended and means "very fast". While cpufreq core and
1029 * governors currently can handle that gracefully, better set it
1030 * to 1 to avoid problems in the future.
1031 */
1032 if (boot_cpu_data.x86 < 0x11)
1033 printk(KERN_ERR FW_WARN PFX "Invalid zero transition "
1034 "latency\n");
1035 max_latency = 1;
1036 }
1037 /* value in usecs, needs to be in nanoseconds */
1038 return 1000 * max_latency;
1039}
1040
1041/* Take a frequency, and issue the fid/vid transition command */
1042static int transition_frequency_fidvid(struct powernow_k8_data *data,
1043 unsigned int index)
1044{
1045 u32 fid = 0;
1046 u32 vid = 0;
1047 int res, i;
1048 struct cpufreq_freqs freqs;
1049
1050 pr_debug("cpu %d transition to index %u\n", smp_processor_id(), index);
1051
1052 /* fid/vid correctness check for k8 */
1053 /* fid are the lower 8 bits of the index we stored into
1054 * the cpufreq frequency table in find_psb_table, vid
1055 * are the upper 8 bits.
1056 */
1057 fid = data->powernow_table[index].index & 0xFF;
1058 vid = (data->powernow_table[index].index & 0xFF00) >> 8;
1059
1060 pr_debug("table matched fid 0x%x, giving vid 0x%x\n", fid, vid);
1061
1062 if (query_current_values_with_pending_wait(data))
1063 return 1;
1064
1065 if ((data->currvid == vid) && (data->currfid == fid)) {
1066 pr_debug("target matches current values (fid 0x%x, vid 0x%x)\n",
1067 fid, vid);
1068 return 0;
1069 }
1070
1071 pr_debug("cpu %d, changing to fid 0x%x, vid 0x%x\n",
1072 smp_processor_id(), fid, vid);
1073 freqs.old = find_khz_freq_from_fid(data->currfid);
1074 freqs.new = find_khz_freq_from_fid(fid);
1075
1076 for_each_cpu(i, data->available_cores) {
1077 freqs.cpu = i;
1078 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
1079 }
1080
1081 res = transition_fid_vid(data, fid, vid);
1082 freqs.new = find_khz_freq_from_fid(data->currfid);
1083
1084 for_each_cpu(i, data->available_cores) {
1085 freqs.cpu = i;
1086 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
1087 }
1088 return res;
1089}
1090
1091/* Take a frequency, and issue the hardware pstate transition command */
1092static int transition_frequency_pstate(struct powernow_k8_data *data,
1093 unsigned int index)
1094{
1095 u32 pstate = 0;
1096 int res, i;
1097 struct cpufreq_freqs freqs;
1098
1099 pr_debug("cpu %d transition to index %u\n", smp_processor_id(), index);
1100
1101 /* get MSR index for hardware pstate transition */
1102 pstate = index & HW_PSTATE_MASK;
1103 if (pstate > data->max_hw_pstate)
1104 return 0;
1105 freqs.old = find_khz_freq_from_pstate(data->powernow_table,
1106 data->currpstate);
1107 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate);
1108
1109 for_each_cpu(i, data->available_cores) {
1110 freqs.cpu = i;
1111 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
1112 }
1113
1114 res = transition_pstate(data, pstate);
1115 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate);
1116
1117 for_each_cpu(i, data->available_cores) {
1118 freqs.cpu = i;
1119 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
1120 }
1121 return res;
1122}
1123
1124/* Driver entry point to switch to the target frequency */
1125static int powernowk8_target(struct cpufreq_policy *pol,
1126 unsigned targfreq, unsigned relation)
1127{
1128 cpumask_var_t oldmask;
1129 struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu);
1130 u32 checkfid;
1131 u32 checkvid;
1132 unsigned int newstate;
1133 int ret = -EIO;
1134
1135 if (!data)
1136 return -EINVAL;
1137
1138 checkfid = data->currfid;
1139 checkvid = data->currvid;
1140
1141 /* only run on specific CPU from here on. */
1142 /* This is poor form: use a workqueue or smp_call_function_single */
1143 if (!alloc_cpumask_var(&oldmask, GFP_KERNEL))
1144 return -ENOMEM;
1145
1146 cpumask_copy(oldmask, tsk_cpus_allowed(current));
1147 set_cpus_allowed_ptr(current, cpumask_of(pol->cpu));
1148
1149 if (smp_processor_id() != pol->cpu) {
1150 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
1151 goto err_out;
1152 }
1153
1154 if (pending_bit_stuck()) {
1155 printk(KERN_ERR PFX "failing targ, change pending bit set\n");
1156 goto err_out;
1157 }
1158
1159 pr_debug("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n",
1160 pol->cpu, targfreq, pol->min, pol->max, relation);
1161
1162 if (query_current_values_with_pending_wait(data))
1163 goto err_out;
1164
1165 if (cpu_family != CPU_HW_PSTATE) {
1166 pr_debug("targ: curr fid 0x%x, vid 0x%x\n",
1167 data->currfid, data->currvid);
1168
1169 if ((checkvid != data->currvid) ||
1170 (checkfid != data->currfid)) {
1171 printk(KERN_INFO PFX
1172 "error - out of sync, fix 0x%x 0x%x, "
1173 "vid 0x%x 0x%x\n",
1174 checkfid, data->currfid,
1175 checkvid, data->currvid);
1176 }
1177 }
1178
1179 if (cpufreq_frequency_table_target(pol, data->powernow_table,
1180 targfreq, relation, &newstate))
1181 goto err_out;
1182
1183 mutex_lock(&fidvid_mutex);
1184
1185 powernow_k8_acpi_pst_values(data, newstate);
1186
1187 if (cpu_family == CPU_HW_PSTATE)
1188 ret = transition_frequency_pstate(data, newstate);
1189 else
1190 ret = transition_frequency_fidvid(data, newstate);
1191 if (ret) {
1192 printk(KERN_ERR PFX "transition frequency failed\n");
1193 ret = 1;
1194 mutex_unlock(&fidvid_mutex);
1195 goto err_out;
1196 }
1197 mutex_unlock(&fidvid_mutex);
1198
1199 if (cpu_family == CPU_HW_PSTATE)
1200 pol->cur = find_khz_freq_from_pstate(data->powernow_table,
1201 newstate);
1202 else
1203 pol->cur = find_khz_freq_from_fid(data->currfid);
1204 ret = 0;
1205
1206err_out:
1207 set_cpus_allowed_ptr(current, oldmask);
1208 free_cpumask_var(oldmask);
1209 return ret;
1210}
1211
1212/* Driver entry point to verify the policy and range of frequencies */
1213static int powernowk8_verify(struct cpufreq_policy *pol)
1214{
1215 struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu);
1216
1217 if (!data)
1218 return -EINVAL;
1219
1220 return cpufreq_frequency_table_verify(pol, data->powernow_table);
1221}
1222
1223struct init_on_cpu {
1224 struct powernow_k8_data *data;
1225 int rc;
1226};
1227
1228static void __cpuinit powernowk8_cpu_init_on_cpu(void *_init_on_cpu)
1229{
1230 struct init_on_cpu *init_on_cpu = _init_on_cpu;
1231
1232 if (pending_bit_stuck()) {
1233 printk(KERN_ERR PFX "failing init, change pending bit set\n");
1234 init_on_cpu->rc = -ENODEV;
1235 return;
1236 }
1237
1238 if (query_current_values_with_pending_wait(init_on_cpu->data)) {
1239 init_on_cpu->rc = -ENODEV;
1240 return;
1241 }
1242
1243 if (cpu_family == CPU_OPTERON)
1244 fidvid_msr_init();
1245
1246 init_on_cpu->rc = 0;
1247}
1248
1249/* per CPU init entry point to the driver */
1250static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1251{
1252 static const char ACPI_PSS_BIOS_BUG_MSG[] =
1253 KERN_ERR FW_BUG PFX "No compatible ACPI _PSS objects found.\n"
1254 FW_BUG PFX "Try again with latest BIOS.\n";
1255 struct powernow_k8_data *data;
1256 struct init_on_cpu init_on_cpu;
1257 int rc;
1258 struct cpuinfo_x86 *c = &cpu_data(pol->cpu);
1259
1260 if (!cpu_online(pol->cpu))
1261 return -ENODEV;
1262
1263 smp_call_function_single(pol->cpu, check_supported_cpu, &rc, 1);
1264 if (rc)
1265 return -ENODEV;
1266
1267 data = kzalloc(sizeof(struct powernow_k8_data), GFP_KERNEL);
1268 if (!data) {
1269 printk(KERN_ERR PFX "unable to alloc powernow_k8_data");
1270 return -ENOMEM;
1271 }
1272
1273 data->cpu = pol->cpu;
1274 data->currpstate = HW_PSTATE_INVALID;
1275
1276 if (powernow_k8_cpu_init_acpi(data)) {
1277 /*
1278 * Use the PSB BIOS structure. This is only available on
1279 * an UP version, and is deprecated by AMD.
1280 */
1281 if (num_online_cpus() != 1) {
1282 printk_once(ACPI_PSS_BIOS_BUG_MSG);
1283 goto err_out;
1284 }
1285 if (pol->cpu != 0) {
1286 printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for "
1287 "CPU other than CPU0. Complain to your BIOS "
1288 "vendor.\n");
1289 goto err_out;
1290 }
1291 rc = find_psb_table(data);
1292 if (rc)
1293 goto err_out;
1294
1295 /* Take a crude guess here.
1296 * That guess was in microseconds, so multiply with 1000 */
1297 pol->cpuinfo.transition_latency = (
1298 ((data->rvo + 8) * data->vstable * VST_UNITS_20US) +
1299 ((1 << data->irt) * 30)) * 1000;
1300 } else /* ACPI _PSS objects available */
1301 pol->cpuinfo.transition_latency = get_transition_latency(data);
1302
1303 /* only run on specific CPU from here on */
1304 init_on_cpu.data = data;
1305 smp_call_function_single(data->cpu, powernowk8_cpu_init_on_cpu,
1306 &init_on_cpu, 1);
1307 rc = init_on_cpu.rc;
1308 if (rc != 0)
1309 goto err_out_exit_acpi;
1310
1311 if (cpu_family == CPU_HW_PSTATE)
1312 cpumask_copy(pol->cpus, cpumask_of(pol->cpu));
1313 else
1314 cpumask_copy(pol->cpus, cpu_core_mask(pol->cpu));
1315 data->available_cores = pol->cpus;
1316
1317 if (cpu_family == CPU_HW_PSTATE)
1318 pol->cur = find_khz_freq_from_pstate(data->powernow_table,
1319 data->currpstate);
1320 else
1321 pol->cur = find_khz_freq_from_fid(data->currfid);
1322 pr_debug("policy current frequency %d kHz\n", pol->cur);
1323
1324 /* min/max the cpu is capable of */
1325 if (cpufreq_frequency_table_cpuinfo(pol, data->powernow_table)) {
1326 printk(KERN_ERR FW_BUG PFX "invalid powernow_table\n");
1327 powernow_k8_cpu_exit_acpi(data);
1328 kfree(data->powernow_table);
1329 kfree(data);
1330 return -EINVAL;
1331 }
1332
1333 /* Check for APERF/MPERF support in hardware */
1334 if (cpu_has(c, X86_FEATURE_APERFMPERF))
1335 cpufreq_amd64_driver.getavg = cpufreq_get_measured_perf;
1336
1337 cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu);
1338
1339 if (cpu_family == CPU_HW_PSTATE)
1340 pr_debug("cpu_init done, current pstate 0x%x\n",
1341 data->currpstate);
1342 else
1343 pr_debug("cpu_init done, current fid 0x%x, vid 0x%x\n",
1344 data->currfid, data->currvid);
1345
1346 per_cpu(powernow_data, pol->cpu) = data;
1347
1348 return 0;
1349
1350err_out_exit_acpi:
1351 powernow_k8_cpu_exit_acpi(data);
1352
1353err_out:
1354 kfree(data);
1355 return -ENODEV;
1356}
1357
1358static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol)
1359{
1360 struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu);
1361
1362 if (!data)
1363 return -EINVAL;
1364
1365 powernow_k8_cpu_exit_acpi(data);
1366
1367 cpufreq_frequency_table_put_attr(pol->cpu);
1368
1369 kfree(data->powernow_table);
1370 kfree(data);
1371 per_cpu(powernow_data, pol->cpu) = NULL;
1372
1373 return 0;
1374}
1375
1376static void query_values_on_cpu(void *_err)
1377{
1378 int *err = _err;
1379 struct powernow_k8_data *data = __this_cpu_read(powernow_data);
1380
1381 *err = query_current_values_with_pending_wait(data);
1382}
1383
1384static unsigned int powernowk8_get(unsigned int cpu)
1385{
1386 struct powernow_k8_data *data = per_cpu(powernow_data, cpu);
1387 unsigned int khz = 0;
1388 int err;
1389
1390 if (!data)
1391 return 0;
1392
1393 smp_call_function_single(cpu, query_values_on_cpu, &err, true);
1394 if (err)
1395 goto out;
1396
1397 if (cpu_family == CPU_HW_PSTATE)
1398 khz = find_khz_freq_from_pstate(data->powernow_table,
1399 data->currpstate);
1400 else
1401 khz = find_khz_freq_from_fid(data->currfid);
1402
1403
1404out:
1405 return khz;
1406}
1407
1408static void _cpb_toggle_msrs(bool t)
1409{
1410 int cpu;
1411
1412 get_online_cpus();
1413
1414 rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs);
1415
1416 for_each_cpu(cpu, cpu_online_mask) {
1417 struct msr *reg = per_cpu_ptr(msrs, cpu);
1418 if (t)
1419 reg->l &= ~BIT(25);
1420 else
1421 reg->l |= BIT(25);
1422 }
1423 wrmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs);
1424
1425 put_online_cpus();
1426}
1427
1428/*
1429 * Switch on/off core performance boosting.
1430 *
1431 * 0=disable
1432 * 1=enable.
1433 */
1434static void cpb_toggle(bool t)
1435{
1436 if (!cpb_capable)
1437 return;
1438
1439 if (t && !cpb_enabled) {
1440 cpb_enabled = true;
1441 _cpb_toggle_msrs(t);
1442 printk(KERN_INFO PFX "Core Boosting enabled.\n");
1443 } else if (!t && cpb_enabled) {
1444 cpb_enabled = false;
1445 _cpb_toggle_msrs(t);
1446 printk(KERN_INFO PFX "Core Boosting disabled.\n");
1447 }
1448}
1449
1450static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf,
1451 size_t count)
1452{
1453 int ret = -EINVAL;
1454 unsigned long val = 0;
1455
1456 ret = strict_strtoul(buf, 10, &val);
1457 if (!ret && (val == 0 || val == 1) && cpb_capable)
1458 cpb_toggle(val);
1459 else
1460 return -EINVAL;
1461
1462 return count;
1463}
1464
1465static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf)
1466{
1467 return sprintf(buf, "%u\n", cpb_enabled);
1468}
1469
1470#define define_one_rw(_name) \
1471static struct freq_attr _name = \
1472__ATTR(_name, 0644, show_##_name, store_##_name)
1473
1474define_one_rw(cpb);
1475
1476static struct freq_attr *powernow_k8_attr[] = {
1477 &cpufreq_freq_attr_scaling_available_freqs,
1478 &cpb,
1479 NULL,
1480};
1481
1482static struct cpufreq_driver cpufreq_amd64_driver = {
1483 .verify = powernowk8_verify,
1484 .target = powernowk8_target,
1485 .bios_limit = acpi_processor_get_bios_limit,
1486 .init = powernowk8_cpu_init,
1487 .exit = __devexit_p(powernowk8_cpu_exit),
1488 .get = powernowk8_get,
1489 .name = "powernow-k8",
1490 .owner = THIS_MODULE,
1491 .attr = powernow_k8_attr,
1492};
1493
1494/*
1495 * Clear the boost-disable flag on the CPU_DOWN path so that this cpu
1496 * cannot block the remaining ones from boosting. On the CPU_UP path we
1497 * simply keep the boost-disable flag in sync with the current global
1498 * state.
1499 */
1500static int cpb_notify(struct notifier_block *nb, unsigned long action,
1501 void *hcpu)
1502{
1503 unsigned cpu = (long)hcpu;
1504 u32 lo, hi;
1505
1506 switch (action) {
1507 case CPU_UP_PREPARE:
1508 case CPU_UP_PREPARE_FROZEN:
1509
1510 if (!cpb_enabled) {
1511 rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
1512 lo |= BIT(25);
1513 wrmsr_on_cpu(cpu, MSR_K7_HWCR, lo, hi);
1514 }
1515 break;
1516
1517 case CPU_DOWN_PREPARE:
1518 case CPU_DOWN_PREPARE_FROZEN:
1519 rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
1520 lo &= ~BIT(25);
1521 wrmsr_on_cpu(cpu, MSR_K7_HWCR, lo, hi);
1522 break;
1523
1524 default:
1525 break;
1526 }
1527
1528 return NOTIFY_OK;
1529}
1530
1531static struct notifier_block cpb_nb = {
1532 .notifier_call = cpb_notify,
1533};
1534
1535/* driver entry point for init */
1536static int __cpuinit powernowk8_init(void)
1537{
1538 unsigned int i, supported_cpus = 0, cpu;
1539 int rv;
1540
1541 for_each_online_cpu(i) {
1542 int rc;
1543 smp_call_function_single(i, check_supported_cpu, &rc, 1);
1544 if (rc == 0)
1545 supported_cpus++;
1546 }
1547
1548 if (supported_cpus != num_online_cpus())
1549 return -ENODEV;
1550
1551 printk(KERN_INFO PFX "Found %d %s (%d cpu cores) (" VERSION ")\n",
1552 num_online_nodes(), boot_cpu_data.x86_model_id, supported_cpus);
1553
1554 if (boot_cpu_has(X86_FEATURE_CPB)) {
1555
1556 cpb_capable = true;
1557
1558 msrs = msrs_alloc();
1559 if (!msrs) {
1560 printk(KERN_ERR "%s: Error allocating msrs!\n", __func__);
1561 return -ENOMEM;
1562 }
1563
1564 register_cpu_notifier(&cpb_nb);
1565
1566 rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs);
1567
1568 for_each_cpu(cpu, cpu_online_mask) {
1569 struct msr *reg = per_cpu_ptr(msrs, cpu);
1570 cpb_enabled |= !(!!(reg->l & BIT(25)));
1571 }
1572
1573 printk(KERN_INFO PFX "Core Performance Boosting: %s.\n",
1574 (cpb_enabled ? "on" : "off"));
1575 }
1576
1577 rv = cpufreq_register_driver(&cpufreq_amd64_driver);
1578 if (rv < 0 && boot_cpu_has(X86_FEATURE_CPB)) {
1579 unregister_cpu_notifier(&cpb_nb);
1580 msrs_free(msrs);
1581 msrs = NULL;
1582 }
1583 return rv;
1584}
1585
1586/* driver entry point for term */
1587static void __exit powernowk8_exit(void)
1588{
1589 pr_debug("exit\n");
1590
1591 if (boot_cpu_has(X86_FEATURE_CPB)) {
1592 msrs_free(msrs);
1593 msrs = NULL;
1594
1595 unregister_cpu_notifier(&cpb_nb);
1596 }
1597
1598 cpufreq_unregister_driver(&cpufreq_amd64_driver);
1599}
1600
1601MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and "
1602 "Mark Langsdorf <mark.langsdorf@amd.com>");
1603MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver.");
1604MODULE_LICENSE("GPL");
1605
1606late_initcall(powernowk8_init);
1607module_exit(powernowk8_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
deleted file mode 100644
index 3744d26cdc2b..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ /dev/null
@@ -1,222 +0,0 @@
1/*
2 * (c) 2003-2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 */
7
8enum pstate {
9 HW_PSTATE_INVALID = 0xff,
10 HW_PSTATE_0 = 0,
11 HW_PSTATE_1 = 1,
12 HW_PSTATE_2 = 2,
13 HW_PSTATE_3 = 3,
14 HW_PSTATE_4 = 4,
15 HW_PSTATE_5 = 5,
16 HW_PSTATE_6 = 6,
17 HW_PSTATE_7 = 7,
18};
19
20struct powernow_k8_data {
21 unsigned int cpu;
22
23 u32 numps; /* number of p-states */
24 u32 batps; /* number of p-states supported on battery */
25 u32 max_hw_pstate; /* maximum legal hardware pstate */
26
27 /* these values are constant when the PSB is used to determine
28 * vid/fid pairings, but are modified during the ->target() call
29 * when ACPI is used */
30 u32 rvo; /* ramp voltage offset */
31 u32 irt; /* isochronous relief time */
32 u32 vidmvs; /* usable value calculated from mvs */
33 u32 vstable; /* voltage stabilization time, units 20 us */
34 u32 plllock; /* pll lock time, units 1 us */
35 u32 exttype; /* extended interface = 1 */
36
37 /* keep track of the current fid / vid or pstate */
38 u32 currvid;
39 u32 currfid;
40 enum pstate currpstate;
41
42 /* the powernow_table includes all frequency and vid/fid pairings:
43 * fid are the lower 8 bits of the index, vid are the upper 8 bits.
44 * frequency is in kHz */
45 struct cpufreq_frequency_table *powernow_table;
46
47 /* the acpi table needs to be kept. it's only available if ACPI was
48 * used to determine valid frequency/vid/fid states */
49 struct acpi_processor_performance acpi_data;
50
51 /* we need to keep track of associated cores, but let cpufreq
52 * handle hotplug events - so just point at cpufreq pol->cpus
53 * structure */
54 struct cpumask *available_cores;
55};
56
57/* processor's cpuid instruction support */
58#define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
59#define CPUID_XFAM 0x0ff00000 /* extended family */
60#define CPUID_XFAM_K8 0
61#define CPUID_XMOD 0x000f0000 /* extended model */
62#define CPUID_XMOD_REV_MASK 0x000c0000
63#define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
64#define CPUID_USE_XFAM_XMOD 0x00000f00
65#define CPUID_GET_MAX_CAPABILITIES 0x80000000
66#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
67#define P_STATE_TRANSITION_CAPABLE 6
68
69/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
70/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
71/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
72/* the register number is placed in ecx, and the data is returned in edx:eax. */
73
74#define MSR_FIDVID_CTL 0xc0010041
75#define MSR_FIDVID_STATUS 0xc0010042
76
77/* Field definitions within the FID VID Low Control MSR : */
78#define MSR_C_LO_INIT_FID_VID 0x00010000
79#define MSR_C_LO_NEW_VID 0x00003f00
80#define MSR_C_LO_NEW_FID 0x0000003f
81#define MSR_C_LO_VID_SHIFT 8
82
83/* Field definitions within the FID VID High Control MSR : */
84#define MSR_C_HI_STP_GNT_TO 0x000fffff
85
86/* Field definitions within the FID VID Low Status MSR : */
87#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
88#define MSR_S_LO_MAX_RAMP_VID 0x3f000000
89#define MSR_S_LO_MAX_FID 0x003f0000
90#define MSR_S_LO_START_FID 0x00003f00
91#define MSR_S_LO_CURRENT_FID 0x0000003f
92
93/* Field definitions within the FID VID High Status MSR : */
94#define MSR_S_HI_MIN_WORKING_VID 0x3f000000
95#define MSR_S_HI_MAX_WORKING_VID 0x003f0000
96#define MSR_S_HI_START_VID 0x00003f00
97#define MSR_S_HI_CURRENT_VID 0x0000003f
98#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
99
100
101/* Hardware Pstate _PSS and MSR definitions */
102#define USE_HW_PSTATE 0x00000080
103#define HW_PSTATE_MASK 0x00000007
104#define HW_PSTATE_VALID_MASK 0x80000000
105#define HW_PSTATE_MAX_MASK 0x000000f0
106#define HW_PSTATE_MAX_SHIFT 4
107#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */
108#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */
109#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */
110#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */
111
112/* define the two driver architectures */
113#define CPU_OPTERON 0
114#define CPU_HW_PSTATE 1
115
116
117/*
118 * There are restrictions frequencies have to follow:
119 * - only 1 entry in the low fid table ( <=1.4GHz )
120 * - lowest entry in the high fid table must be >= 2 * the entry in the
121 * low fid table
122 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
123 * in the low fid table
124 * - the parts can only step at <= 200 MHz intervals, odd fid values are
125 * supported in revision G and later revisions.
126 * - lowest frequency must be >= interprocessor hypertransport link speed
127 * (only applies to MP systems obviously)
128 */
129
130/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
131#define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */
132#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
133
134#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
135#define HI_VCOFREQ_TABLE_BOTTOM 1600
136
137#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
138
139#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
140#define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
141
142#define MIN_FREQ 800 /* Min and max freqs, per spec */
143#define MAX_FREQ 5000
144
145#define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
146#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
147
148#define VID_OFF 0x3f
149
150#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
151
152#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
153
154#define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
155#define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */
156
157/*
158 * Most values of interest are encoded in a single field of the _PSS
159 * entries: the "control" value.
160 */
161
162#define IRT_SHIFT 30
163#define RVO_SHIFT 28
164#define EXT_TYPE_SHIFT 27
165#define PLL_L_SHIFT 20
166#define MVS_SHIFT 18
167#define VST_SHIFT 11
168#define VID_SHIFT 6
169#define IRT_MASK 3
170#define RVO_MASK 3
171#define EXT_TYPE_MASK 1
172#define PLL_L_MASK 0x7f
173#define MVS_MASK 3
174#define VST_MASK 0x7f
175#define VID_MASK 0x1f
176#define FID_MASK 0x1f
177#define EXT_VID_MASK 0x3f
178#define EXT_FID_MASK 0x3f
179
180
181/*
182 * Version 1.4 of the PSB table. This table is constructed by BIOS and is
183 * to tell the OS's power management driver which VIDs and FIDs are
184 * supported by this particular processor.
185 * If the data in the PSB / PST is wrong, then this driver will program the
186 * wrong values into hardware, which is very likely to lead to a crash.
187 */
188
189#define PSB_ID_STRING "AMDK7PNOW!"
190#define PSB_ID_STRING_LEN 10
191
192#define PSB_VERSION_1_4 0x14
193
194struct psb_s {
195 u8 signature[10];
196 u8 tableversion;
197 u8 flags1;
198 u16 vstable;
199 u8 flags2;
200 u8 num_tables;
201 u32 cpuid;
202 u8 plllocktime;
203 u8 maxfid;
204 u8 maxvid;
205 u8 numps;
206};
207
208/* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
209struct pst_s {
210 u8 fid;
211 u8 vid;
212};
213
214static int core_voltage_pre_transition(struct powernow_k8_data *data,
215 u32 reqvid, u32 regfid);
216static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
217static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
218
219static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
220
221static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
222static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
diff --git a/arch/x86/kernel/cpu/cpufreq/sc520_freq.c b/arch/x86/kernel/cpu/cpufreq/sc520_freq.c
deleted file mode 100644
index 1e205e6b1727..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/sc520_freq.c
+++ /dev/null
@@ -1,192 +0,0 @@
1/*
2 * sc520_freq.c: cpufreq driver for the AMD Elan sc520
3 *
4 * Copyright (C) 2005 Sean Young <sean@mess.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Based on elanfreq.c
12 *
13 * 2005-03-30: - initial revision
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19
20#include <linux/delay.h>
21#include <linux/cpufreq.h>
22#include <linux/timex.h>
23#include <linux/io.h>
24
25#include <asm/msr.h>
26
27#define MMCR_BASE 0xfffef000 /* The default base address */
28#define OFFS_CPUCTL 0x2 /* CPU Control Register */
29
30static __u8 __iomem *cpuctl;
31
32#define PFX "sc520_freq: "
33
34static struct cpufreq_frequency_table sc520_freq_table[] = {
35 {0x01, 100000},
36 {0x02, 133000},
37 {0, CPUFREQ_TABLE_END},
38};
39
40static unsigned int sc520_freq_get_cpu_frequency(unsigned int cpu)
41{
42 u8 clockspeed_reg = *cpuctl;
43
44 switch (clockspeed_reg & 0x03) {
45 default:
46 printk(KERN_ERR PFX "error: cpuctl register has unexpected "
47 "value %02x\n", clockspeed_reg);
48 case 0x01:
49 return 100000;
50 case 0x02:
51 return 133000;
52 }
53}
54
55static void sc520_freq_set_cpu_state(unsigned int state)
56{
57
58 struct cpufreq_freqs freqs;
59 u8 clockspeed_reg;
60
61 freqs.old = sc520_freq_get_cpu_frequency(0);
62 freqs.new = sc520_freq_table[state].frequency;
63 freqs.cpu = 0; /* AMD Elan is UP */
64
65 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
66
67 pr_debug("attempting to set frequency to %i kHz\n",
68 sc520_freq_table[state].frequency);
69
70 local_irq_disable();
71
72 clockspeed_reg = *cpuctl & ~0x03;
73 *cpuctl = clockspeed_reg | sc520_freq_table[state].index;
74
75 local_irq_enable();
76
77 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
78};
79
80static int sc520_freq_verify(struct cpufreq_policy *policy)
81{
82 return cpufreq_frequency_table_verify(policy, &sc520_freq_table[0]);
83}
84
85static int sc520_freq_target(struct cpufreq_policy *policy,
86 unsigned int target_freq,
87 unsigned int relation)
88{
89 unsigned int newstate = 0;
90
91 if (cpufreq_frequency_table_target(policy, sc520_freq_table,
92 target_freq, relation, &newstate))
93 return -EINVAL;
94
95 sc520_freq_set_cpu_state(newstate);
96
97 return 0;
98}
99
100
101/*
102 * Module init and exit code
103 */
104
105static int sc520_freq_cpu_init(struct cpufreq_policy *policy)
106{
107 struct cpuinfo_x86 *c = &cpu_data(0);
108 int result;
109
110 /* capability check */
111 if (c->x86_vendor != X86_VENDOR_AMD ||
112 c->x86 != 4 || c->x86_model != 9)
113 return -ENODEV;
114
115 /* cpuinfo and default policy values */
116 policy->cpuinfo.transition_latency = 1000000; /* 1ms */
117 policy->cur = sc520_freq_get_cpu_frequency(0);
118
119 result = cpufreq_frequency_table_cpuinfo(policy, sc520_freq_table);
120 if (result)
121 return result;
122
123 cpufreq_frequency_table_get_attr(sc520_freq_table, policy->cpu);
124
125 return 0;
126}
127
128
129static int sc520_freq_cpu_exit(struct cpufreq_policy *policy)
130{
131 cpufreq_frequency_table_put_attr(policy->cpu);
132 return 0;
133}
134
135
136static struct freq_attr *sc520_freq_attr[] = {
137 &cpufreq_freq_attr_scaling_available_freqs,
138 NULL,
139};
140
141
142static struct cpufreq_driver sc520_freq_driver = {
143 .get = sc520_freq_get_cpu_frequency,
144 .verify = sc520_freq_verify,
145 .target = sc520_freq_target,
146 .init = sc520_freq_cpu_init,
147 .exit = sc520_freq_cpu_exit,
148 .name = "sc520_freq",
149 .owner = THIS_MODULE,
150 .attr = sc520_freq_attr,
151};
152
153
154static int __init sc520_freq_init(void)
155{
156 struct cpuinfo_x86 *c = &cpu_data(0);
157 int err;
158
159 /* Test if we have the right hardware */
160 if (c->x86_vendor != X86_VENDOR_AMD ||
161 c->x86 != 4 || c->x86_model != 9) {
162 pr_debug("no Elan SC520 processor found!\n");
163 return -ENODEV;
164 }
165 cpuctl = ioremap((unsigned long)(MMCR_BASE + OFFS_CPUCTL), 1);
166 if (!cpuctl) {
167 printk(KERN_ERR "sc520_freq: error: failed to remap memory\n");
168 return -ENOMEM;
169 }
170
171 err = cpufreq_register_driver(&sc520_freq_driver);
172 if (err)
173 iounmap(cpuctl);
174
175 return err;
176}
177
178
179static void __exit sc520_freq_exit(void)
180{
181 cpufreq_unregister_driver(&sc520_freq_driver);
182 iounmap(cpuctl);
183}
184
185
186MODULE_LICENSE("GPL");
187MODULE_AUTHOR("Sean Young <sean@mess.org>");
188MODULE_DESCRIPTION("cpufreq driver for AMD's Elan sc520 CPU");
189
190module_init(sc520_freq_init);
191module_exit(sc520_freq_exit);
192
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
deleted file mode 100644
index 6ea3455def21..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ /dev/null
@@ -1,633 +0,0 @@
1/*
2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
4 *
5 * Since the original Pentium M, most new Intel CPUs support Enhanced
6 * SpeedStep.
7 *
8 * Despite the "SpeedStep" in the name, this is almost entirely unlike
9 * traditional SpeedStep.
10 *
11 * Modelled on speedstep.c
12 *
13 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/cpufreq.h>
20#include <linux/sched.h> /* current */
21#include <linux/delay.h>
22#include <linux/compiler.h>
23#include <linux/gfp.h>
24
25#include <asm/msr.h>
26#include <asm/processor.h>
27#include <asm/cpufeature.h>
28
29#define PFX "speedstep-centrino: "
30#define MAINTAINER "cpufreq@vger.kernel.org"
31
32#define INTEL_MSR_RANGE (0xffff)
33
34struct cpu_id
35{
36 __u8 x86; /* CPU family */
37 __u8 x86_model; /* model */
38 __u8 x86_mask; /* stepping */
39};
40
41enum {
42 CPU_BANIAS,
43 CPU_DOTHAN_A1,
44 CPU_DOTHAN_A2,
45 CPU_DOTHAN_B0,
46 CPU_MP4HT_D0,
47 CPU_MP4HT_E0,
48};
49
50static const struct cpu_id cpu_ids[] = {
51 [CPU_BANIAS] = { 6, 9, 5 },
52 [CPU_DOTHAN_A1] = { 6, 13, 1 },
53 [CPU_DOTHAN_A2] = { 6, 13, 2 },
54 [CPU_DOTHAN_B0] = { 6, 13, 6 },
55 [CPU_MP4HT_D0] = {15, 3, 4 },
56 [CPU_MP4HT_E0] = {15, 4, 1 },
57};
58#define N_IDS ARRAY_SIZE(cpu_ids)
59
60struct cpu_model
61{
62 const struct cpu_id *cpu_id;
63 const char *model_name;
64 unsigned max_freq; /* max clock in kHz */
65
66 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
67};
68static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
69 const struct cpu_id *x);
70
71/* Operating points for current CPU */
72static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
73static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
74
75static struct cpufreq_driver centrino_driver;
76
77#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
78
79/* Computes the correct form for IA32_PERF_CTL MSR for a particular
80 frequency/voltage operating point; frequency in MHz, volts in mV.
81 This is stored as "index" in the structure. */
82#define OP(mhz, mv) \
83 { \
84 .frequency = (mhz) * 1000, \
85 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
86 }
87
88/*
89 * These voltage tables were derived from the Intel Pentium M
90 * datasheet, document 25261202.pdf, Table 5. I have verified they
91 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
92 * M.
93 */
94
95/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
96static struct cpufreq_frequency_table banias_900[] =
97{
98 OP(600, 844),
99 OP(800, 988),
100 OP(900, 1004),
101 { .frequency = CPUFREQ_TABLE_END }
102};
103
104/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
105static struct cpufreq_frequency_table banias_1000[] =
106{
107 OP(600, 844),
108 OP(800, 972),
109 OP(900, 988),
110 OP(1000, 1004),
111 { .frequency = CPUFREQ_TABLE_END }
112};
113
114/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
115static struct cpufreq_frequency_table banias_1100[] =
116{
117 OP( 600, 956),
118 OP( 800, 1020),
119 OP( 900, 1100),
120 OP(1000, 1164),
121 OP(1100, 1180),
122 { .frequency = CPUFREQ_TABLE_END }
123};
124
125
126/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
127static struct cpufreq_frequency_table banias_1200[] =
128{
129 OP( 600, 956),
130 OP( 800, 1004),
131 OP( 900, 1020),
132 OP(1000, 1100),
133 OP(1100, 1164),
134 OP(1200, 1180),
135 { .frequency = CPUFREQ_TABLE_END }
136};
137
138/* Intel Pentium M processor 1.30GHz (Banias) */
139static struct cpufreq_frequency_table banias_1300[] =
140{
141 OP( 600, 956),
142 OP( 800, 1260),
143 OP(1000, 1292),
144 OP(1200, 1356),
145 OP(1300, 1388),
146 { .frequency = CPUFREQ_TABLE_END }
147};
148
149/* Intel Pentium M processor 1.40GHz (Banias) */
150static struct cpufreq_frequency_table banias_1400[] =
151{
152 OP( 600, 956),
153 OP( 800, 1180),
154 OP(1000, 1308),
155 OP(1200, 1436),
156 OP(1400, 1484),
157 { .frequency = CPUFREQ_TABLE_END }
158};
159
160/* Intel Pentium M processor 1.50GHz (Banias) */
161static struct cpufreq_frequency_table banias_1500[] =
162{
163 OP( 600, 956),
164 OP( 800, 1116),
165 OP(1000, 1228),
166 OP(1200, 1356),
167 OP(1400, 1452),
168 OP(1500, 1484),
169 { .frequency = CPUFREQ_TABLE_END }
170};
171
172/* Intel Pentium M processor 1.60GHz (Banias) */
173static struct cpufreq_frequency_table banias_1600[] =
174{
175 OP( 600, 956),
176 OP( 800, 1036),
177 OP(1000, 1164),
178 OP(1200, 1276),
179 OP(1400, 1420),
180 OP(1600, 1484),
181 { .frequency = CPUFREQ_TABLE_END }
182};
183
184/* Intel Pentium M processor 1.70GHz (Banias) */
185static struct cpufreq_frequency_table banias_1700[] =
186{
187 OP( 600, 956),
188 OP( 800, 1004),
189 OP(1000, 1116),
190 OP(1200, 1228),
191 OP(1400, 1308),
192 OP(1700, 1484),
193 { .frequency = CPUFREQ_TABLE_END }
194};
195#undef OP
196
197#define _BANIAS(cpuid, max, name) \
198{ .cpu_id = cpuid, \
199 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
200 .max_freq = (max)*1000, \
201 .op_points = banias_##max, \
202}
203#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
204
205/* CPU models, their operating frequency range, and freq/voltage
206 operating points */
207static struct cpu_model models[] =
208{
209 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
210 BANIAS(1000),
211 BANIAS(1100),
212 BANIAS(1200),
213 BANIAS(1300),
214 BANIAS(1400),
215 BANIAS(1500),
216 BANIAS(1600),
217 BANIAS(1700),
218
219 /* NULL model_name is a wildcard */
220 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
221 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
222 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
223 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
224 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
225
226 { NULL, }
227};
228#undef _BANIAS
229#undef BANIAS
230
231static int centrino_cpu_init_table(struct cpufreq_policy *policy)
232{
233 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
234 struct cpu_model *model;
235
236 for(model = models; model->cpu_id != NULL; model++)
237 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
238 (model->model_name == NULL ||
239 strcmp(cpu->x86_model_id, model->model_name) == 0))
240 break;
241
242 if (model->cpu_id == NULL) {
243 /* No match at all */
244 pr_debug("no support for CPU model \"%s\": "
245 "send /proc/cpuinfo to " MAINTAINER "\n",
246 cpu->x86_model_id);
247 return -ENOENT;
248 }
249
250 if (model->op_points == NULL) {
251 /* Matched a non-match */
252 pr_debug("no table support for CPU model \"%s\"\n",
253 cpu->x86_model_id);
254 pr_debug("try using the acpi-cpufreq driver\n");
255 return -ENOENT;
256 }
257
258 per_cpu(centrino_model, policy->cpu) = model;
259
260 pr_debug("found \"%s\": max frequency: %dkHz\n",
261 model->model_name, model->max_freq);
262
263 return 0;
264}
265
266#else
267static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
268{
269 return -ENODEV;
270}
271#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
272
273static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
274 const struct cpu_id *x)
275{
276 if ((c->x86 == x->x86) &&
277 (c->x86_model == x->x86_model) &&
278 (c->x86_mask == x->x86_mask))
279 return 1;
280 return 0;
281}
282
283/* To be called only after centrino_model is initialized */
284static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
285{
286 int i;
287
288 /*
289 * Extract clock in kHz from PERF_CTL value
290 * for centrino, as some DSDTs are buggy.
291 * Ideally, this can be done using the acpi_data structure.
292 */
293 if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
294 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
295 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
296 msr = (msr >> 8) & 0xff;
297 return msr * 100000;
298 }
299
300 if ((!per_cpu(centrino_model, cpu)) ||
301 (!per_cpu(centrino_model, cpu)->op_points))
302 return 0;
303
304 msr &= 0xffff;
305 for (i = 0;
306 per_cpu(centrino_model, cpu)->op_points[i].frequency
307 != CPUFREQ_TABLE_END;
308 i++) {
309 if (msr == per_cpu(centrino_model, cpu)->op_points[i].index)
310 return per_cpu(centrino_model, cpu)->
311 op_points[i].frequency;
312 }
313 if (failsafe)
314 return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
315 else
316 return 0;
317}
318
319/* Return the current CPU frequency in kHz */
320static unsigned int get_cur_freq(unsigned int cpu)
321{
322 unsigned l, h;
323 unsigned clock_freq;
324
325 rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
326 clock_freq = extract_clock(l, cpu, 0);
327
328 if (unlikely(clock_freq == 0)) {
329 /*
330 * On some CPUs, we can see transient MSR values (which are
331 * not present in _PSS), while CPU is doing some automatic
332 * P-state transition (like TM2). Get the last freq set
333 * in PERF_CTL.
334 */
335 rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
336 clock_freq = extract_clock(l, cpu, 1);
337 }
338 return clock_freq;
339}
340
341
342static int centrino_cpu_init(struct cpufreq_policy *policy)
343{
344 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
345 unsigned freq;
346 unsigned l, h;
347 int ret;
348 int i;
349
350 /* Only Intel makes Enhanced Speedstep-capable CPUs */
351 if (cpu->x86_vendor != X86_VENDOR_INTEL ||
352 !cpu_has(cpu, X86_FEATURE_EST))
353 return -ENODEV;
354
355 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
356 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
357
358 if (policy->cpu != 0)
359 return -ENODEV;
360
361 for (i = 0; i < N_IDS; i++)
362 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
363 break;
364
365 if (i != N_IDS)
366 per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
367
368 if (!per_cpu(centrino_cpu, policy->cpu)) {
369 pr_debug("found unsupported CPU with "
370 "Enhanced SpeedStep: send /proc/cpuinfo to "
371 MAINTAINER "\n");
372 return -ENODEV;
373 }
374
375 if (centrino_cpu_init_table(policy)) {
376 return -ENODEV;
377 }
378
379 /* Check to see if Enhanced SpeedStep is enabled, and try to
380 enable it if not. */
381 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
382
383 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
384 l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
385 pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
386 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
387
388 /* check to see if it stuck */
389 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
390 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
391 printk(KERN_INFO PFX
392 "couldn't enable Enhanced SpeedStep\n");
393 return -ENODEV;
394 }
395 }
396
397 freq = get_cur_freq(policy->cpu);
398 policy->cpuinfo.transition_latency = 10000;
399 /* 10uS transition latency */
400 policy->cur = freq;
401
402 pr_debug("centrino_cpu_init: cur=%dkHz\n", policy->cur);
403
404 ret = cpufreq_frequency_table_cpuinfo(policy,
405 per_cpu(centrino_model, policy->cpu)->op_points);
406 if (ret)
407 return (ret);
408
409 cpufreq_frequency_table_get_attr(
410 per_cpu(centrino_model, policy->cpu)->op_points, policy->cpu);
411
412 return 0;
413}
414
415static int centrino_cpu_exit(struct cpufreq_policy *policy)
416{
417 unsigned int cpu = policy->cpu;
418
419 if (!per_cpu(centrino_model, cpu))
420 return -ENODEV;
421
422 cpufreq_frequency_table_put_attr(cpu);
423
424 per_cpu(centrino_model, cpu) = NULL;
425
426 return 0;
427}
428
429/**
430 * centrino_verify - verifies a new CPUFreq policy
431 * @policy: new policy
432 *
433 * Limit must be within this model's frequency range at least one
434 * border included.
435 */
436static int centrino_verify (struct cpufreq_policy *policy)
437{
438 return cpufreq_frequency_table_verify(policy,
439 per_cpu(centrino_model, policy->cpu)->op_points);
440}
441
442/**
443 * centrino_setpolicy - set a new CPUFreq policy
444 * @policy: new policy
445 * @target_freq: the target frequency
446 * @relation: how that frequency relates to achieved frequency
447 * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
448 *
449 * Sets a new CPUFreq policy.
450 */
451static int centrino_target (struct cpufreq_policy *policy,
452 unsigned int target_freq,
453 unsigned int relation)
454{
455 unsigned int newstate = 0;
456 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
457 struct cpufreq_freqs freqs;
458 int retval = 0;
459 unsigned int j, k, first_cpu, tmp;
460 cpumask_var_t covered_cpus;
461
462 if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
463 return -ENOMEM;
464
465 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
466 retval = -ENODEV;
467 goto out;
468 }
469
470 if (unlikely(cpufreq_frequency_table_target(policy,
471 per_cpu(centrino_model, cpu)->op_points,
472 target_freq,
473 relation,
474 &newstate))) {
475 retval = -EINVAL;
476 goto out;
477 }
478
479 first_cpu = 1;
480 for_each_cpu(j, policy->cpus) {
481 int good_cpu;
482
483 /* cpufreq holds the hotplug lock, so we are safe here */
484 if (!cpu_online(j))
485 continue;
486
487 /*
488 * Support for SMP systems.
489 * Make sure we are running on CPU that wants to change freq
490 */
491 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
492 good_cpu = cpumask_any_and(policy->cpus,
493 cpu_online_mask);
494 else
495 good_cpu = j;
496
497 if (good_cpu >= nr_cpu_ids) {
498 pr_debug("couldn't limit to CPUs in this domain\n");
499 retval = -EAGAIN;
500 if (first_cpu) {
501 /* We haven't started the transition yet. */
502 goto out;
503 }
504 break;
505 }
506
507 msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;
508
509 if (first_cpu) {
510 rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
511 if (msr == (oldmsr & 0xffff)) {
512 pr_debug("no change needed - msr was and needs "
513 "to be %x\n", oldmsr);
514 retval = 0;
515 goto out;
516 }
517
518 freqs.old = extract_clock(oldmsr, cpu, 0);
519 freqs.new = extract_clock(msr, cpu, 0);
520
521 pr_debug("target=%dkHz old=%d new=%d msr=%04x\n",
522 target_freq, freqs.old, freqs.new, msr);
523
524 for_each_cpu(k, policy->cpus) {
525 if (!cpu_online(k))
526 continue;
527 freqs.cpu = k;
528 cpufreq_notify_transition(&freqs,
529 CPUFREQ_PRECHANGE);
530 }
531
532 first_cpu = 0;
533 /* all but 16 LSB are reserved, treat them with care */
534 oldmsr &= ~0xffff;
535 msr &= 0xffff;
536 oldmsr |= msr;
537 }
538
539 wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
540 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
541 break;
542
543 cpumask_set_cpu(j, covered_cpus);
544 }
545
546 for_each_cpu(k, policy->cpus) {
547 if (!cpu_online(k))
548 continue;
549 freqs.cpu = k;
550 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
551 }
552
553 if (unlikely(retval)) {
554 /*
555 * We have failed halfway through the frequency change.
556 * We have sent callbacks to policy->cpus and
557 * MSRs have already been written on coverd_cpus.
558 * Best effort undo..
559 */
560
561 for_each_cpu(j, covered_cpus)
562 wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
563
564 tmp = freqs.new;
565 freqs.new = freqs.old;
566 freqs.old = tmp;
567 for_each_cpu(j, policy->cpus) {
568 if (!cpu_online(j))
569 continue;
570 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
571 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
572 }
573 }
574 retval = 0;
575
576out:
577 free_cpumask_var(covered_cpus);
578 return retval;
579}
580
581static struct freq_attr* centrino_attr[] = {
582 &cpufreq_freq_attr_scaling_available_freqs,
583 NULL,
584};
585
586static struct cpufreq_driver centrino_driver = {
587 .name = "centrino", /* should be speedstep-centrino,
588 but there's a 16 char limit */
589 .init = centrino_cpu_init,
590 .exit = centrino_cpu_exit,
591 .verify = centrino_verify,
592 .target = centrino_target,
593 .get = get_cur_freq,
594 .attr = centrino_attr,
595 .owner = THIS_MODULE,
596};
597
598
599/**
600 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
601 *
602 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
603 * unsupported devices, -ENOENT if there's no voltage table for this
604 * particular CPU model, -EINVAL on problems during initiatization,
605 * and zero on success.
606 *
607 * This is quite picky. Not only does the CPU have to advertise the
608 * "est" flag in the cpuid capability flags, we look for a specific
609 * CPU model and stepping, and we need to have the exact model name in
610 * our voltage tables. That is, be paranoid about not releasing
611 * someone's valuable magic smoke.
612 */
613static int __init centrino_init(void)
614{
615 struct cpuinfo_x86 *cpu = &cpu_data(0);
616
617 if (!cpu_has(cpu, X86_FEATURE_EST))
618 return -ENODEV;
619
620 return cpufreq_register_driver(&centrino_driver);
621}
622
623static void __exit centrino_exit(void)
624{
625 cpufreq_unregister_driver(&centrino_driver);
626}
627
628MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
629MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
630MODULE_LICENSE ("GPL");
631
632late_initcall(centrino_init);
633module_exit(centrino_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
deleted file mode 100644
index a748ce782fee..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
+++ /dev/null
@@ -1,448 +0,0 @@
1/*
2 * (C) 2001 Dave Jones, Arjan van de ven.
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 *
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon reverse engineered information, and on Intel documentation
7 * for chipsets ICH2-M and ICH3-M.
8 *
9 * Many thanks to Ducrot Bruno for finding and fixing the last
10 * "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
11 * for extensive testing.
12 *
13 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
14 */
15
16
17/*********************************************************************
18 * SPEEDSTEP - DEFINITIONS *
19 *********************************************************************/
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/cpufreq.h>
25#include <linux/pci.h>
26#include <linux/sched.h>
27
28#include "speedstep-lib.h"
29
30
31/* speedstep_chipset:
32 * It is necessary to know which chipset is used. As accesses to
33 * this device occur at various places in this module, we need a
34 * static struct pci_dev * pointing to that device.
35 */
36static struct pci_dev *speedstep_chipset_dev;
37
38
39/* speedstep_processor
40 */
41static enum speedstep_processor speedstep_processor;
42
43static u32 pmbase;
44
45/*
46 * There are only two frequency states for each processor. Values
47 * are in kHz for the time being.
48 */
49static struct cpufreq_frequency_table speedstep_freqs[] = {
50 {SPEEDSTEP_HIGH, 0},
51 {SPEEDSTEP_LOW, 0},
52 {0, CPUFREQ_TABLE_END},
53};
54
55
56/**
57 * speedstep_find_register - read the PMBASE address
58 *
59 * Returns: -ENODEV if no register could be found
60 */
61static int speedstep_find_register(void)
62{
63 if (!speedstep_chipset_dev)
64 return -ENODEV;
65
66 /* get PMBASE */
67 pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
68 if (!(pmbase & 0x01)) {
69 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
70 return -ENODEV;
71 }
72
73 pmbase &= 0xFFFFFFFE;
74 if (!pmbase) {
75 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
76 return -ENODEV;
77 }
78
79 pr_debug("pmbase is 0x%x\n", pmbase);
80 return 0;
81}
82
83/**
84 * speedstep_set_state - set the SpeedStep state
85 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
86 *
87 * Tries to change the SpeedStep state. Can be called from
88 * smp_call_function_single.
89 */
90static void speedstep_set_state(unsigned int state)
91{
92 u8 pm2_blk;
93 u8 value;
94 unsigned long flags;
95
96 if (state > 0x1)
97 return;
98
99 /* Disable IRQs */
100 local_irq_save(flags);
101
102 /* read state */
103 value = inb(pmbase + 0x50);
104
105 pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
106
107 /* write new state */
108 value &= 0xFE;
109 value |= state;
110
111 pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
112
113 /* Disable bus master arbitration */
114 pm2_blk = inb(pmbase + 0x20);
115 pm2_blk |= 0x01;
116 outb(pm2_blk, (pmbase + 0x20));
117
118 /* Actual transition */
119 outb(value, (pmbase + 0x50));
120
121 /* Restore bus master arbitration */
122 pm2_blk &= 0xfe;
123 outb(pm2_blk, (pmbase + 0x20));
124
125 /* check if transition was successful */
126 value = inb(pmbase + 0x50);
127
128 /* Enable IRQs */
129 local_irq_restore(flags);
130
131 pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
132
133 if (state == (value & 0x1))
134 pr_debug("change to %u MHz succeeded\n",
135 speedstep_get_frequency(speedstep_processor) / 1000);
136 else
137 printk(KERN_ERR "cpufreq: change failed - I/O error\n");
138
139 return;
140}
141
142/* Wrapper for smp_call_function_single. */
143static void _speedstep_set_state(void *_state)
144{
145 speedstep_set_state(*(unsigned int *)_state);
146}
147
148/**
149 * speedstep_activate - activate SpeedStep control in the chipset
150 *
151 * Tries to activate the SpeedStep status and control registers.
152 * Returns -EINVAL on an unsupported chipset, and zero on success.
153 */
154static int speedstep_activate(void)
155{
156 u16 value = 0;
157
158 if (!speedstep_chipset_dev)
159 return -EINVAL;
160
161 pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
162 if (!(value & 0x08)) {
163 value |= 0x08;
164 pr_debug("activating SpeedStep (TM) registers\n");
165 pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
166 }
167
168 return 0;
169}
170
171
172/**
173 * speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
174 *
175 * Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
176 * the LPC bridge / PM module which contains all power-management
177 * functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
178 * chipset, or zero on failure.
179 */
180static unsigned int speedstep_detect_chipset(void)
181{
182 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
183 PCI_DEVICE_ID_INTEL_82801DB_12,
184 PCI_ANY_ID, PCI_ANY_ID,
185 NULL);
186 if (speedstep_chipset_dev)
187 return 4; /* 4-M */
188
189 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
190 PCI_DEVICE_ID_INTEL_82801CA_12,
191 PCI_ANY_ID, PCI_ANY_ID,
192 NULL);
193 if (speedstep_chipset_dev)
194 return 3; /* 3-M */
195
196
197 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
198 PCI_DEVICE_ID_INTEL_82801BA_10,
199 PCI_ANY_ID, PCI_ANY_ID,
200 NULL);
201 if (speedstep_chipset_dev) {
202 /* speedstep.c causes lockups on Dell Inspirons 8000 and
203 * 8100 which use a pretty old revision of the 82815
204 * host brige. Abort on these systems.
205 */
206 static struct pci_dev *hostbridge;
207
208 hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
209 PCI_DEVICE_ID_INTEL_82815_MC,
210 PCI_ANY_ID, PCI_ANY_ID,
211 NULL);
212
213 if (!hostbridge)
214 return 2; /* 2-M */
215
216 if (hostbridge->revision < 5) {
217 pr_debug("hostbridge does not support speedstep\n");
218 speedstep_chipset_dev = NULL;
219 pci_dev_put(hostbridge);
220 return 0;
221 }
222
223 pci_dev_put(hostbridge);
224 return 2; /* 2-M */
225 }
226
227 return 0;
228}
229
230static void get_freq_data(void *_speed)
231{
232 unsigned int *speed = _speed;
233
234 *speed = speedstep_get_frequency(speedstep_processor);
235}
236
237static unsigned int speedstep_get(unsigned int cpu)
238{
239 unsigned int speed;
240
241 /* You're supposed to ensure CPU is online. */
242 if (smp_call_function_single(cpu, get_freq_data, &speed, 1) != 0)
243 BUG();
244
245 pr_debug("detected %u kHz as current frequency\n", speed);
246 return speed;
247}
248
249/**
250 * speedstep_target - set a new CPUFreq policy
251 * @policy: new policy
252 * @target_freq: the target frequency
253 * @relation: how that frequency relates to achieved frequency
254 * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
255 *
256 * Sets a new CPUFreq policy.
257 */
258static int speedstep_target(struct cpufreq_policy *policy,
259 unsigned int target_freq,
260 unsigned int relation)
261{
262 unsigned int newstate = 0, policy_cpu;
263 struct cpufreq_freqs freqs;
264 int i;
265
266 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0],
267 target_freq, relation, &newstate))
268 return -EINVAL;
269
270 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
271 freqs.old = speedstep_get(policy_cpu);
272 freqs.new = speedstep_freqs[newstate].frequency;
273 freqs.cpu = policy->cpu;
274
275 pr_debug("transiting from %u to %u kHz\n", freqs.old, freqs.new);
276
277 /* no transition necessary */
278 if (freqs.old == freqs.new)
279 return 0;
280
281 for_each_cpu(i, policy->cpus) {
282 freqs.cpu = i;
283 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
284 }
285
286 smp_call_function_single(policy_cpu, _speedstep_set_state, &newstate,
287 true);
288
289 for_each_cpu(i, policy->cpus) {
290 freqs.cpu = i;
291 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
292 }
293
294 return 0;
295}
296
297
298/**
299 * speedstep_verify - verifies a new CPUFreq policy
300 * @policy: new policy
301 *
302 * Limit must be within speedstep_low_freq and speedstep_high_freq, with
303 * at least one border included.
304 */
305static int speedstep_verify(struct cpufreq_policy *policy)
306{
307 return cpufreq_frequency_table_verify(policy, &speedstep_freqs[0]);
308}
309
310struct get_freqs {
311 struct cpufreq_policy *policy;
312 int ret;
313};
314
315static void get_freqs_on_cpu(void *_get_freqs)
316{
317 struct get_freqs *get_freqs = _get_freqs;
318
319 get_freqs->ret =
320 speedstep_get_freqs(speedstep_processor,
321 &speedstep_freqs[SPEEDSTEP_LOW].frequency,
322 &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
323 &get_freqs->policy->cpuinfo.transition_latency,
324 &speedstep_set_state);
325}
326
327static int speedstep_cpu_init(struct cpufreq_policy *policy)
328{
329 int result;
330 unsigned int policy_cpu, speed;
331 struct get_freqs gf;
332
333 /* only run on CPU to be set, or on its sibling */
334#ifdef CONFIG_SMP
335 cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
336#endif
337 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
338
339 /* detect low and high frequency and transition latency */
340 gf.policy = policy;
341 smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
342 if (gf.ret)
343 return gf.ret;
344
345 /* get current speed setting */
346 speed = speedstep_get(policy_cpu);
347 if (!speed)
348 return -EIO;
349
350 pr_debug("currently at %s speed setting - %i MHz\n",
351 (speed == speedstep_freqs[SPEEDSTEP_LOW].frequency)
352 ? "low" : "high",
353 (speed / 1000));
354
355 /* cpuinfo and default policy values */
356 policy->cur = speed;
357
358 result = cpufreq_frequency_table_cpuinfo(policy, speedstep_freqs);
359 if (result)
360 return result;
361
362 cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
363
364 return 0;
365}
366
367
368static int speedstep_cpu_exit(struct cpufreq_policy *policy)
369{
370 cpufreq_frequency_table_put_attr(policy->cpu);
371 return 0;
372}
373
374static struct freq_attr *speedstep_attr[] = {
375 &cpufreq_freq_attr_scaling_available_freqs,
376 NULL,
377};
378
379
380static struct cpufreq_driver speedstep_driver = {
381 .name = "speedstep-ich",
382 .verify = speedstep_verify,
383 .target = speedstep_target,
384 .init = speedstep_cpu_init,
385 .exit = speedstep_cpu_exit,
386 .get = speedstep_get,
387 .owner = THIS_MODULE,
388 .attr = speedstep_attr,
389};
390
391
392/**
393 * speedstep_init - initializes the SpeedStep CPUFreq driver
394 *
395 * Initializes the SpeedStep support. Returns -ENODEV on unsupported
396 * devices, -EINVAL on problems during initiatization, and zero on
397 * success.
398 */
399static int __init speedstep_init(void)
400{
401 /* detect processor */
402 speedstep_processor = speedstep_detect_processor();
403 if (!speedstep_processor) {
404 pr_debug("Intel(R) SpeedStep(TM) capable processor "
405 "not found\n");
406 return -ENODEV;
407 }
408
409 /* detect chipset */
410 if (!speedstep_detect_chipset()) {
411 pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
412 "(yet) available.\n");
413 return -ENODEV;
414 }
415
416 /* activate speedstep support */
417 if (speedstep_activate()) {
418 pci_dev_put(speedstep_chipset_dev);
419 return -EINVAL;
420 }
421
422 if (speedstep_find_register())
423 return -ENODEV;
424
425 return cpufreq_register_driver(&speedstep_driver);
426}
427
428
429/**
430 * speedstep_exit - unregisters SpeedStep support
431 *
432 * Unregisters SpeedStep support.
433 */
434static void __exit speedstep_exit(void)
435{
436 pci_dev_put(speedstep_chipset_dev);
437 cpufreq_unregister_driver(&speedstep_driver);
438}
439
440
441MODULE_AUTHOR("Dave Jones <davej@redhat.com>, "
442 "Dominik Brodowski <linux@brodo.de>");
443MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
444 "with ICH-M southbridges.");
445MODULE_LICENSE("GPL");
446
447module_init(speedstep_init);
448module_exit(speedstep_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
deleted file mode 100644
index 8af2d2fd9d51..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
+++ /dev/null
@@ -1,478 +0,0 @@
1/*
2 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
3 *
4 * Licensed under the terms of the GNU GPL License version 2.
5 *
6 * Library for common functions for Intel SpeedStep v.1 and v.2 support
7 *
8 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/cpufreq.h>
16
17#include <asm/msr.h>
18#include <asm/tsc.h>
19#include "speedstep-lib.h"
20
21#define PFX "speedstep-lib: "
22
23#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
24static int relaxed_check;
25#else
26#define relaxed_check 0
27#endif
28
29/*********************************************************************
30 * GET PROCESSOR CORE SPEED IN KHZ *
31 *********************************************************************/
32
33static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
34{
35 /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
36 struct {
37 unsigned int ratio; /* Frequency Multiplier (x10) */
38 u8 bitmap; /* power on configuration bits
39 [27, 25:22] (in MSR 0x2a) */
40 } msr_decode_mult[] = {
41 { 30, 0x01 },
42 { 35, 0x05 },
43 { 40, 0x02 },
44 { 45, 0x06 },
45 { 50, 0x00 },
46 { 55, 0x04 },
47 { 60, 0x0b },
48 { 65, 0x0f },
49 { 70, 0x09 },
50 { 75, 0x0d },
51 { 80, 0x0a },
52 { 85, 0x26 },
53 { 90, 0x20 },
54 { 100, 0x2b },
55 { 0, 0xff } /* error or unknown value */
56 };
57
58 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
59 struct {
60 unsigned int value; /* Front Side Bus speed in MHz */
61 u8 bitmap; /* power on configuration bits [18: 19]
62 (in MSR 0x2a) */
63 } msr_decode_fsb[] = {
64 { 66, 0x0 },
65 { 100, 0x2 },
66 { 133, 0x1 },
67 { 0, 0xff}
68 };
69
70 u32 msr_lo, msr_tmp;
71 int i = 0, j = 0;
72
73 /* read MSR 0x2a - we only need the low 32 bits */
74 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
75 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
76 msr_tmp = msr_lo;
77
78 /* decode the FSB */
79 msr_tmp &= 0x00c0000;
80 msr_tmp >>= 18;
81 while (msr_tmp != msr_decode_fsb[i].bitmap) {
82 if (msr_decode_fsb[i].bitmap == 0xff)
83 return 0;
84 i++;
85 }
86
87 /* decode the multiplier */
88 if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
89 pr_debug("workaround for early PIIIs\n");
90 msr_lo &= 0x03c00000;
91 } else
92 msr_lo &= 0x0bc00000;
93 msr_lo >>= 22;
94 while (msr_lo != msr_decode_mult[j].bitmap) {
95 if (msr_decode_mult[j].bitmap == 0xff)
96 return 0;
97 j++;
98 }
99
100 pr_debug("speed is %u\n",
101 (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
102
103 return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
104}
105
106
107static unsigned int pentiumM_get_frequency(void)
108{
109 u32 msr_lo, msr_tmp;
110
111 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
112 pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
113
114 /* see table B-2 of 24547212.pdf */
115 if (msr_lo & 0x00040000) {
116 printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
117 msr_lo, msr_tmp);
118 return 0;
119 }
120
121 msr_tmp = (msr_lo >> 22) & 0x1f;
122 pr_debug("bits 22-26 are 0x%x, speed is %u\n",
123 msr_tmp, (msr_tmp * 100 * 1000));
124
125 return msr_tmp * 100 * 1000;
126}
127
128static unsigned int pentium_core_get_frequency(void)
129{
130 u32 fsb = 0;
131 u32 msr_lo, msr_tmp;
132 int ret;
133
134 rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
135 /* see table B-2 of 25366920.pdf */
136 switch (msr_lo & 0x07) {
137 case 5:
138 fsb = 100000;
139 break;
140 case 1:
141 fsb = 133333;
142 break;
143 case 3:
144 fsb = 166667;
145 break;
146 case 2:
147 fsb = 200000;
148 break;
149 case 0:
150 fsb = 266667;
151 break;
152 case 4:
153 fsb = 333333;
154 break;
155 default:
156 printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
157 }
158
159 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
160 pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
161 msr_lo, msr_tmp);
162
163 msr_tmp = (msr_lo >> 22) & 0x1f;
164 pr_debug("bits 22-26 are 0x%x, speed is %u\n",
165 msr_tmp, (msr_tmp * fsb));
166
167 ret = (msr_tmp * fsb);
168 return ret;
169}
170
171
172static unsigned int pentium4_get_frequency(void)
173{
174 struct cpuinfo_x86 *c = &boot_cpu_data;
175 u32 msr_lo, msr_hi, mult;
176 unsigned int fsb = 0;
177 unsigned int ret;
178 u8 fsb_code;
179
180 /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
181 * to System Bus Frequency Ratio Field in the Processor Frequency
182 * Configuration Register of the MSR. Therefore the current
183 * frequency cannot be calculated and has to be measured.
184 */
185 if (c->x86_model < 2)
186 return cpu_khz;
187
188 rdmsr(0x2c, msr_lo, msr_hi);
189
190 pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
191
192 /* decode the FSB: see IA-32 Intel (C) Architecture Software
193 * Developer's Manual, Volume 3: System Prgramming Guide,
194 * revision #12 in Table B-1: MSRs in the Pentium 4 and
195 * Intel Xeon Processors, on page B-4 and B-5.
196 */
197 fsb_code = (msr_lo >> 16) & 0x7;
198 switch (fsb_code) {
199 case 0:
200 fsb = 100 * 1000;
201 break;
202 case 1:
203 fsb = 13333 * 10;
204 break;
205 case 2:
206 fsb = 200 * 1000;
207 break;
208 }
209
210 if (!fsb)
211 printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
212 "Please send an e-mail to <linux@brodo.de>\n");
213
214 /* Multiplier. */
215 mult = msr_lo >> 24;
216
217 pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
218 fsb, mult, (fsb * mult));
219
220 ret = (fsb * mult);
221 return ret;
222}
223
224
225/* Warning: may get called from smp_call_function_single. */
226unsigned int speedstep_get_frequency(enum speedstep_processor processor)
227{
228 switch (processor) {
229 case SPEEDSTEP_CPU_PCORE:
230 return pentium_core_get_frequency();
231 case SPEEDSTEP_CPU_PM:
232 return pentiumM_get_frequency();
233 case SPEEDSTEP_CPU_P4D:
234 case SPEEDSTEP_CPU_P4M:
235 return pentium4_get_frequency();
236 case SPEEDSTEP_CPU_PIII_T:
237 case SPEEDSTEP_CPU_PIII_C:
238 case SPEEDSTEP_CPU_PIII_C_EARLY:
239 return pentium3_get_frequency(processor);
240 default:
241 return 0;
242 };
243 return 0;
244}
245EXPORT_SYMBOL_GPL(speedstep_get_frequency);
246
247
248/*********************************************************************
249 * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
250 *********************************************************************/
251
252unsigned int speedstep_detect_processor(void)
253{
254 struct cpuinfo_x86 *c = &cpu_data(0);
255 u32 ebx, msr_lo, msr_hi;
256
257 pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
258
259 if ((c->x86_vendor != X86_VENDOR_INTEL) ||
260 ((c->x86 != 6) && (c->x86 != 0xF)))
261 return 0;
262
263 if (c->x86 == 0xF) {
264 /* Intel Mobile Pentium 4-M
265 * or Intel Mobile Pentium 4 with 533 MHz FSB */
266 if (c->x86_model != 2)
267 return 0;
268
269 ebx = cpuid_ebx(0x00000001);
270 ebx &= 0x000000FF;
271
272 pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
273
274 switch (c->x86_mask) {
275 case 4:
276 /*
277 * B-stepping [M-P4-M]
278 * sample has ebx = 0x0f, production has 0x0e.
279 */
280 if ((ebx == 0x0e) || (ebx == 0x0f))
281 return SPEEDSTEP_CPU_P4M;
282 break;
283 case 7:
284 /*
285 * C-stepping [M-P4-M]
286 * needs to have ebx=0x0e, else it's a celeron:
287 * cf. 25130917.pdf / page 7, footnote 5 even
288 * though 25072120.pdf / page 7 doesn't say
289 * samples are only of B-stepping...
290 */
291 if (ebx == 0x0e)
292 return SPEEDSTEP_CPU_P4M;
293 break;
294 case 9:
295 /*
296 * D-stepping [M-P4-M or M-P4/533]
297 *
298 * this is totally strange: CPUID 0x0F29 is
299 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
300 * The latter need to be sorted out as they don't
301 * support speedstep.
302 * Celerons with CPUID 0x0F29 may have either
303 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
304 * specific.
305 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
306 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
307 * also, M-P4M HTs have ebx=0x8, too
308 * For now, they are distinguished by the model_id
309 * string
310 */
311 if ((ebx == 0x0e) ||
312 (strstr(c->x86_model_id,
313 "Mobile Intel(R) Pentium(R) 4") != NULL))
314 return SPEEDSTEP_CPU_P4M;
315 break;
316 default:
317 break;
318 }
319 return 0;
320 }
321
322 switch (c->x86_model) {
323 case 0x0B: /* Intel PIII [Tualatin] */
324 /* cpuid_ebx(1) is 0x04 for desktop PIII,
325 * 0x06 for mobile PIII-M */
326 ebx = cpuid_ebx(0x00000001);
327 pr_debug("ebx is %x\n", ebx);
328
329 ebx &= 0x000000FF;
330
331 if (ebx != 0x06)
332 return 0;
333
334 /* So far all PIII-M processors support SpeedStep. See
335 * Intel's 24540640.pdf of June 2003
336 */
337 return SPEEDSTEP_CPU_PIII_T;
338
339 case 0x08: /* Intel PIII [Coppermine] */
340
341 /* all mobile PIII Coppermines have FSB 100 MHz
342 * ==> sort out a few desktop PIIIs. */
343 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
344 pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
345 msr_lo, msr_hi);
346 msr_lo &= 0x00c0000;
347 if (msr_lo != 0x0080000)
348 return 0;
349
350 /*
351 * If the processor is a mobile version,
352 * platform ID has bit 50 set
353 * it has SpeedStep technology if either
354 * bit 56 or 57 is set
355 */
356 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
357 pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
358 msr_lo, msr_hi);
359 if ((msr_hi & (1<<18)) &&
360 (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
361 if (c->x86_mask == 0x01) {
362 pr_debug("early PIII version\n");
363 return SPEEDSTEP_CPU_PIII_C_EARLY;
364 } else
365 return SPEEDSTEP_CPU_PIII_C;
366 }
367
368 default:
369 return 0;
370 }
371}
372EXPORT_SYMBOL_GPL(speedstep_detect_processor);
373
374
375/*********************************************************************
376 * DETECT SPEEDSTEP SPEEDS *
377 *********************************************************************/
378
379unsigned int speedstep_get_freqs(enum speedstep_processor processor,
380 unsigned int *low_speed,
381 unsigned int *high_speed,
382 unsigned int *transition_latency,
383 void (*set_state) (unsigned int state))
384{
385 unsigned int prev_speed;
386 unsigned int ret = 0;
387 unsigned long flags;
388 struct timeval tv1, tv2;
389
390 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
391 return -EINVAL;
392
393 pr_debug("trying to determine both speeds\n");
394
395 /* get current speed */
396 prev_speed = speedstep_get_frequency(processor);
397 if (!prev_speed)
398 return -EIO;
399
400 pr_debug("previous speed is %u\n", prev_speed);
401
402 local_irq_save(flags);
403
404 /* switch to low state */
405 set_state(SPEEDSTEP_LOW);
406 *low_speed = speedstep_get_frequency(processor);
407 if (!*low_speed) {
408 ret = -EIO;
409 goto out;
410 }
411
412 pr_debug("low speed is %u\n", *low_speed);
413
414 /* start latency measurement */
415 if (transition_latency)
416 do_gettimeofday(&tv1);
417
418 /* switch to high state */
419 set_state(SPEEDSTEP_HIGH);
420
421 /* end latency measurement */
422 if (transition_latency)
423 do_gettimeofday(&tv2);
424
425 *high_speed = speedstep_get_frequency(processor);
426 if (!*high_speed) {
427 ret = -EIO;
428 goto out;
429 }
430
431 pr_debug("high speed is %u\n", *high_speed);
432
433 if (*low_speed == *high_speed) {
434 ret = -ENODEV;
435 goto out;
436 }
437
438 /* switch to previous state, if necessary */
439 if (*high_speed != prev_speed)
440 set_state(SPEEDSTEP_LOW);
441
442 if (transition_latency) {
443 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
444 tv2.tv_usec - tv1.tv_usec;
445 pr_debug("transition latency is %u uSec\n", *transition_latency);
446
447 /* convert uSec to nSec and add 20% for safety reasons */
448 *transition_latency *= 1200;
449
450 /* check if the latency measurement is too high or too low
451 * and set it to a safe value (500uSec) in that case
452 */
453 if (*transition_latency > 10000000 ||
454 *transition_latency < 50000) {
455 printk(KERN_WARNING PFX "frequency transition "
456 "measured seems out of range (%u "
457 "nSec), falling back to a safe one of"
458 "%u nSec.\n",
459 *transition_latency, 500000);
460 *transition_latency = 500000;
461 }
462 }
463
464out:
465 local_irq_restore(flags);
466 return ret;
467}
468EXPORT_SYMBOL_GPL(speedstep_get_freqs);
469
470#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
471module_param(relaxed_check, int, 0444);
472MODULE_PARM_DESC(relaxed_check,
473 "Don't do all checks for speedstep capability.");
474#endif
475
476MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
477MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
478MODULE_LICENSE("GPL");
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.h b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.h
deleted file mode 100644
index 70d9cea1219d..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
3 *
4 * Licensed under the terms of the GNU GPL License version 2.
5 *
6 * Library for common functions for Intel SpeedStep v.1 and v.2 support
7 *
8 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
9 */
10
11
12
13/* processors */
14enum speedstep_processor {
15 SPEEDSTEP_CPU_PIII_C_EARLY = 0x00000001, /* Coppermine core */
16 SPEEDSTEP_CPU_PIII_C = 0x00000002, /* Coppermine core */
17 SPEEDSTEP_CPU_PIII_T = 0x00000003, /* Tualatin core */
18 SPEEDSTEP_CPU_P4M = 0x00000004, /* P4-M */
19/* the following processors are not speedstep-capable and are not auto-detected
20 * in speedstep_detect_processor(). However, their speed can be detected using
21 * the speedstep_get_frequency() call. */
22 SPEEDSTEP_CPU_PM = 0xFFFFFF03, /* Pentium M */
23 SPEEDSTEP_CPU_P4D = 0xFFFFFF04, /* desktop P4 */
24 SPEEDSTEP_CPU_PCORE = 0xFFFFFF05, /* Core */
25};
26
27/* speedstep states -- only two of them */
28
29#define SPEEDSTEP_HIGH 0x00000000
30#define SPEEDSTEP_LOW 0x00000001
31
32
33/* detect a speedstep-capable processor */
34extern enum speedstep_processor speedstep_detect_processor(void);
35
36/* detect the current speed (in khz) of the processor */
37extern unsigned int speedstep_get_frequency(enum speedstep_processor processor);
38
39
40/* detect the low and high speeds of the processor. The callback
41 * set_state"'s first argument is either SPEEDSTEP_HIGH or
42 * SPEEDSTEP_LOW; the second argument is zero so that no
43 * cpufreq_notify_transition calls are initiated.
44 */
45extern unsigned int speedstep_get_freqs(enum speedstep_processor processor,
46 unsigned int *low_speed,
47 unsigned int *high_speed,
48 unsigned int *transition_latency,
49 void (*set_state) (unsigned int state));
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c b/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
deleted file mode 100644
index c76ead3490bf..000000000000
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
+++ /dev/null
@@ -1,464 +0,0 @@
1/*
2 * Intel SpeedStep SMI driver.
3 *
4 * (C) 2003 Hiroshi Miura <miura@da-cha.org>
5 *
6 * Licensed under the terms of the GNU GPL License version 2.
7 *
8 */
9
10
11/*********************************************************************
12 * SPEEDSTEP - DEFINITIONS *
13 *********************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/init.h>
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <asm/ist.h>
23
24#include "speedstep-lib.h"
25
26/* speedstep system management interface port/command.
27 *
28 * These parameters are got from IST-SMI BIOS call.
29 * If user gives it, these are used.
30 *
31 */
32static int smi_port;
33static int smi_cmd;
34static unsigned int smi_sig;
35
36/* info about the processor */
37static enum speedstep_processor speedstep_processor;
38
39/*
40 * There are only two frequency states for each processor. Values
41 * are in kHz for the time being.
42 */
43static struct cpufreq_frequency_table speedstep_freqs[] = {
44 {SPEEDSTEP_HIGH, 0},
45 {SPEEDSTEP_LOW, 0},
46 {0, CPUFREQ_TABLE_END},
47};
48
49#define GET_SPEEDSTEP_OWNER 0
50#define GET_SPEEDSTEP_STATE 1
51#define SET_SPEEDSTEP_STATE 2
52#define GET_SPEEDSTEP_FREQS 4
53
54/* how often shall the SMI call be tried if it failed, e.g. because
55 * of DMA activity going on? */
56#define SMI_TRIES 5
57
58/**
59 * speedstep_smi_ownership
60 */
61static int speedstep_smi_ownership(void)
62{
63 u32 command, result, magic, dummy;
64 u32 function = GET_SPEEDSTEP_OWNER;
65 unsigned char magic_data[] = "Copyright (c) 1999 Intel Corporation";
66
67 command = (smi_sig & 0xffffff00) | (smi_cmd & 0xff);
68 magic = virt_to_phys(magic_data);
69
70 pr_debug("trying to obtain ownership with command %x at port %x\n",
71 command, smi_port);
72
73 __asm__ __volatile__(
74 "push %%ebp\n"
75 "out %%al, (%%dx)\n"
76 "pop %%ebp\n"
77 : "=D" (result),
78 "=a" (dummy), "=b" (dummy), "=c" (dummy), "=d" (dummy),
79 "=S" (dummy)
80 : "a" (command), "b" (function), "c" (0), "d" (smi_port),
81 "D" (0), "S" (magic)
82 : "memory"
83 );
84
85 pr_debug("result is %x\n", result);
86
87 return result;
88}
89
90/**
91 * speedstep_smi_get_freqs - get SpeedStep preferred & current freq.
92 * @low: the low frequency value is placed here
93 * @high: the high frequency value is placed here
94 *
95 * Only available on later SpeedStep-enabled systems, returns false results or
96 * even hangs [cf. bugme.osdl.org # 1422] on earlier systems. Empirical testing
97 * shows that the latter occurs if !(ist_info.event & 0xFFFF).
98 */
99static int speedstep_smi_get_freqs(unsigned int *low, unsigned int *high)
100{
101 u32 command, result = 0, edi, high_mhz, low_mhz, dummy;
102 u32 state = 0;
103 u32 function = GET_SPEEDSTEP_FREQS;
104
105 if (!(ist_info.event & 0xFFFF)) {
106 pr_debug("bug #1422 -- can't read freqs from BIOS\n");
107 return -ENODEV;
108 }
109
110 command = (smi_sig & 0xffffff00) | (smi_cmd & 0xff);
111
112 pr_debug("trying to determine frequencies with command %x at port %x\n",
113 command, smi_port);
114
115 __asm__ __volatile__(
116 "push %%ebp\n"
117 "out %%al, (%%dx)\n"
118 "pop %%ebp"
119 : "=a" (result),
120 "=b" (high_mhz),
121 "=c" (low_mhz),
122 "=d" (state), "=D" (edi), "=S" (dummy)
123 : "a" (command),
124 "b" (function),
125 "c" (state),
126 "d" (smi_port), "S" (0), "D" (0)
127 );
128
129 pr_debug("result %x, low_freq %u, high_freq %u\n",
130 result, low_mhz, high_mhz);
131
132 /* abort if results are obviously incorrect... */
133 if ((high_mhz + low_mhz) < 600)
134 return -EINVAL;
135
136 *high = high_mhz * 1000;
137 *low = low_mhz * 1000;
138
139 return result;
140}
141
142/**
143 * speedstep_get_state - set the SpeedStep state
144 * @state: processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
145 *
146 */
147static int speedstep_get_state(void)
148{
149 u32 function = GET_SPEEDSTEP_STATE;
150 u32 result, state, edi, command, dummy;
151
152 command = (smi_sig & 0xffffff00) | (smi_cmd & 0xff);
153
154 pr_debug("trying to determine current setting with command %x "
155 "at port %x\n", command, smi_port);
156
157 __asm__ __volatile__(
158 "push %%ebp\n"
159 "out %%al, (%%dx)\n"
160 "pop %%ebp\n"
161 : "=a" (result),
162 "=b" (state), "=D" (edi),
163 "=c" (dummy), "=d" (dummy), "=S" (dummy)
164 : "a" (command), "b" (function), "c" (0),
165 "d" (smi_port), "S" (0), "D" (0)
166 );
167
168 pr_debug("state is %x, result is %x\n", state, result);
169
170 return state & 1;
171}
172
173
174/**
175 * speedstep_set_state - set the SpeedStep state
176 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
177 *
178 */
179static void speedstep_set_state(unsigned int state)
180{
181 unsigned int result = 0, command, new_state, dummy;
182 unsigned long flags;
183 unsigned int function = SET_SPEEDSTEP_STATE;
184 unsigned int retry = 0;
185
186 if (state > 0x1)
187 return;
188
189 /* Disable IRQs */
190 local_irq_save(flags);
191
192 command = (smi_sig & 0xffffff00) | (smi_cmd & 0xff);
193
194 pr_debug("trying to set frequency to state %u "
195 "with command %x at port %x\n",
196 state, command, smi_port);
197
198 do {
199 if (retry) {
200 pr_debug("retry %u, previous result %u, waiting...\n",
201 retry, result);
202 mdelay(retry * 50);
203 }
204 retry++;
205 __asm__ __volatile__(
206 "push %%ebp\n"
207 "out %%al, (%%dx)\n"
208 "pop %%ebp"
209 : "=b" (new_state), "=D" (result),
210 "=c" (dummy), "=a" (dummy),
211 "=d" (dummy), "=S" (dummy)
212 : "a" (command), "b" (function), "c" (state),
213 "d" (smi_port), "S" (0), "D" (0)
214 );
215 } while ((new_state != state) && (retry <= SMI_TRIES));
216
217 /* enable IRQs */
218 local_irq_restore(flags);
219
220 if (new_state == state)
221 pr_debug("change to %u MHz succeeded after %u tries "
222 "with result %u\n",
223 (speedstep_freqs[new_state].frequency / 1000),
224 retry, result);
225 else
226 printk(KERN_ERR "cpufreq: change to state %u "
227 "failed with new_state %u and result %u\n",
228 state, new_state, result);
229
230 return;
231}
232
233
234/**
235 * speedstep_target - set a new CPUFreq policy
236 * @policy: new policy
237 * @target_freq: new freq
238 * @relation:
239 *
240 * Sets a new CPUFreq policy/freq.
241 */
242static int speedstep_target(struct cpufreq_policy *policy,
243 unsigned int target_freq, unsigned int relation)
244{
245 unsigned int newstate = 0;
246 struct cpufreq_freqs freqs;
247
248 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0],
249 target_freq, relation, &newstate))
250 return -EINVAL;
251
252 freqs.old = speedstep_freqs[speedstep_get_state()].frequency;
253 freqs.new = speedstep_freqs[newstate].frequency;
254 freqs.cpu = 0; /* speedstep.c is UP only driver */
255
256 if (freqs.old == freqs.new)
257 return 0;
258
259 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
260 speedstep_set_state(newstate);
261 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
262
263 return 0;
264}
265
266
267/**
268 * speedstep_verify - verifies a new CPUFreq policy
269 * @policy: new policy
270 *
271 * Limit must be within speedstep_low_freq and speedstep_high_freq, with
272 * at least one border included.
273 */
274static int speedstep_verify(struct cpufreq_policy *policy)
275{
276 return cpufreq_frequency_table_verify(policy, &speedstep_freqs[0]);
277}
278
279
280static int speedstep_cpu_init(struct cpufreq_policy *policy)
281{
282 int result;
283 unsigned int speed, state;
284 unsigned int *low, *high;
285
286 /* capability check */
287 if (policy->cpu != 0)
288 return -ENODEV;
289
290 result = speedstep_smi_ownership();
291 if (result) {
292 pr_debug("fails in acquiring ownership of a SMI interface.\n");
293 return -EINVAL;
294 }
295
296 /* detect low and high frequency */
297 low = &speedstep_freqs[SPEEDSTEP_LOW].frequency;
298 high = &speedstep_freqs[SPEEDSTEP_HIGH].frequency;
299
300 result = speedstep_smi_get_freqs(low, high);
301 if (result) {
302 /* fall back to speedstep_lib.c dection mechanism:
303 * try both states out */
304 pr_debug("could not detect low and high frequencies "
305 "by SMI call.\n");
306 result = speedstep_get_freqs(speedstep_processor,
307 low, high,
308 NULL,
309 &speedstep_set_state);
310
311 if (result) {
312 pr_debug("could not detect two different speeds"
313 " -- aborting.\n");
314 return result;
315 } else
316 pr_debug("workaround worked.\n");
317 }
318
319 /* get current speed setting */
320 state = speedstep_get_state();
321 speed = speedstep_freqs[state].frequency;
322
323 pr_debug("currently at %s speed setting - %i MHz\n",
324 (speed == speedstep_freqs[SPEEDSTEP_LOW].frequency)
325 ? "low" : "high",
326 (speed / 1000));
327
328 /* cpuinfo and default policy values */
329 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
330 policy->cur = speed;
331
332 result = cpufreq_frequency_table_cpuinfo(policy, speedstep_freqs);
333 if (result)
334 return result;
335
336 cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
337
338 return 0;
339}
340
341static int speedstep_cpu_exit(struct cpufreq_policy *policy)
342{
343 cpufreq_frequency_table_put_attr(policy->cpu);
344 return 0;
345}
346
347static unsigned int speedstep_get(unsigned int cpu)
348{
349 if (cpu)
350 return -ENODEV;
351 return speedstep_get_frequency(speedstep_processor);
352}
353
354
355static int speedstep_resume(struct cpufreq_policy *policy)
356{
357 int result = speedstep_smi_ownership();
358
359 if (result)
360 pr_debug("fails in re-acquiring ownership of a SMI interface.\n");
361
362 return result;
363}
364
365static struct freq_attr *speedstep_attr[] = {
366 &cpufreq_freq_attr_scaling_available_freqs,
367 NULL,
368};
369
370static struct cpufreq_driver speedstep_driver = {
371 .name = "speedstep-smi",
372 .verify = speedstep_verify,
373 .target = speedstep_target,
374 .init = speedstep_cpu_init,
375 .exit = speedstep_cpu_exit,
376 .get = speedstep_get,
377 .resume = speedstep_resume,
378 .owner = THIS_MODULE,
379 .attr = speedstep_attr,
380};
381
382/**
383 * speedstep_init - initializes the SpeedStep CPUFreq driver
384 *
385 * Initializes the SpeedStep support. Returns -ENODEV on unsupported
386 * BIOS, -EINVAL on problems during initiatization, and zero on
387 * success.
388 */
389static int __init speedstep_init(void)
390{
391 speedstep_processor = speedstep_detect_processor();
392
393 switch (speedstep_processor) {
394 case SPEEDSTEP_CPU_PIII_T:
395 case SPEEDSTEP_CPU_PIII_C:
396 case SPEEDSTEP_CPU_PIII_C_EARLY:
397 break;
398 default:
399 speedstep_processor = 0;
400 }
401
402 if (!speedstep_processor) {
403 pr_debug("No supported Intel CPU detected.\n");
404 return -ENODEV;
405 }
406
407 pr_debug("signature:0x%.8ulx, command:0x%.8ulx, "
408 "event:0x%.8ulx, perf_level:0x%.8ulx.\n",
409 ist_info.signature, ist_info.command,
410 ist_info.event, ist_info.perf_level);
411
412 /* Error if no IST-SMI BIOS or no PARM
413 sig= 'ISGE' aka 'Intel Speedstep Gate E' */
414 if ((ist_info.signature != 0x47534943) && (
415 (smi_port == 0) || (smi_cmd == 0)))
416 return -ENODEV;
417
418 if (smi_sig == 1)
419 smi_sig = 0x47534943;
420 else
421 smi_sig = ist_info.signature;
422
423 /* setup smi_port from MODLULE_PARM or BIOS */
424 if ((smi_port > 0xff) || (smi_port < 0))
425 return -EINVAL;
426 else if (smi_port == 0)
427 smi_port = ist_info.command & 0xff;
428
429 if ((smi_cmd > 0xff) || (smi_cmd < 0))
430 return -EINVAL;
431 else if (smi_cmd == 0)
432 smi_cmd = (ist_info.command >> 16) & 0xff;
433
434 return cpufreq_register_driver(&speedstep_driver);
435}
436
437
438/**
439 * speedstep_exit - unregisters SpeedStep support
440 *
441 * Unregisters SpeedStep support.
442 */
443static void __exit speedstep_exit(void)
444{
445 cpufreq_unregister_driver(&speedstep_driver);
446}
447
448module_param(smi_port, int, 0444);
449module_param(smi_cmd, int, 0444);
450module_param(smi_sig, uint, 0444);
451
452MODULE_PARM_DESC(smi_port, "Override the BIOS-given IST port with this value "
453 "-- Intel's default setting is 0xb2");
454MODULE_PARM_DESC(smi_cmd, "Override the BIOS-given IST command with this value "
455 "-- Intel's default setting is 0x82");
456MODULE_PARM_DESC(smi_sig, "Set to 1 to fake the IST signature when using the "
457 "SMI interface.");
458
459MODULE_AUTHOR("Hiroshi Miura");
460MODULE_DESCRIPTION("Speedstep driver for IST applet SMI interface.");
461MODULE_LICENSE("GPL");
462
463module_init(speedstep_init);
464module_exit(speedstep_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 03:42:57 -0500