perf/x86: Rename Intel specific macros

There are macros that are Intel specific and not x86 generic. Rename
them into INTEL_*.

This patch removes X86_PMC_IDX_GENERIC and does:

 $ sed -i -e 's/X86_PMC_MAX_/INTEL_PMC_MAX_/g'           \
         arch/x86/include/asm/kvm_host.h                 \
         arch/x86/include/asm/perf_event.h               \
         arch/x86/kernel/cpu/perf_event.c                \
         arch/x86/kernel/cpu/perf_event_p4.c             \
         arch/x86/kvm/pmu.c
 $ sed -i -e 's/X86_PMC_IDX_FIXED/INTEL_PMC_IDX_FIXED/g' \
         arch/x86/include/asm/perf_event.h               \
         arch/x86/kernel/cpu/perf_event.c                \
         arch/x86/kernel/cpu/perf_event_intel.c          \
         arch/x86/kernel/cpu/perf_event_intel_ds.c       \
         arch/x86/kvm/pmu.c
 $ sed -i -e 's/X86_PMC_MSK_/INTEL_PMC_MSK_/g'           \
         arch/x86/include/asm/perf_event.h               \
         arch/x86/kernel/cpu/perf_event.c

Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1340217996-2254-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

4 files changed, 29 insertions, 29 deletions

diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index e677d9923f4f..668050002602 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -63,7 +63,7 @@ u64 x86_perf_event_update(struct perf_event *event)
         int idx = hwc->idx;
         s64 delta;
 
-        if (idx == X86_PMC_IDX_FIXED_BTS)
+        if (idx == INTEL_PMC_IDX_FIXED_BTS)
                 return 0;
 
         /*
@@ -626,8 +626,8 @@ static bool __perf_sched_find_counter(struct perf_sched *sched)
         c = sched->constraints[sched->state.event];
 
         /* Prefer fixed purpose counters */
-        if (c->idxmsk64 & (~0ULL << X86_PMC_IDX_FIXED)) {
-                idx = X86_PMC_IDX_FIXED;
+        if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
+                idx = INTEL_PMC_IDX_FIXED;
                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
                         if (!__test_and_set_bit(idx, sched->state.used))
                                 goto done;
@@ -635,7 +635,7 @@ static bool __perf_sched_find_counter(struct perf_sched *sched)
         }
         /* Grab the first unused counter starting with idx */
         idx = sched->state.counter;
-        for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
+        for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
                 if (!__test_and_set_bit(idx, sched->state.used))
                         goto done;
         }
@@ -813,13 +813,13 @@ static inline void x86_assign_hw_event(struct perf_event *event,
         hwc->last_cpu = smp_processor_id();
         hwc->last_tag = ++cpuc->tags[i];
 
-        if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
+        if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
                 hwc->config_base = 0;
                 hwc->event_base = 0;
-        } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
+        } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
-                hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
-                hwc->event_base_rdpmc = (hwc->idx - X86_PMC_IDX_FIXED) | 1<<30;
+                hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
+                hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
         } else {
                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
@@ -921,7 +921,7 @@ int x86_perf_event_set_period(struct perf_event *event)
         s64 period = hwc->sample_period;
         int ret = 0, idx = hwc->idx;
 
-        if (idx == X86_PMC_IDX_FIXED_BTS)
+        if (idx == INTEL_PMC_IDX_FIXED_BTS)
                 return 0;
 
         /*
@@ -1338,21 +1338,21 @@ static int __init init_hw_perf_events(void)
         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
                 quirk->func();
 
-        if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
+        if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
-                     x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
-                x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
+                     x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
+                x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
         }
         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
 
-        if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
+        if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
-                     x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
-                x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
+                     x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
+                x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
         }
 
         x86_pmu.intel_ctrl |=
-                ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
+                ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
 
         perf_events_lapic_init();
         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
@@ -1368,7 +1368,7 @@ static int __init init_hw_perf_events(void)
                  */
                 for_each_event_constraint(c, x86_pmu.event_constraints) {
                         if (c->cmask != X86_RAW_EVENT_MASK
-                            || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) {
+                            || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
                                 continue;
                         }
 
@@ -1611,8 +1611,8 @@ static int x86_pmu_event_idx(struct perf_event *event)
         if (!x86_pmu.attr_rdpmc)
                 return 0;
 
-        if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) {
-                idx -= X86_PMC_IDX_FIXED;
+        if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
+                idx -= INTEL_PMC_IDX_FIXED;
                 idx |= 1 << 30;
         }
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 8408e37f5fa4..5b0b362c7ae6 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -747,7 +747,7 @@ static void intel_pmu_disable_all(void)
 
         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 
-        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
+        if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
                 intel_pmu_disable_bts();
 
         intel_pmu_pebs_disable_all();
@@ -763,9 +763,9 @@ static void intel_pmu_enable_all(int added)
         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
 
-        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
+        if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
                 struct perf_event *event =
-                        cpuc->events[X86_PMC_IDX_FIXED_BTS];
+                        cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 
                 if (WARN_ON_ONCE(!event))
                         return;
@@ -871,7 +871,7 @@ static inline void intel_pmu_ack_status(u64 ack)
 
 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
 {
-        int idx = hwc->idx - X86_PMC_IDX_FIXED;
+        int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
         u64 ctrl_val, mask;
 
         mask = 0xfULL << (idx * 4);
@@ -886,7 +886,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
         struct hw_perf_event *hwc = &event->hw;
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
+        if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
                 intel_pmu_disable_bts();
                 intel_pmu_drain_bts_buffer();
                 return;
@@ -915,7 +915,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
 
 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
 {
-        int idx = hwc->idx - X86_PMC_IDX_FIXED;
+        int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
         u64 ctrl_val, bits, mask;
 
         /*
@@ -949,7 +949,7 @@ static void intel_pmu_enable_event(struct perf_event *event)
         struct hw_perf_event *hwc = &event->hw;
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
+        if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
                 if (!__this_cpu_read(cpu_hw_events.enabled))
                         return;
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 026373edef7f..629ae0b7ad90 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -248,7 +248,7 @@ void reserve_ds_buffers(void)
  */
 
 struct event_constraint bts_constraint =
-        EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
+        EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 
 void intel_pmu_enable_bts(u64 config)
 {
@@ -295,7 +295,7 @@ int intel_pmu_drain_bts_buffer(void)
                 u64     to;
                 u64     flags;
         };
-        struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
+        struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
         struct bts_record *at, *top;
         struct perf_output_handle handle;
         struct perf_event_header header;
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 6c82e4037989..92c7e39a079f 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -1325,7 +1325,7 @@ __init int p4_pmu_init(void)
         unsigned int low, high;
 
         /* If we get stripped -- indexing fails */
-        BUILD_BUG_ON(ARCH_P4_MAX_CCCR > X86_PMC_MAX_GENERIC);
+        BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC);
 
         rdmsr(MSR_IA32_MISC_ENABLE, low, high);
         if (!(low & (1 << 7))) {