x86, cpu: Package Level Thermal Control, Power Limit Notification definitions

Add package level thermal and power limit feature support.

The two MSRs and features are new starting with Intel's Sandy Bridge processor.

Please check Intel 64 and IA-32 Architectures SDMV Vol 3A 14.5.6 Power Limit
Notification and 14.6 Package Level Thermal Management.

This patch also fixes a bug which defines reverse THERM_INT_LOW_ENABLE bit and
THERM_INT_HIGH_ENABLE bit.

[ hpa: fixed up against current tip:x86/cpu ]

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
LKML-Reference: <1280448826-12004-2-git-send-email-fenghua.yu@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 9815364b477e..34b4dad6f0b8 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -33,6 +33,8 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
         static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
                 { X86_FEATURE_IDA,              CR_EAX, 1, 0x00000006, 0 },
                 { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006, 0 },
+                { X86_FEATURE_PLN,              CR_EAX, 4, 0x00000006, 0 },
+                { X86_FEATURE_PTS,              CR_EAX, 6, 0x00000006, 0 },
                 { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
                 { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
                 { X86_FEATURE_XSAVEOPT,         CR_EAX, 0, 0x0000000d, 1 },