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author | H. Peter Anvin <hpa@zytor.com> | 2008-09-04 12:04:45 -0400 |
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committer | H. Peter Anvin <hpa@zytor.com> | 2008-09-04 12:04:45 -0400 |
commit | fe47784ba5cbb6b713c013e046859946789b45e4 (patch) | |
tree | 6384958d55e29be0d2eb8ae78fa437c10636d8d6 /arch/x86/kernel/cpu/perfctr-watchdog.c | |
parent | 83b8e28b14d63db928cb39e5c5ed2a548246bd71 (diff) | |
parent | af2e1f276ff08f17192411ea3b71c13a758dfe12 (diff) |
Merge branch 'x86/cpu' into x86/xsave
Conflicts:
arch/x86/kernel/cpu/feature_names.c
include/asm-x86/cpufeature.h
Diffstat (limited to 'arch/x86/kernel/cpu/perfctr-watchdog.c')
-rw-r--r-- | arch/x86/kernel/cpu/perfctr-watchdog.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c index de7439f82b92..05cc22dbd4ff 100644 --- a/arch/x86/kernel/cpu/perfctr-watchdog.c +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c | |||
@@ -478,7 +478,13 @@ static int setup_p4_watchdog(unsigned nmi_hz) | |||
478 | perfctr_msr = MSR_P4_IQ_PERFCTR1; | 478 | perfctr_msr = MSR_P4_IQ_PERFCTR1; |
479 | evntsel_msr = MSR_P4_CRU_ESCR0; | 479 | evntsel_msr = MSR_P4_CRU_ESCR0; |
480 | cccr_msr = MSR_P4_IQ_CCCR1; | 480 | cccr_msr = MSR_P4_IQ_CCCR1; |
481 | cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4); | 481 | |
482 | /* Pentium 4 D processors don't support P4_CCCR_OVF_PMI1 */ | ||
483 | if (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask == 4) | ||
484 | cccr_val = P4_CCCR_OVF_PMI0; | ||
485 | else | ||
486 | cccr_val = P4_CCCR_OVF_PMI1; | ||
487 | cccr_val |= P4_CCCR_ESCR_SELECT(4); | ||
482 | } | 488 | } |
483 | 489 | ||
484 | evntsel = P4_ESCR_EVENT_SELECT(0x3F) | 490 | evntsel = P4_ESCR_EVENT_SELECT(0x3F) |