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authorJaswinder Singh Rajput <jaswinderrajput@gmail.com>2009-02-28 08:07:49 -0500
committerIngo Molnar <mingo@elte.hu>2009-03-02 05:31:06 -0500
commit169e41eb7f5464c077a7e0e129f025759d04cc54 (patch)
treeb4b6b57274eedff0c72a37e97497bc33a5c2bd9c /arch/x86/kernel/cpu/perf_counter.c
parentf87ad35d37fa543925210550f7db20a54c83ed70 (diff)
x86: decent declarations in perf_counter.c
Impact: cleanup making decent declrations for struct pmc_x86_ops and fix checkpatch error: ERROR: Macros with complex values should be enclosed in parenthesis Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_counter.c')
-rw-r--r--arch/x86/kernel/cpu/perf_counter.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 266618aa1a03..a1f3646a3e8e 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -42,12 +42,12 @@ struct cpu_hw_counters {
42 * struct pmc_x86_ops - performance counter x86 ops 42 * struct pmc_x86_ops - performance counter x86 ops
43 */ 43 */
44struct pmc_x86_ops { 44struct pmc_x86_ops {
45 u64 (*save_disable_all) (void); 45 u64 (*save_disable_all)(void);
46 void (*restore_all) (u64 ctrl); 46 void (*restore_all)(u64 ctrl);
47 unsigned eventsel; 47 unsigned eventsel;
48 unsigned perfctr; 48 unsigned perfctr;
49 int (*event_map) (int event); 49 int (*event_map)(int event);
50 int max_events; 50 int max_events;
51}; 51};
52 52
53static struct pmc_x86_ops *pmc_ops; 53static struct pmc_x86_ops *pmc_ops;
@@ -561,7 +561,7 @@ perf_handle_group(struct perf_counter *sibling, u64 *status, u64 *overflown)
561/* 561/*
562 * Maximum interrupt frequency of 100KHz per CPU 562 * Maximum interrupt frequency of 100KHz per CPU
563 */ 563 */
564#define PERFMON_MAX_INTERRUPTS 100000/HZ 564#define PERFMON_MAX_INTERRUPTS (100000/HZ)
565 565
566/* 566/*
567 * This handler is triggered by the local APIC, so the APIC IRQ handling 567 * This handler is triggered by the local APIC, so the APIC IRQ handling