perf_counters: allow users to count user, kernel and/or hypervisor events

Impact: new perf_counter feature

This extends the perf_counter_hw_event struct with bits that specify
that events in user, kernel and/or hypervisor mode should not be
counted (i.e. should be excluded), and adds code to program the PMU
mode selection bits accordingly on x86 and powerpc.

For software counters, we don't currently have the infrastructure to
distinguish which mode an event occurs in, so we currently fail the
counter initialization if the setting of the hw_event.exclude_* bits
would require us to distinguish.  Context switches and CPU migrations
are currently considered to occur in kernel mode.

On x86, this changes the previous policy that only root can count
kernel events.  Now non-root users can count kernel events or exclude
them.  Non-root users still can't use NMI events, though.  On x86 we
don't appear to have any way to control whether hypervisor events are
counted or not, so hw_event.exclude_hv is ignored.

On powerpc, the selection of whether to count events in user, kernel
and/or hypervisor mode is PMU-wide, not per-counter, so this adds a
check that the hw_event.exclude_* settings are the same as other events
on the PMU.  Counters being added to a group have to have the same
settings as the other hardware counters in the group.  Counters and
groups can only be enabled in hw_perf_group_sched_in or power_perf_enable
if they have the same settings as any other counters already on the
PMU.  If we are not running on a hypervisor, the exclude_hv setting
is ignored (by forcing it to 0) since we can't ever get any
hypervisor events.

Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 19 insertions, 12 deletions

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 9901e46998d1..383d4c6423a1 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -107,21 +107,25 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
                 return -EINVAL;
 
         /*
-         * Count user events, and generate PMC IRQs:
+         * Generate PMC IRQs:
          * (keep 'enabled' bit clear for now)
          */
-        hwc->config = ARCH_PERFMON_EVENTSEL_USR | ARCH_PERFMON_EVENTSEL_INT;
+        hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 
         /*
-         * If privileged enough, count OS events too, and allow
-         * NMI events as well:
+         * Count user and OS events unless requested not to.
          */
-        hwc->nmi = 0;
-        if (capable(CAP_SYS_ADMIN)) {
+        if (!hw_event->exclude_user)
+                hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
+        if (!hw_event->exclude_kernel)
                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
-                if (hw_event->nmi)
-                        hwc->nmi = 1;
-        }
+
+        /*
+         * If privileged enough, allow NMI events:
+         */
+        hwc->nmi = 0;
+        if (capable(CAP_SYS_ADMIN) && hw_event->nmi)
+                hwc->nmi = 1;
 
         hwc->irq_period         = hw_event->irq_period;
         /*
@@ -248,10 +252,13 @@ __pmc_fixed_enable(struct perf_counter *counter,
         int err;
 
         /*
-         * Enable IRQ generation (0x8) and ring-3 counting (0x2),
-         * and enable ring-0 counting if allowed:
+         * Enable IRQ generation (0x8),
+         * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
+         * if requested:
          */
-        bits = 0x8ULL | 0x2ULL;
+        bits = 0x8ULL;
+        if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
+                bits |= 0x2;
         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
                 bits |= 0x1;
         bits <<= (idx * 4);