diff options
| author | Huang Ying <ying.huang@intel.com> | 2010-06-08 02:09:08 -0400 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2010-06-11 00:27:26 -0400 |
| commit | 1f9a0bd4989fd16842ad71fc89240b48ab191446 (patch) | |
| tree | 71d33c7503888bcbae670b8ce8824a2c367a6b58 /arch/x86/kernel/cpu/mcheck | |
| parent | e44a21b7268a022c7749f521c06214145bd161e4 (diff) | |
x86, mce: Rename MSR_IA32_MCx_CTL2 value
Rename CMCI_EN to MCI_CTL2_CMCI_EN and CMCI_THRESHOLD_MASK to
MCI_CTL2_CMCI_THRESHOLD_MASK to make naming consistent.
Signed-off-by: Huang Ying <ying.huang@intel.com>
LKML-Reference: <1275977348.3444.659.camel@yhuang-dev.sh.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/kernel/cpu/mcheck')
| -rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_intel.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 62b48e40920a..faf7b2919a87 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c | |||
| @@ -95,19 +95,19 @@ static void cmci_discover(int banks, int boot) | |||
| 95 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); | 95 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); |
| 96 | 96 | ||
| 97 | /* Already owned by someone else? */ | 97 | /* Already owned by someone else? */ |
| 98 | if (val & CMCI_EN) { | 98 | if (val & MCI_CTL2_CMCI_EN) { |
| 99 | if (test_and_clear_bit(i, owned) && !boot) | 99 | if (test_and_clear_bit(i, owned) && !boot) |
| 100 | print_update("SHD", &hdr, i); | 100 | print_update("SHD", &hdr, i); |
| 101 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | 101 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); |
| 102 | continue; | 102 | continue; |
| 103 | } | 103 | } |
| 104 | 104 | ||
| 105 | val |= CMCI_EN | CMCI_THRESHOLD; | 105 | val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD; |
| 106 | wrmsrl(MSR_IA32_MCx_CTL2(i), val); | 106 | wrmsrl(MSR_IA32_MCx_CTL2(i), val); |
| 107 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); | 107 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); |
| 108 | 108 | ||
| 109 | /* Did the enable bit stick? -- the bank supports CMCI */ | 109 | /* Did the enable bit stick? -- the bank supports CMCI */ |
| 110 | if (val & CMCI_EN) { | 110 | if (val & MCI_CTL2_CMCI_EN) { |
| 111 | if (!test_and_set_bit(i, owned) && !boot) | 111 | if (!test_and_set_bit(i, owned) && !boot) |
| 112 | print_update("CMCI", &hdr, i); | 112 | print_update("CMCI", &hdr, i); |
| 113 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | 113 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); |
| @@ -155,7 +155,7 @@ void cmci_clear(void) | |||
| 155 | continue; | 155 | continue; |
| 156 | /* Disable CMCI */ | 156 | /* Disable CMCI */ |
| 157 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); | 157 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); |
| 158 | val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK); | 158 | val &= ~(MCI_CTL2_CMCI_EN|MCI_CTL2_CMCI_THRESHOLD_MASK); |
| 159 | wrmsrl(MSR_IA32_MCx_CTL2(i), val); | 159 | wrmsrl(MSR_IA32_MCx_CTL2(i), val); |
| 160 | __clear_bit(i, __get_cpu_var(mce_banks_owned)); | 160 | __clear_bit(i, __get_cpu_var(mce_banks_owned)); |
| 161 | } | 161 | } |