Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (96 commits)
  apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
  apic, x86: Check if EILVT APIC registers are available (AMD only)
  x86: ioapic: Call free_irte only if interrupt remapping enabled
  arm: Use ARCH_IRQ_INIT_FLAGS
  genirq, ARM: Fix boot on ARM platforms
  genirq: Fix CONFIG_GENIRQ_NO_DEPRECATED=y build
  x86: Switch sparse_irq allocations to GFP_KERNEL
  genirq: Switch sparse_irq allocator to GFP_KERNEL
  genirq: Make sparse_lock a mutex
  x86: lguest: Use new irq allocator
  genirq: Remove the now unused sparse irq leftovers
  genirq: Sanitize dynamic irq handling
  genirq: Remove arch_init_chip_data()
  x86: xen: Sanitise sparse_irq handling
  x86: Use sane enumeration
  x86: uv: Clean up the direct access to irq_desc
  x86: Make io_apic.c local functions static
  genirq: Remove irq_2_iommu
  x86: Speed up the irq_remapped check in hot pathes
  intr_remap: Simplify the code further
  ...

Fix up trivial conflicts in arch/x86/Kconfig

1 files changed, 24 insertions, 3 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 39aaee5c1ab2..80c482382d5c 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -131,7 +131,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
         u32 low = 0, high = 0, address = 0;
         unsigned int bank, block;
         struct thresh_restart tr;
-        u8 lvt_off;
+        int lvt_off = -1;
+        u8 offset;
 
         for (bank = 0; bank < NR_BANKS; ++bank) {
                 for (block = 0; block < NR_BLOCKS; ++block) {
@@ -162,8 +163,28 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
                         if (shared_bank[bank] && c->cpu_core_id)
                                 break;
 #endif
-                        lvt_off = setup_APIC_eilvt_mce(THRESHOLD_APIC_VECTOR,
-                                                       APIC_EILVT_MSG_FIX, 0);
+                        offset = (high & MASK_LVTOFF_HI) >> 20;
+                        if (lvt_off < 0) {
+                                if (setup_APIC_eilvt(offset,
+                                                     THRESHOLD_APIC_VECTOR,
+                                                     APIC_EILVT_MSG_FIX, 0)) {
+                                        pr_err(FW_BUG "cpu %d, failed to "
+                                               "setup threshold interrupt "
+                                               "for bank %d, block %d "
+                                               "(MSR%08X=0x%x%08x)",
+                                               smp_processor_id(), bank, block,
+                                               address, high, low);
+                                        continue;
+                                }
+                                lvt_off = offset;
+                        } else if (lvt_off != offset) {
+                                pr_err(FW_BUG "cpu %d, invalid threshold "
+                                       "interrupt offset %d for bank %d,"
+                                       "block %d (MSR%08X=0x%x%08x)",
+                                       smp_processor_id(), lvt_off, bank,
+                                       block, address, high, low);
+                                continue;
+                        }
 
                         high &= ~MASK_LVTOFF_HI;
                         high |= lvt_off << 20;