Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86: (613 commits)
  x86: standalone trampoline code
  x86: move suspend wakeup code to C
  x86: coding style fixes to arch/x86/kernel/acpi/sleep.c
  x86: setup_trampoline() - fix section mismatch warning
  x86: section mismatch fixes, #1
  x86: fix paranoia about using BIOS quickboot mechanism.
  x86: print out buggy mptable
  x86: use cpu_online()
  x86: use cpumask_of_cpu()
  x86: remove unnecessary tmp local variable
  x86: remove unnecessary memset()
  x86: use ioapic_read_entry() and ioapic_write_entry()
  x86: avoid redundant loop in io_apic_level_ack_pending()
  x86: remove superfluous initialisation in boot code.
  x86: merge mpparse_{32,64}.c
  x86: unify mp_register_gsi
  x86: unify mp_config_acpi_legacy_irqs
  x86: unify mp_register_ioapic
  x86: unify uniq_io_apic_id
  x86: unify smp_scan_config
  ...

1 files changed, 53 insertions, 53 deletions

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fae31ce747bd..fe9224c51d37 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -30,7 +30,7 @@
 struct movsl_mask movsl_mask __read_mostly;
 #endif
 
-void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
+static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
         if (c->x86 == 15 && c->x86_cache_alignment == 64)
@@ -45,7 +45,7 @@ void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  *
  *      This is called before we do cpu ident work
  */
- 
+
 int __cpuinit ppro_with_ram_bug(void)
 {
         /* Uses data from early_cpu_detect now */
@@ -58,7 +58,7 @@ int __cpuinit ppro_with_ram_bug(void)
         }
         return 0;
 }
-        
+
 
 /*
  * P4 Xeon errata 037 workaround.
@@ -69,7 +69,7 @@ static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
         unsigned long lo, hi;
 
         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
-                rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
+                rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
                 if ((lo & (1<<9)) == 0) {
                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
@@ -127,10 +127,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
          */
         c->f00f_bug = 0;
         if (!paravirt_enabled() && c->x86 == 5) {
-                static int f00f_workaround_enabled = 0;
+                static int f00f_workaround_enabled;
 
                 c->f00f_bug = 1;
-                if ( !f00f_workaround_enabled ) {
+                if (!f00f_workaround_enabled) {
                         trap_init_f00f_bug();
                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
                         f00f_workaround_enabled = 1;
@@ -139,20 +139,22 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 #endif
 
         l2 = init_intel_cacheinfo(c);
-        if (c->cpuid_level > 9 ) {
+        if (c->cpuid_level > 9) {
                 unsigned eax = cpuid_eax(10);
                 /* Check for version and the number of counters */
                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
-                        set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+                        set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
         }
 
         /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
-                clear_bit(X86_FEATURE_SEP, c->x86_capability);
+                clear_cpu_cap(c, X86_FEATURE_SEP);
 
-        /* Names for the Pentium II/Celeron processors 
-           detectable only by also checking the cache size.
-           Dixon is NOT a Celeron. */
+        /*
+         * Names for the Pentium II/Celeron processors
+         * detectable only by also checking the cache size.
+         * Dixon is NOT a Celeron.
+         */
         if (c->x86 == 6) {
                 switch (c->x86_model) {
                 case 5:
@@ -163,14 +165,14 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                                         p = "Mobile Pentium II (Dixon)";
                         }
                         break;
-                        
+
                 case 6:
                         if (l2 == 128)
                                 p = "Celeron (Mendocino)";
                         else if (c->x86_mask == 0 || c->x86_mask == 5)
                                 p = "Celeron-A";
                         break;
-                        
+
                 case 8:
                         if (l2 == 128)
                                 p = "Celeron (Coppermine)";
@@ -178,9 +180,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                 }
         }
 
-        if ( p )
+        if (p)
                 strcpy(c->x86_model_id, p);
-        
+
         c->x86_max_cores = num_cpu_cores(c);
 
         detect_ht(c);
@@ -207,28 +209,29 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 #endif
 
         if (cpu_has_xmm2)
-                set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability);
+                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
         if (c->x86 == 15) {
-                set_bit(X86_FEATURE_P4, c->x86_capability);
+                set_cpu_cap(c, X86_FEATURE_P4);
         }
-        if (c->x86 == 6) 
-                set_bit(X86_FEATURE_P3, c->x86_capability);
+        if (c->x86 == 6)
+                set_cpu_cap(c, X86_FEATURE_P3);
         if (cpu_has_ds) {
                 unsigned int l1;
                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
                 if (!(l1 & (1<<11)))
-                        set_bit(X86_FEATURE_BTS, c->x86_capability);
+                        set_cpu_cap(c, X86_FEATURE_BTS);
                 if (!(l1 & (1<<12)))
-                        set_bit(X86_FEATURE_PEBS, c->x86_capability);
+                        set_cpu_cap(c, X86_FEATURE_PEBS);
         }
 
         if (cpu_has_bts)
                 ds_init_intel(c);
 }
 
-static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
+static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 {
-        /* Intel PIII Tualatin. This comes in two flavours.
+        /*
+         * Intel PIII Tualatin. This comes in two flavours.
          * One has 256kb of cache, the other 512. We have no way
          * to determine which, so we use a boottime override
          * for the 512kb model, and assume 256 otherwise.
@@ -240,42 +243,42 @@ static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned
 
 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
         .c_vendor       = "Intel",
-        .c_ident        = { "GenuineIntel" },
+        .c_ident        = { "GenuineIntel" },
         .c_models = {
-                { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = 
-                  { 
-                          [0] = "486 DX-25/33", 
-                          [1] = "486 DX-50", 
-                          [2] = "486 SX", 
-                          [3] = "486 DX/2", 
-                          [4] = "486 SL", 
-                          [5] = "486 SX/2", 
-                          [7] = "486 DX/2-WB", 
-                          [8] = "486 DX/4", 
+                { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
+                  {
+                          [0] = "486 DX-25/33",
+                          [1] = "486 DX-50",
+                          [2] = "486 SX",
+                          [3] = "486 DX/2",
+                          [4] = "486 SL",
+                          [5] = "486 SX/2",
+                          [7] = "486 DX/2-WB",
+                          [8] = "486 DX/4",
                           [9] = "486 DX/4-WB"
                   }
                 },
                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
-                  { 
-                          [0] = "Pentium 60/66 A-step", 
-                          [1] = "Pentium 60/66", 
+                  {
+                          [0] = "Pentium 60/66 A-step",
+                          [1] = "Pentium 60/66",
                           [2] = "Pentium 75 - 200",
-                          [3] = "OverDrive PODP5V83", 
+                          [3] = "OverDrive PODP5V83",
                           [4] = "Pentium MMX",
-                          [7] = "Mobile Pentium 75 - 200", 
+                          [7] = "Mobile Pentium 75 - 200",
                           [8] = "Mobile Pentium MMX"
                   }
                 },
                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
-                  { 
+                  {
                           [0] = "Pentium Pro A-step",
-                          [1] = "Pentium Pro", 
-                          [3] = "Pentium II (Klamath)", 
-                          [4] = "Pentium II (Deschutes)", 
-                          [5] = "Pentium II (Deschutes)", 
+                          [1] = "Pentium Pro",
+                          [3] = "Pentium II (Klamath)",
+                          [4] = "Pentium II (Deschutes)",
+                          [5] = "Pentium II (Deschutes)",
                           [6] = "Mobile Pentium II",
-                          [7] = "Pentium III (Katmai)", 
-                          [8] = "Pentium III (Coppermine)", 
+                          [7] = "Pentium III (Katmai)",
+                          [8] = "Pentium III (Coppermine)",
                           [10] = "Pentium III (Cascades)",
                           [11] = "Pentium III (Tualatin)",
                   }
@@ -290,15 +293,12 @@ static struct cpu_dev intel_cpu_dev __cpuinitdata = {
                   }
                 },
         },
+        .c_early_init   = early_init_intel,
         .c_init         = init_intel,
         .c_size_cache   = intel_size_cache,
 };
 
-__init int intel_cpu_init(void)
-{
-        cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
-        return 0;
-}
+cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
 
 #ifndef CONFIG_X86_CMPXCHG
 unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
@@ -364,5 +364,5 @@ unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
 EXPORT_SYMBOL(cmpxchg_486_u64);
 #endif
 
-// arch_initcall(intel_cpu_init);
+/* arch_initcall(intel_cpu_init); */