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authorKees Cook <keescook@chromium.org>2013-04-10 15:24:22 -0400
committerH. Peter Anvin <hpa@linux.intel.com>2013-04-11 16:53:19 -0400
commit4eefbe792baedb474e256d35370849992fcf1c79 (patch)
tree03a95dab4a014a7f36133f9660ca180b01df62d4 /arch/x86/kernel/cpu/intel.c
parent31880c37c11e28cb81c70757e38392b42e695dc6 (diff)
x86: Use a read-only IDT alias on all CPUs
Make a copy of the IDT (as seen via the "sidt" instruction) read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks, and has the added benefit of also not leaking the kernel base offset, if it has been relocated. We already did this on vendor == Intel and family == 5 because of the F0 0F bug -- regardless of if a particular CPU had the F0 0F bug or not. Since the workaround was so cheap, there simply was no reason to be very specific. This patch extends the readonly alias to all CPUs, but does not activate the #PF to #UD conversion code needed to deliver the proper exception in the F0 0F case except on Intel family 5 processors. Signed-off-by: Kees Cook <keescook@chromium.org> Link: http://lkml.kernel.org/r/20130410192422.GA17344@www.outflux.net Cc: Eric Northup <digitaleric@google.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r--arch/x86/kernel/cpu/intel.c18
1 files changed, 1 insertions, 17 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1905ce98bee0..71700247a5d7 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -164,20 +164,6 @@ int __cpuinit ppro_with_ram_bug(void)
164 return 0; 164 return 0;
165} 165}
166 166
167#ifdef CONFIG_X86_F00F_BUG
168static void __cpuinit trap_init_f00f_bug(void)
169{
170 __set_fixmap(FIX_F00F_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO);
171
172 /*
173 * Update the IDT descriptor and reload the IDT so that
174 * it uses the read-only mapped virtual address.
175 */
176 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
177 load_idt(&idt_descr);
178}
179#endif
180
181static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c) 167static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
182{ 168{
183 /* calling is from identify_secondary_cpu() ? */ 169 /* calling is from identify_secondary_cpu() ? */
@@ -206,8 +192,7 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
206 /* 192 /*
207 * All current models of Pentium and Pentium with MMX technology CPUs 193 * All current models of Pentium and Pentium with MMX technology CPUs
208 * have the F0 0F bug, which lets nonprivileged users lock up the 194 * have the F0 0F bug, which lets nonprivileged users lock up the
209 * system. 195 * system. Announce that the fault handler will be checking for it.
210 * Note that the workaround only should be initialized once...
211 */ 196 */
212 c->f00f_bug = 0; 197 c->f00f_bug = 0;
213 if (!paravirt_enabled() && c->x86 == 5) { 198 if (!paravirt_enabled() && c->x86 == 5) {
@@ -215,7 +200,6 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
215 200
216 c->f00f_bug = 1; 201 c->f00f_bug = 1;
217 if (!f00f_workaround_enabled) { 202 if (!f00f_workaround_enabled) {
218 trap_init_f00f_bug();
219 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); 203 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
220 f00f_workaround_enabled = 1; 204 f00f_workaround_enabled = 1;
221 } 205 }