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authorPaolo Ciarrocchi <paolo.ciarrocchi@gmail.com>2008-02-22 17:09:42 -0500
committerIngo Molnar <mingo@elte.hu>2008-04-17 11:40:49 -0400
commit65eb6b4326daddd1cccd003bd4df3fd75b06f0e1 (patch)
treed9f66b8c2f1d2acf10368257e8e8d41d9e3d8cb6 /arch/x86/kernel/cpu/intel.c
parent60e11746d97c099b305e25e587731148387d02eb (diff)
x86: coding style fixes to arch/x86/kernel/cpu/intel.c
Before: total: 37 errors, 16 warnings, 366 lines checked After: total: 0 errors, 15 warnings, 369 lines checked No code changed: arch/x86/kernel/cpu/intel.o: text data bss dec hex filename 1534 452 0 1986 7c2 intel.o.before 1534 452 0 1986 7c2 intel.o.after md5: 1ca348a06de6eb354c4b6ea715a57db5 intel.o.before.asm 1ca348a06de6eb354c4b6ea715a57db5 intel.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r--arch/x86/kernel/cpu/intel.c83
1 files changed, 43 insertions, 40 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 34468b2e2507..c9ecf378cc41 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -45,7 +45,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
45 * 45 *
46 * This is called before we do cpu ident work 46 * This is called before we do cpu ident work
47 */ 47 */
48 48
49int __cpuinit ppro_with_ram_bug(void) 49int __cpuinit ppro_with_ram_bug(void)
50{ 50{
51 /* Uses data from early_cpu_detect now */ 51 /* Uses data from early_cpu_detect now */
@@ -58,7 +58,7 @@ int __cpuinit ppro_with_ram_bug(void)
58 } 58 }
59 return 0; 59 return 0;
60} 60}
61 61
62 62
63/* 63/*
64 * P4 Xeon errata 037 workaround. 64 * P4 Xeon errata 037 workaround.
@@ -69,7 +69,7 @@ static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
69 unsigned long lo, hi; 69 unsigned long lo, hi;
70 70
71 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 71 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
72 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi); 72 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
73 if ((lo & (1<<9)) == 0) { 73 if ((lo & (1<<9)) == 0) {
74 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); 74 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
75 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); 75 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
@@ -127,10 +127,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
127 */ 127 */
128 c->f00f_bug = 0; 128 c->f00f_bug = 0;
129 if (!paravirt_enabled() && c->x86 == 5) { 129 if (!paravirt_enabled() && c->x86 == 5) {
130 static int f00f_workaround_enabled = 0; 130 static int f00f_workaround_enabled;
131 131
132 c->f00f_bug = 1; 132 c->f00f_bug = 1;
133 if ( !f00f_workaround_enabled ) { 133 if (!f00f_workaround_enabled) {
134 trap_init_f00f_bug(); 134 trap_init_f00f_bug();
135 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); 135 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
136 f00f_workaround_enabled = 1; 136 f00f_workaround_enabled = 1;
@@ -139,7 +139,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
139#endif 139#endif
140 140
141 l2 = init_intel_cacheinfo(c); 141 l2 = init_intel_cacheinfo(c);
142 if (c->cpuid_level > 9 ) { 142 if (c->cpuid_level > 9) {
143 unsigned eax = cpuid_eax(10); 143 unsigned eax = cpuid_eax(10);
144 /* Check for version and the number of counters */ 144 /* Check for version and the number of counters */
145 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 145 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
@@ -150,9 +150,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
150 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 150 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
151 clear_bit(X86_FEATURE_SEP, c->x86_capability); 151 clear_bit(X86_FEATURE_SEP, c->x86_capability);
152 152
153 /* Names for the Pentium II/Celeron processors 153 /*
154 detectable only by also checking the cache size. 154 * Names for the Pentium II/Celeron processors
155 Dixon is NOT a Celeron. */ 155 * detectable only by also checking the cache size.
156 * Dixon is NOT a Celeron.
157 */
156 if (c->x86 == 6) { 158 if (c->x86 == 6) {
157 switch (c->x86_model) { 159 switch (c->x86_model) {
158 case 5: 160 case 5:
@@ -163,14 +165,14 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
163 p = "Mobile Pentium II (Dixon)"; 165 p = "Mobile Pentium II (Dixon)";
164 } 166 }
165 break; 167 break;
166 168
167 case 6: 169 case 6:
168 if (l2 == 128) 170 if (l2 == 128)
169 p = "Celeron (Mendocino)"; 171 p = "Celeron (Mendocino)";
170 else if (c->x86_mask == 0 || c->x86_mask == 5) 172 else if (c->x86_mask == 0 || c->x86_mask == 5)
171 p = "Celeron-A"; 173 p = "Celeron-A";
172 break; 174 break;
173 175
174 case 8: 176 case 8:
175 if (l2 == 128) 177 if (l2 == 128)
176 p = "Celeron (Coppermine)"; 178 p = "Celeron (Coppermine)";
@@ -178,9 +180,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
178 } 180 }
179 } 181 }
180 182
181 if ( p ) 183 if (p)
182 strcpy(c->x86_model_id, p); 184 strcpy(c->x86_model_id, p);
183 185
184 c->x86_max_cores = num_cpu_cores(c); 186 c->x86_max_cores = num_cpu_cores(c);
185 187
186 detect_ht(c); 188 detect_ht(c);
@@ -211,7 +213,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
211 if (c->x86 == 15) { 213 if (c->x86 == 15) {
212 set_bit(X86_FEATURE_P4, c->x86_capability); 214 set_bit(X86_FEATURE_P4, c->x86_capability);
213 } 215 }
214 if (c->x86 == 6) 216 if (c->x86 == 6)
215 set_bit(X86_FEATURE_P3, c->x86_capability); 217 set_bit(X86_FEATURE_P3, c->x86_capability);
216 if (cpu_has_ds) { 218 if (cpu_has_ds) {
217 unsigned int l1; 219 unsigned int l1;
@@ -226,9 +228,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
226 ds_init_intel(c); 228 ds_init_intel(c);
227} 229}
228 230
229static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size) 231static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
230{ 232{
231 /* Intel PIII Tualatin. This comes in two flavours. 233 /*
234 * Intel PIII Tualatin. This comes in two flavours.
232 * One has 256kb of cache, the other 512. We have no way 235 * One has 256kb of cache, the other 512. We have no way
233 * to determine which, so we use a boottime override 236 * to determine which, so we use a boottime override
234 * for the 512kb model, and assume 256 otherwise. 237 * for the 512kb model, and assume 256 otherwise.
@@ -240,42 +243,42 @@ static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned
240 243
241static struct cpu_dev intel_cpu_dev __cpuinitdata = { 244static struct cpu_dev intel_cpu_dev __cpuinitdata = {
242 .c_vendor = "Intel", 245 .c_vendor = "Intel",
243 .c_ident = { "GenuineIntel" }, 246 .c_ident = { "GenuineIntel" },
244 .c_models = { 247 .c_models = {
245 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = 248 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
246 { 249 {
247 [0] = "486 DX-25/33", 250 [0] = "486 DX-25/33",
248 [1] = "486 DX-50", 251 [1] = "486 DX-50",
249 [2] = "486 SX", 252 [2] = "486 SX",
250 [3] = "486 DX/2", 253 [3] = "486 DX/2",
251 [4] = "486 SL", 254 [4] = "486 SL",
252 [5] = "486 SX/2", 255 [5] = "486 SX/2",
253 [7] = "486 DX/2-WB", 256 [7] = "486 DX/2-WB",
254 [8] = "486 DX/4", 257 [8] = "486 DX/4",
255 [9] = "486 DX/4-WB" 258 [9] = "486 DX/4-WB"
256 } 259 }
257 }, 260 },
258 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = 261 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
259 { 262 {
260 [0] = "Pentium 60/66 A-step", 263 [0] = "Pentium 60/66 A-step",
261 [1] = "Pentium 60/66", 264 [1] = "Pentium 60/66",
262 [2] = "Pentium 75 - 200", 265 [2] = "Pentium 75 - 200",
263 [3] = "OverDrive PODP5V83", 266 [3] = "OverDrive PODP5V83",
264 [4] = "Pentium MMX", 267 [4] = "Pentium MMX",
265 [7] = "Mobile Pentium 75 - 200", 268 [7] = "Mobile Pentium 75 - 200",
266 [8] = "Mobile Pentium MMX" 269 [8] = "Mobile Pentium MMX"
267 } 270 }
268 }, 271 },
269 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = 272 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
270 { 273 {
271 [0] = "Pentium Pro A-step", 274 [0] = "Pentium Pro A-step",
272 [1] = "Pentium Pro", 275 [1] = "Pentium Pro",
273 [3] = "Pentium II (Klamath)", 276 [3] = "Pentium II (Klamath)",
274 [4] = "Pentium II (Deschutes)", 277 [4] = "Pentium II (Deschutes)",
275 [5] = "Pentium II (Deschutes)", 278 [5] = "Pentium II (Deschutes)",
276 [6] = "Mobile Pentium II", 279 [6] = "Mobile Pentium II",
277 [7] = "Pentium III (Katmai)", 280 [7] = "Pentium III (Katmai)",
278 [8] = "Pentium III (Coppermine)", 281 [8] = "Pentium III (Coppermine)",
279 [10] = "Pentium III (Cascades)", 282 [10] = "Pentium III (Cascades)",
280 [11] = "Pentium III (Tualatin)", 283 [11] = "Pentium III (Tualatin)",
281 } 284 }
@@ -361,5 +364,5 @@ unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
361EXPORT_SYMBOL(cmpxchg_486_u64); 364EXPORT_SYMBOL(cmpxchg_486_u64);
362#endif 365#endif
363 366
364// arch_initcall(intel_cpu_init); 367/* arch_initcall(intel_cpu_init); */
365 368