diff options
author | Andi Kleen <ak@suse.de> | 2008-01-30 07:32:40 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-01-30 07:32:40 -0500 |
commit | 2b16a2353814a513cdb5c5c739b76a19d7ea39ce (patch) | |
tree | caee8a54a0e85b4839078286114f4c9f920ac89e /arch/x86/kernel/cpu/intel.c | |
parent | 68071a96655c883b316da9ef497f6dec8953529f (diff) |
x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detection
Need this in the next patch in time_init and that happens early.
This includes a minor fix on i386 where early_intel_workarounds()
[which is now called early_init_intel] really executes early as
the comments say.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r-- | arch/x86/kernel/cpu/intel.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 5731de3e1bd1..f1136115279a 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c | |||
@@ -29,13 +29,14 @@ | |||
29 | struct movsl_mask movsl_mask __read_mostly; | 29 | struct movsl_mask movsl_mask __read_mostly; |
30 | #endif | 30 | #endif |
31 | 31 | ||
32 | void __cpuinit early_intel_workaround(struct cpuinfo_x86 *c) | 32 | void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
33 | { | 33 | { |
34 | if (c->x86_vendor != X86_VENDOR_INTEL) | ||
35 | return; | ||
36 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | 34 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ |
37 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | 35 | if (c->x86 == 15 && c->x86_cache_alignment == 64) |
38 | c->x86_cache_alignment = 128; | 36 | c->x86_cache_alignment = 128; |
37 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || | ||
38 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | ||
39 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | ||
39 | } | 40 | } |
40 | 41 | ||
41 | /* | 42 | /* |
@@ -115,6 +116,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) | |||
115 | unsigned int l2 = 0; | 116 | unsigned int l2 = 0; |
116 | char *p = NULL; | 117 | char *p = NULL; |
117 | 118 | ||
119 | early_init_intel(c); | ||
120 | |||
118 | #ifdef CONFIG_X86_F00F_BUG | 121 | #ifdef CONFIG_X86_F00F_BUG |
119 | /* | 122 | /* |
120 | * All current models of Pentium and Pentium with MMX technology CPUs | 123 | * All current models of Pentium and Pentium with MMX technology CPUs |
@@ -210,10 +213,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) | |||
210 | } | 213 | } |
211 | if (c->x86 == 6) | 214 | if (c->x86 == 6) |
212 | set_bit(X86_FEATURE_P3, c->x86_capability); | 215 | set_bit(X86_FEATURE_P3, c->x86_capability); |
213 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || | ||
214 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | ||
215 | set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); | ||
216 | |||
217 | if (cpu_has_ds) { | 216 | if (cpu_has_ds) { |
218 | unsigned int l1; | 217 | unsigned int l1; |
219 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | 218 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); |