diff options
author | Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> | 2008-02-22 17:11:23 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-04-17 11:40:50 -0400 |
commit | adf85265b455f096fa9caf4aea51f274cdaca3c6 (patch) | |
tree | 8d95c1446173002b49c519ea4f092fa1f9d69c89 /arch/x86/kernel/cpu/cyrix.c | |
parent | 7030760ae5d29d637d1e962c70d1d9c58be3306f (diff) |
x86: coding style fixes to arch/x86/kernel/cpu/cyrix.c
Before:
total: 46 errors, 10 warnings, 450 lines checked
After:
total: 1 errors, 10 warnings, 449 lines checked
No code changed:
arch/x86/kernel/cpu/cyrix.o:
text data bss dec hex filename
2048 908 4 2960 b90 cyrix.o.before
2048 908 4 2960 b90 cyrix.o.after
md5:
9add5e69dbd788f91ff24eea8462dad7 cyrix.o.before.asm
9add5e69dbd788f91ff24eea8462dad7 cyrix.o.after.asm
Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/cyrix.c')
-rw-r--r-- | arch/x86/kernel/cpu/cyrix.c | 113 |
1 files changed, 56 insertions, 57 deletions
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c index 9c4ee98f2cb8..f7085bde4c28 100644 --- a/arch/x86/kernel/cpu/cyrix.c +++ b/arch/x86/kernel/cpu/cyrix.c | |||
@@ -19,7 +19,7 @@ static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) | |||
19 | { | 19 | { |
20 | unsigned char ccr2, ccr3; | 20 | unsigned char ccr2, ccr3; |
21 | unsigned long flags; | 21 | unsigned long flags; |
22 | 22 | ||
23 | /* we test for DEVID by checking whether CCR3 is writable */ | 23 | /* we test for DEVID by checking whether CCR3 is writable */ |
24 | local_irq_save(flags); | 24 | local_irq_save(flags); |
25 | ccr3 = getCx86(CX86_CCR3); | 25 | ccr3 = getCx86(CX86_CCR3); |
@@ -37,8 +37,7 @@ static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) | |||
37 | setCx86(CX86_CCR2, ccr2); | 37 | setCx86(CX86_CCR2, ccr2); |
38 | *dir0 = 0xfe; | 38 | *dir0 = 0xfe; |
39 | } | 39 | } |
40 | } | 40 | } else { |
41 | else { | ||
42 | setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ | 41 | setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ |
43 | 42 | ||
44 | /* read DIR0 and DIR1 CPU registers */ | 43 | /* read DIR0 and DIR1 CPU registers */ |
@@ -86,7 +85,7 @@ static char cyrix_model_mult2[] __cpuinitdata = "12233445"; | |||
86 | static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c) | 85 | static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c) |
87 | { | 86 | { |
88 | unsigned long flags; | 87 | unsigned long flags; |
89 | 88 | ||
90 | if (Cx86_dir0_msb == 3) { | 89 | if (Cx86_dir0_msb == 3) { |
91 | unsigned char ccr3, ccr5; | 90 | unsigned char ccr3, ccr5; |
92 | 91 | ||
@@ -132,7 +131,7 @@ static void __cpuinit set_cx86_memwb(void) | |||
132 | /* set 'Not Write-through' */ | 131 | /* set 'Not Write-through' */ |
133 | write_cr0(read_cr0() | X86_CR0_NW); | 132 | write_cr0(read_cr0() | X86_CR0_NW); |
134 | /* CCR2 bit 2: lock NW bit and set WT1 */ | 133 | /* CCR2 bit 2: lock NW bit and set WT1 */ |
135 | setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 ); | 134 | setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14); |
136 | } | 135 | } |
137 | 136 | ||
138 | static void __cpuinit set_cx86_inc(void) | 137 | static void __cpuinit set_cx86_inc(void) |
@@ -148,7 +147,7 @@ static void __cpuinit set_cx86_inc(void) | |||
148 | setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02); | 147 | setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02); |
149 | /* PCR0 -- Performance Control */ | 148 | /* PCR0 -- Performance Control */ |
150 | /* Incrementor Margin 10 */ | 149 | /* Incrementor Margin 10 */ |
151 | setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04); | 150 | setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04); |
152 | setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ | 151 | setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ |
153 | } | 152 | } |
154 | 153 | ||
@@ -167,16 +166,16 @@ static void __cpuinit geode_configure(void) | |||
167 | 166 | ||
168 | ccr3 = getCx86(CX86_CCR3); | 167 | ccr3 = getCx86(CX86_CCR3); |
169 | setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ | 168 | setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ |
170 | 169 | ||
171 | 170 | ||
172 | /* FPU fast, DTE cache, Mem bypass */ | 171 | /* FPU fast, DTE cache, Mem bypass */ |
173 | setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38); | 172 | setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38); |
174 | setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ | 173 | setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ |
175 | 174 | ||
176 | set_cx86_memwb(); | 175 | set_cx86_memwb(); |
177 | set_cx86_reorder(); | 176 | set_cx86_reorder(); |
178 | set_cx86_inc(); | 177 | set_cx86_inc(); |
179 | 178 | ||
180 | local_irq_restore(flags); | 179 | local_irq_restore(flags); |
181 | } | 180 | } |
182 | 181 | ||
@@ -187,12 +186,14 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) | |||
187 | char *buf = c->x86_model_id; | 186 | char *buf = c->x86_model_id; |
188 | const char *p = NULL; | 187 | const char *p = NULL; |
189 | 188 | ||
190 | /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; | 189 | /* |
191 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ | 190 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
191 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway | ||
192 | */ | ||
192 | clear_bit(0*32+31, c->x86_capability); | 193 | clear_bit(0*32+31, c->x86_capability); |
193 | 194 | ||
194 | /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */ | 195 | /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */ |
195 | if ( test_bit(1*32+24, c->x86_capability) ) { | 196 | if (test_bit(1*32+24, c->x86_capability)) { |
196 | clear_bit(1*32+24, c->x86_capability); | 197 | clear_bit(1*32+24, c->x86_capability); |
197 | set_bit(X86_FEATURE_CXMMX, c->x86_capability); | 198 | set_bit(X86_FEATURE_CXMMX, c->x86_capability); |
198 | } | 199 | } |
@@ -213,7 +214,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) | |||
213 | * the model, multiplier and stepping. Black magic included, | 214 | * the model, multiplier and stepping. Black magic included, |
214 | * to make the silicon step/rev numbers match the printed ones. | 215 | * to make the silicon step/rev numbers match the printed ones. |
215 | */ | 216 | */ |
216 | 217 | ||
217 | switch (dir0_msn) { | 218 | switch (dir0_msn) { |
218 | unsigned char tmp; | 219 | unsigned char tmp; |
219 | 220 | ||
@@ -250,17 +251,18 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) | |||
250 | #ifdef CONFIG_PCI | 251 | #ifdef CONFIG_PCI |
251 | { | 252 | { |
252 | u32 vendor, device; | 253 | u32 vendor, device; |
253 | /* It isn't really a PCI quirk directly, but the cure is the | 254 | /* |
254 | same. The MediaGX has deep magic SMM stuff that handles the | 255 | * It isn't really a PCI quirk directly, but the cure is the |
255 | SB emulation. It throws away the fifo on disable_dma() which | 256 | * same. The MediaGX has deep magic SMM stuff that handles the |
256 | is wrong and ruins the audio. | 257 | * SB emulation. It throws away the fifo on disable_dma() which |
257 | 258 | * is wrong and ruins the audio. | |
258 | Bug2: VSA1 has a wrap bug so that using maximum sized DMA | 259 | * |
259 | causes bad things. According to NatSemi VSA2 has another | 260 | * Bug2: VSA1 has a wrap bug so that using maximum sized DMA |
260 | bug to do with 'hlt'. I've not seen any boards using VSA2 | 261 | * causes bad things. According to NatSemi VSA2 has another |
261 | and X doesn't seem to support it either so who cares 8). | 262 | * bug to do with 'hlt'. I've not seen any boards using VSA2 |
262 | VSA1 we work around however. | 263 | * and X doesn't seem to support it either so who cares 8). |
263 | */ | 264 | * VSA1 we work around however. |
265 | */ | ||
264 | 266 | ||
265 | printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n"); | 267 | printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n"); |
266 | isa_dma_bridge_buggy = 2; | 268 | isa_dma_bridge_buggy = 2; |
@@ -273,52 +275,48 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) | |||
273 | 275 | ||
274 | /* | 276 | /* |
275 | * The 5510/5520 companion chips have a funky PIT. | 277 | * The 5510/5520 companion chips have a funky PIT. |
276 | */ | 278 | */ |
277 | if (vendor == PCI_VENDOR_ID_CYRIX && | 279 | if (vendor == PCI_VENDOR_ID_CYRIX && |
278 | (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520)) | 280 | (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520)) |
279 | mark_tsc_unstable("cyrix 5510/5520 detected"); | 281 | mark_tsc_unstable("cyrix 5510/5520 detected"); |
280 | } | 282 | } |
281 | #endif | 283 | #endif |
282 | c->x86_cache_size=16; /* Yep 16K integrated cache thats it */ | 284 | c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */ |
283 | 285 | ||
284 | /* GXm supports extended cpuid levels 'ala' AMD */ | 286 | /* GXm supports extended cpuid levels 'ala' AMD */ |
285 | if (c->cpuid_level == 2) { | 287 | if (c->cpuid_level == 2) { |
286 | /* Enable cxMMX extensions (GX1 Datasheet 54) */ | 288 | /* Enable cxMMX extensions (GX1 Datasheet 54) */ |
287 | setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1); | 289 | setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1); |
288 | 290 | ||
289 | /* | 291 | /* |
290 | * GXm : 0x30 ... 0x5f GXm datasheet 51 | 292 | * GXm : 0x30 ... 0x5f GXm datasheet 51 |
291 | * GXlv: 0x6x GXlv datasheet 54 | 293 | * GXlv: 0x6x GXlv datasheet 54 |
292 | * ? : 0x7x | 294 | * ? : 0x7x |
293 | * GX1 : 0x8x GX1 datasheet 56 | 295 | * GX1 : 0x8x GX1 datasheet 56 |
294 | */ | 296 | */ |
295 | if((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <=dir1 && dir1 <= 0x8f)) | 297 | if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f)) |
296 | geode_configure(); | 298 | geode_configure(); |
297 | get_model_name(c); /* get CPU marketing name */ | 299 | get_model_name(c); /* get CPU marketing name */ |
298 | return; | 300 | return; |
299 | } | 301 | } else { /* MediaGX */ |
300 | else { /* MediaGX */ | ||
301 | Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4'; | 302 | Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4'; |
302 | p = Cx86_cb+2; | 303 | p = Cx86_cb+2; |
303 | c->x86_model = (dir1 & 0x20) ? 1 : 2; | 304 | c->x86_model = (dir1 & 0x20) ? 1 : 2; |
304 | } | 305 | } |
305 | break; | 306 | break; |
306 | 307 | ||
307 | case 5: /* 6x86MX/M II */ | 308 | case 5: /* 6x86MX/M II */ |
308 | if (dir1 > 7) | 309 | if (dir1 > 7) { |
309 | { | ||
310 | dir0_msn++; /* M II */ | 310 | dir0_msn++; /* M II */ |
311 | /* Enable MMX extensions (App note 108) */ | 311 | /* Enable MMX extensions (App note 108) */ |
312 | setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1); | 312 | setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1); |
313 | } | 313 | } else { |
314 | else | ||
315 | { | ||
316 | c->coma_bug = 1; /* 6x86MX, it has the bug. */ | 314 | c->coma_bug = 1; /* 6x86MX, it has the bug. */ |
317 | } | 315 | } |
318 | tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; | 316 | tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; |
319 | Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]; | 317 | Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]; |
320 | p = Cx86_cb+tmp; | 318 | p = Cx86_cb+tmp; |
321 | if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) | 319 | if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) |
322 | (c->x86_model)++; | 320 | (c->x86_model)++; |
323 | /* Emulate MTRRs using Cyrix's ARRs. */ | 321 | /* Emulate MTRRs using Cyrix's ARRs. */ |
324 | set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability); | 322 | set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability); |
@@ -343,7 +341,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) | |||
343 | break; | 341 | break; |
344 | } | 342 | } |
345 | strcpy(buf, Cx86_model[dir0_msn & 7]); | 343 | strcpy(buf, Cx86_model[dir0_msn & 7]); |
346 | if (p) strcat(buf, p); | 344 | if (p) |
345 | strcat(buf, p); | ||
347 | return; | 346 | return; |
348 | } | 347 | } |
349 | 348 | ||
@@ -352,7 +351,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) | |||
352 | */ | 351 | */ |
353 | static void __cpuinit init_nsc(struct cpuinfo_x86 *c) | 352 | static void __cpuinit init_nsc(struct cpuinfo_x86 *c) |
354 | { | 353 | { |
355 | /* There may be GX1 processors in the wild that are branded | 354 | /* |
355 | * There may be GX1 processors in the wild that are branded | ||
356 | * NSC and not Cyrix. | 356 | * NSC and not Cyrix. |
357 | * | 357 | * |
358 | * This function only handles the GX processor, and kicks every | 358 | * This function only handles the GX processor, and kicks every |
@@ -377,7 +377,7 @@ static void __cpuinit init_nsc(struct cpuinfo_x86 *c) | |||
377 | * by the fact that they preserve the flags across the division of 5/2. | 377 | * by the fact that they preserve the flags across the division of 5/2. |
378 | * PII and PPro exhibit this behavior too, but they have cpuid available. | 378 | * PII and PPro exhibit this behavior too, but they have cpuid available. |
379 | */ | 379 | */ |
380 | 380 | ||
381 | /* | 381 | /* |
382 | * Perform the Cyrix 5/2 test. A Cyrix won't change | 382 | * Perform the Cyrix 5/2 test. A Cyrix won't change |
383 | * the flags, while other 486 chips will. | 383 | * the flags, while other 486 chips will. |
@@ -398,27 +398,26 @@ static inline int test_cyrix_52div(void) | |||
398 | return (unsigned char) (test >> 8) == 0x02; | 398 | return (unsigned char) (test >> 8) == 0x02; |
399 | } | 399 | } |
400 | 400 | ||
401 | static void __cpuinit cyrix_identify(struct cpuinfo_x86 * c) | 401 | static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c) |
402 | { | 402 | { |
403 | /* Detect Cyrix with disabled CPUID */ | 403 | /* Detect Cyrix with disabled CPUID */ |
404 | if ( c->x86 == 4 && test_cyrix_52div() ) { | 404 | if (c->x86 == 4 && test_cyrix_52div()) { |
405 | unsigned char dir0, dir1; | 405 | unsigned char dir0, dir1; |
406 | 406 | ||
407 | strcpy(c->x86_vendor_id, "CyrixInstead"); | 407 | strcpy(c->x86_vendor_id, "CyrixInstead"); |
408 | c->x86_vendor = X86_VENDOR_CYRIX; | 408 | c->x86_vendor = X86_VENDOR_CYRIX; |
409 | 409 | ||
410 | /* Actually enable cpuid on the older cyrix */ | 410 | /* Actually enable cpuid on the older cyrix */ |
411 | 411 | ||
412 | /* Retrieve CPU revisions */ | 412 | /* Retrieve CPU revisions */ |
413 | 413 | ||
414 | do_cyrix_devid(&dir0, &dir1); | 414 | do_cyrix_devid(&dir0, &dir1); |
415 | 415 | ||
416 | dir0>>=4; | 416 | dir0 >>= 4; |
417 | 417 | ||
418 | /* Check it is an affected model */ | 418 | /* Check it is an affected model */ |
419 | 419 | ||
420 | if (dir0 == 5 || dir0 == 3) | 420 | if (dir0 == 5 || dir0 == 3) { |
421 | { | ||
422 | unsigned char ccr3; | 421 | unsigned char ccr3; |
423 | unsigned long flags; | 422 | unsigned long flags; |
424 | printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n"); | 423 | printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n"); |
@@ -434,7 +433,7 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 * c) | |||
434 | 433 | ||
435 | static struct cpu_dev cyrix_cpu_dev __cpuinitdata = { | 434 | static struct cpu_dev cyrix_cpu_dev __cpuinitdata = { |
436 | .c_vendor = "Cyrix", | 435 | .c_vendor = "Cyrix", |
437 | .c_ident = { "CyrixInstead" }, | 436 | .c_ident = { "CyrixInstead" }, |
438 | .c_init = init_cyrix, | 437 | .c_init = init_cyrix, |
439 | .c_identify = cyrix_identify, | 438 | .c_identify = cyrix_identify, |
440 | }; | 439 | }; |
@@ -443,7 +442,7 @@ cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev); | |||
443 | 442 | ||
444 | static struct cpu_dev nsc_cpu_dev __cpuinitdata = { | 443 | static struct cpu_dev nsc_cpu_dev __cpuinitdata = { |
445 | .c_vendor = "NSC", | 444 | .c_vendor = "NSC", |
446 | .c_ident = { "Geode by NSC" }, | 445 | .c_ident = { "Geode by NSC" }, |
447 | .c_init = init_nsc, | 446 | .c_init = init_nsc, |
448 | }; | 447 | }; |
449 | 448 | ||