diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2008-06-09 11:27:20 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-06-10 09:52:14 -0400 |
commit | 732d7be17b98ebfd59e5864c3490f19856fa832c (patch) | |
tree | 404a3af449d073675312032b6182f9400e64a091 /arch/x86/kernel/cpu/amd.c | |
parent | aa83f3f2cfc74d66d01b1d2eb1485ea1103a0f4e (diff) |
x86: use cpuinfo to check for interrupt pending message msr
Simplify code: no need to do a cpuid(1) again. The cpuinfo structure
has all necessary information already.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/amd.c')
-rw-r--r-- | arch/x86/kernel/cpu/amd.c | 41 |
1 files changed, 15 insertions, 26 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 30b5055be355..e76b49e7a916 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c | |||
@@ -25,35 +25,24 @@ extern void vide(void); | |||
25 | __asm__(".align 4\nvide: ret"); | 25 | __asm__(".align 4\nvide: ret"); |
26 | 26 | ||
27 | #ifdef CONFIG_X86_LOCAL_APIC | 27 | #ifdef CONFIG_X86_LOCAL_APIC |
28 | #define CPUID_PROCESSOR_SIGNATURE 1 | ||
29 | #define CPUID_XFAM 0x0ff00000 | ||
30 | #define CPUID_XFAM_K8 0x00000000 | ||
31 | #define CPUID_XFAM_10H 0x00100000 | ||
32 | #define CPUID_XFAM_11H 0x00200000 | ||
33 | #define CPUID_XMOD 0x000f0000 | ||
34 | #define CPUID_XMOD_REV_F 0x00040000 | ||
35 | 28 | ||
36 | /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ | 29 | /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ |
37 | static __cpuinit int amd_apic_timer_broken(void) | 30 | static __cpuinit int amd_apic_timer_broken(struct cpuinfo_x86 *c) |
38 | { | 31 | { |
39 | u32 lo, hi; | 32 | u32 lo, hi; |
40 | u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); | 33 | |
41 | switch (eax & CPUID_XFAM) { | 34 | if (c->x86 < 0x0F) |
42 | case CPUID_XFAM_K8: | 35 | return 0; |
43 | if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) | 36 | |
44 | break; | 37 | /* Family 0x0f models < rev F do not have this MSR */ |
45 | case CPUID_XFAM_10H: | 38 | if (c->x86 == 0x0f && c->x86_model < 0x40) |
46 | case CPUID_XFAM_11H: | 39 | return 0; |
47 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | 40 | |
48 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { | 41 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); |
49 | if (smp_processor_id() != boot_cpu_physical_apicid) | 42 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
50 | printk(KERN_INFO "AMD C1E detected late. " | 43 | if (smp_processor_id() != boot_cpu_physical_apicid) |
51 | " Force timer broadcast.\n"); | 44 | printk(KERN_INFO "AMD C1E detected late. " |
52 | return 1; | 45 | "Force timer broadcast.\n"); |
53 | } | ||
54 | break; | ||
55 | default: | ||
56 | /* err on the side of caution */ | ||
57 | return 1; | 46 | return 1; |
58 | } | 47 | } |
59 | return 0; | 48 | return 0; |
@@ -297,7 +286,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) | |||
297 | } | 286 | } |
298 | 287 | ||
299 | #ifdef CONFIG_X86_LOCAL_APIC | 288 | #ifdef CONFIG_X86_LOCAL_APIC |
300 | if (amd_apic_timer_broken()) | 289 | if (amd_apic_timer_broken(c)) |
301 | local_apic_timer_disabled = 1; | 290 | local_apic_timer_disabled = 1; |
302 | #endif | 291 | #endif |
303 | 292 | ||