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authorSuresh Siddha <suresh.b.siddha@intel.com>2008-07-10 14:16:49 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-12 02:44:59 -0400
commit1b374e4d6f8b3eb2fcd034fcc24ea8ba1dfde7aa (patch)
treefaf5aa00e344e473957206bc82ffbb746e438d0b /arch/x86/kernel/apic_64.c
parent2d7a66d02e11af9ab8e16c76d22767e622b4e3d7 (diff)
x64, x2apic/intr-remap: basic apic ops support
Introduce basic apic operations which handle the apic programming. This will be used later to introduce another specific operations for x2apic. For the perfomance critial accesses like IPI's, EOI etc, we use the native operations as they are already referenced by different indirections like genapic, irq_chip etc. 64bit Paravirt ops can also define their apic operations accordingly. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/apic_64.c')
-rw-r--r--arch/x86/kernel/apic_64.c34
1 files changed, 32 insertions, 2 deletions
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index 3963f590c3d4..9bb040689b31 100644
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -119,13 +119,13 @@ static int modern_apic(void)
119 return lapic_get_version() >= 0x14; 119 return lapic_get_version() >= 0x14;
120} 120}
121 121
122void apic_wait_icr_idle(void) 122void xapic_wait_icr_idle(void)
123{ 123{
124 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 124 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
125 cpu_relax(); 125 cpu_relax();
126} 126}
127 127
128u32 safe_apic_wait_icr_idle(void) 128u32 safe_xapic_wait_icr_idle(void)
129{ 129{
130 u32 send_status; 130 u32 send_status;
131 int timeout; 131 int timeout;
@@ -141,6 +141,36 @@ u32 safe_apic_wait_icr_idle(void)
141 return send_status; 141 return send_status;
142} 142}
143 143
144void xapic_icr_write(u32 low, u32 id)
145{
146 apic_write(APIC_ICR2, id << 24);
147 apic_write(APIC_ICR, low);
148}
149
150u64 xapic_icr_read(void)
151{
152 u32 icr1, icr2;
153
154 icr2 = apic_read(APIC_ICR2);
155 icr1 = apic_read(APIC_ICR);
156
157 return (icr1 | ((u64)icr2 << 32));
158}
159
160static struct apic_ops xapic_ops = {
161 .read = native_apic_mem_read,
162 .write = native_apic_mem_write,
163 .write_atomic = native_apic_mem_write_atomic,
164 .icr_read = xapic_icr_read,
165 .icr_write = xapic_icr_write,
166 .wait_icr_idle = xapic_wait_icr_idle,
167 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
168};
169
170struct apic_ops __read_mostly *apic_ops = &xapic_ops;
171
172EXPORT_SYMBOL_GPL(apic_ops);
173
144/** 174/**
145 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 175 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
146 */ 176 */